I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator

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2 I/F Memory Array Control Row/Column Decoder I/F Memory Array DRAM Voltage Generator

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4 N P P

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6 DRAM

7 a b MC-Tr avcc=2.5vvbb=-1.5vvpp=4.0v bvcc=1.7vvbb=-1.0vvpp=3.0v µ

8 a b

9 BSG a b Vcc=1.7VVsi=0.2VVbb=-0.8VVpp=3.0V) BSG

10 Word Line Line BSG Conv. BL Pair Sense GND GND

11 µ µ

12 I-leak avcc b

13 MC-Tr

14 a b

15 a b

16 - - 33

17 BSG a bdms

18 avcc b c

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21 CDS a b

22 A 1/2-VCC DRAM 1/2-VCC, MOS 1/2-VCC / DRAM / 1.0V a b

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25 µ

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29 C

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31 D

32 agnd bvbb c

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35 a bgnd-well c

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37 A StretchableMemoryMatrix DRAM 16M STDRAM

DRAM DRAM 16M X Y 12 40964096 1 4096 13X/11Y 2048 2 14X/10Y 1024 1/4 15X/9Y 512 1/8

38 DRAM DRAM 16M X Y X/11Y X/10Y /4 15X/9Y 512 1/8 X STretchableMemory Matrix) DRAM STDRAM, B16M-STDRAM IO 16Mb-STDRAM 32k

39 15X/9Y 4 128k 1/128 / X Y I/O I/O N MOS I/O I/O I/O X /Y =15/9 16us/ 512ms IO

40 C 16M DRAM 16M STDRAM X /Y X X /Y 15/9 X /Y 12/12 1/2 1/ M DRAM 1/2 16M STDRAM 512 1/

41 V pp A V pp OUT V dd IN µ

42 V pp IN L P2 A H P1 V A pp OUT B L V dd IN C H OUT H a b a b

43 V pp V pp OUT V dd IN

44 VDC a

45 VDC a b

46 VDC VDC

47 VDC

48 VDC

49 - - 66

50 - - 67

51 VDC a b

52 VDC a VDC bmm-vdc cmm-vdc

53 a b

54 VCI

55 Ext. V dd Ext. V dd P1 /BE V ref Int. V dd Act Decouple C ACT SE BE Ext.Vdd Int.Vdd GND

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58 1) K. Itoh et al., An experimental 1Mb DRAM with on-chip voltage limiter, in ISSCC Dig. Tech. Papers, Feb. 1984, pp ) T. Furuyama et al., A new on-chip voltage converter for submicrometer high-density DRAM s, IEEE J. Solid-State Circuits, vol. 24, June 1986, pp ) H. Hidaka et al., A 34ns 16Mb DRAM with controllable voltage down-converter, IEEE J. Solid-State Circuits, vol. 27, No. 7, July 1992, pp ) M. Horiguchi, et al., Switched-Source-Impedance CMOS Circuit for Low Standby Subthreshold Current Giga-scale LSI s, Symp. VLSI Circuits Digest of Tech. Papers, pp , June ) T. Yamagata et al., Circuit design techniques for low voltage operating and/or giga-scale DRAMs, in ISSCC Dig. Tech. Papers, Feb. 1995, pp ) T. Yamagata et al., Low voltage circuit design techniques for battery-operated and/or giga-scale DRAM s, IEEE J. Solid-State Circuits, vol. 30, Nov. 1995, pp ) M. Asakura et al., A 34ns 256Mb DRAM with boosted sense-ground scheme, in ISSCC Dig. Tech. Papers, Feb. 1994, pp ) M. Asakura et al., An experimental 256-Mb DRAM with boosted sense-ground scheme, IEEE J. Solid-State Circuits, vol. 29, Nov. 1994, pp ) S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, ) Y. Tsukikawa et al., An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAM s, Symp. On VLSI circuit Dig. Tech. Papers, pp , June ) T. Sakurai et al. Hot-carrier generation in submicrometer VLSI environment, IEEE J. Solid-State Circuits, vol. SC-21, Feb ) T. Tsuruda et al., High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI, in IEEE CICC Dig. Tech. Papers, pp , May ) T. Tsuruda et al., High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI s, IEEE J. Solid-State Circuits, vol. 32, March 1997, pp ) S. Miyano et al., Embedded DRAM SOCs and Its Application for MPEG4 Codec LSIs, in Proc. of VLSI Circuits Short Course, June 2001, pp ) C-L. Hwang, et al., A 2.9ns Random Access Cycle Embedded DRAM with a Destructive Read Architecture, Symp. On VLSI circuit Dig. Tech. Papers, June 2002, pp ) S.Tomishima, et al., A 1.0V 230MHz column access embedded DRAM for portable MPEG

59 applications, IEEE Journal of Solid-State Circuits, Vol.36, NO.11, Nov. 2001, pp ) S.Tomishima, et al., A 1.0V 230MHz column access embedded DRAM for portable MPEG applications, ISSCC Dig. Tech. Papers, Feb. 2001, pp ) S. Mutoh, et al., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, Proc. IEEE ASIC Conf. pp , Sept., ) S. Shigematsu, et al., A 1-V high-speed MTCMOS circuit scheme for power-down applications, Symp. VLSI Circuits Digest of Tech. Papers, pp , June, ) S. Mutoh, et al., 1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS, IEEE J. Solid-State Circuits, Vol. pp , Aug., ) S. Mutoh, et al., A 1V Multi-Threshold Voltage CMOS DSP with an Efficient Power Management Technique for Mobile Phone Application, ISSCC Digest Technical Papers, pp , Feb., ) T. Kobayashi, et al., Self-Adjusting Threshold-Voltage Scheme (SATS) for Low-Voltage High Speed Operation, Proc. CICC. pp , May., ) K. Seta, et al., 50% Active-Power Saving without Speed Degradation using Standby Power Reduction (SPR) Circuit, ISSCC Digest Technical Papers, pp , Feb., ) T. Kuroda, et al., A 0.9V 150MHz 10mW 4 mm 2 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage Scheme, ISSCC Digest Technical Papers, pp , Feb., ) T. Kuroda, et al., A 0.9-V, 150-MHz, 10-mW, 4 mm 2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme, IEEE J. Solid-State Circuits, Vol. pp , Nov., ) T. Kuroda, et al., A High-Speed Low-Power 0.3µm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme, Proc. CICC. pp , May., ) M. Mizuno, et al., Elastic-Vt CMOS Circuits for Multiple On-Chip Power Control, ISSCC Digest Technical Papers, pp , Feb., ) W. C. Ward, Volume production of unique plastic surface-mount modules for the IBM 80-ns 1-Mbit DRAM chip by area wire bond technique, ECC. Papers, 1988, pp ) H. Yamauchi, et al., A 20ns battery-operated 16 Mb CMOS DRAM, in ISSCC Dig. Tech. Papers, Feb. 1993, pp ) K. Noda, et al., A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs, Symp. On VLSI circuit Dig. Tech. Papers, pp , June ) T. Ooishi, et al., A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories, IEEE J. Solid-State Circuits, vol. 31, No. 4, April 1996, pp

60 34) T. Ooishi, et al., A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency DRAMs, Symp. On VLSI circuit Dig. Tech. Papers, pp , June ) T. Kono, et al., A Precharged-Capacitor-Assisted Sensing (PCAS) Scheme with Novel Level Controller for Low-Power DRAM s, IEEE J. Solid-State Circuits, vol. 35, No. 8, Aug. 2000, pp ) T. Kono, et al., A Precharged-Capacitor-Assisted Sensing (PCAS) Scheme with Novel Level Controller for Low-Power DRAM s, Symp. On VLSI circuit Dig. Tech. Papers, pp , June ) S. Tomishima, et al., A blanket source line architecture with triple metal for giga scale memory LSIs, IEICE Trans. Electron., Vol. E79-C, No.7, July 1996, pp

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MPEG Applications 10000 HDTV HDTV: High Definition TV 1000 SDTV: SDTV Standard Definition TV 100 DVD DVD: Digital Video Decoder VP VP: 10 Video Phone 0 16 32 64 128 256 Memory Capacity (Mbit) Data Rate