Core1 FabScalar VerilogHDL Cache Cache FabScalar 1 CoreConnect[2] Wishbone[3] AMBA[4] AMBA 1 AMBA ARM L2 AMBA2.0 AMBA2.0 FabScalar AHB APB AHB AMBA2.0
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- るるみ いさし
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1 AMBA FabScalar FabScalar AMBA AMBA FutureBus Improvement of AMBA Bus Frame-work for Heterogeneos Multi-processor Seto Yusuke 1 Takahiro Sasaki 1 Kazuhiko Ohno 1 Toshio Kondo 1 Abstract: The demand of heterogeneous multi-core processors is increasing in an area of the computer architecture. FabScalar is automatic generation tool for superscalar cores. This tool-set contributes to the construction and verification of heterogeneous systems. But, FabScalar does not have mechanism to generate cache systems and bus systems, which are necessary for multi-core architecture. In this paper, we propose and design a tool to automatically generate bus frame-work for heterogeneous environment. Our verification shows that the bus system generated by the proposed frame-work works correctly. Keywords: Heterogeneous Multi-core AMBA SnoopBus FutureBus 1. N.K.Choudhary FabScalar[1] FabScalar 1 Presently with Graduate School of Information Engineering, Mie University c 2012 Information Processing Society of Japan 1
2 Core1 FabScalar VerilogHDL Cache Cache FabScalar 1 CoreConnect[2] Wishbone[3] AMBA[4] AMBA 1 AMBA ARM L2 AMBA2.0 AMBA2.0 FabScalar AHB APB AHB AMBA2.0 [6] AHB system generator[7] VHDL AMBA2.0 AHB AMBA4.0[5] (AHB)/ (APB) AHB system generator Inst Core0 Data Shared Memory Inst Cache Core2 L2 Cache Data Cache Shared Bus Systems for Heterogeneous Environment c 2012 Information Processing Society of Japan 2
3 ( FabScalar ) if FabScalar FabScalar HDL L2 L3 / AHB system generator AMBA2.0 AMBA2.0 AMBA ARM 4. FabScalar FabScalar AMBA 5.1 AMBA Rev Rev 2.0 SystemVerilog(HDL) / 2 FabScalar 2 5. AMBA ARM MIPS c 2012 Information Processing Society of Japan 3
4 Master0 Master1 Master2 Master3 addr0 addr1 addr2 addr3 wdata0 wdata1 wdata2 wdata3 Cache0 Cache1 Cache2 Cache3 Decoder rdata0 Slave0 Mux_S/M rdata1 Mux_M/S Slave1 2 AMBA Arbiter AMBA AMBA 5.2 AMBA AMBA ( ) AMBA 3 AMBA AMBA AMBA AMBA Master0 Master1 Master2 Master3 from Slave AMBA 6.2 FutureBus Mux_Snoop / 1 MOESI MESI Mux_M/S to Slave from Arbiter addr0 addr1 Snoop_addr addr2 addr3 Arbiter_Snoop c 2012 Information Processing Society of Japan 4
5 Cache0 Cache1 Cache2 Cache3 Master0 Master1 Master2 Master3 Parameter.vh \*** ***\ \* *\ define MASTER_NUM 4 \\ [ ] FutureBus_Signals_0 FB1 FB2 addr3 addr2 addr1 addr0 FB3 Mux_Snoop Snoop_addr FutureBus_Signals Arbiter_Snoop \* *\ define SLAVE_NUM 2 \* *\ define SNOOP_NUM 3 : : [ ] FutureBus[8] FutureBus IEEE MOESI MESI Berkeley Dragon (FutureBus ) Firefly...etc MOESI AMBA MESI Berkeley MOESI ( / ) 7. AMBA SystemVerilog(HDL) 2 AHB system generator / / / 4/2/3 MOESI 8. L2 1 / 16 ( / 1/1 0 ) FutureBus c 2012 Information Processing Society of Japan 5
6 9. 6 A MOESI MESI AMBA (AMBA ) AHB system generator Design compiler(ver SP5) ROHM 0.18µm CMOS 4 / 6/1 1 1,189 [ ] 1,130 [ ] [MHz] [MHz] c 2012 Information Processing Society of Japan 6
7 LSI [1] N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, E. Rotenberg. FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. Proceedings of the 38th IEEE/ACM International Symposium on Computer Architecture (ISCA-38), pp , June [2] IBM: CoreConnect Bus Archirecture, [3] OpenCores: WISHBONE System-on-chip (SoC) Interconnection Architecture for Portable IP Cores, [4] ARM: AMBA (Rev2.0) [5] ARM: AMBA AXI and ACE Protocol Specification, [6] Eric Rotenberg FabScalar Alpha SACSIS [7] OpenCores: AHB system generator [8] P. Sweazey, A. J. Smith. A class of compatible cache consistency protocols and their support by the IEEE Futurebus, Proceedings of the 13th annual international symposium on Computer architecture Vol. 14 No. 2 pp , c 2012 Information Processing Society of Japan 7
FabHetero FabHetero FabHetero FabCache FabCache SPEC2000INT IPC FabCache 0.076%
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1 FabScalar FabCache FabBus FabHetero FabCache FabCache FabCache FabCache FabCache ns 0.1
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