LTC 利得をデジタルでプログラム可能なゼロドリフト高精度計装アンプ

Transcription

1 LTC 利得をデジタルでプログラム可能なゼロドリフト高精度計装アンプ 特長 CMRR.% μ n/ C SPI 電源動作 :.~±. ノイズ :.μ P-P (.Hz~Hz 標準) ピン SSOP パッケージと ピン DFN パッケージ アプリケーション 熱電対アンプ 電子式秤 医療用機器 ストレイン ゲージ アンプ 高分解能データ収集 概要 LTC CMRR μ n/ C LTC charge baanced samped data LTC. SSOP DFN L LT LTC LTM Linear Technoogy および Linear のロゴはリニアテクノロジー社の登録商標です その他すべての商標の所有権は それぞれの所有者に帰属します 標準的応用例 LTC SSOP PACKAGE IN OUT IN _ C S C H C F SENSE R < k RESISTOR ARRAY PARALLEL_SERIAL µp TO OTHER DEICES CS(D) D IN (D) CLK(D) D OUT (D) MUX Q Q Q Q Q Q Q Q -BIT SHIFT-REGISTER -BIT LATCH HOLD_THRU.µF SHDN TA fb

2 LTC 絶対最大定格 Note 全電源電圧 ( ~ )... 入力電流... ±ma IN.... IN デジタル入力電圧... ~ 動作温度範囲 LTCC... C ~ C LTCI... C~ C LTCH... C ~ C 動作温度範囲 (GN パッケージ )... C (DFN パッケージ )... C 保存温度 (GN パッケージ )... C ~ C (DFN パッケージ )... C ~ C リード温度 ( 半田付け 秒 )... C ピン配置 IN IN CS(D) D IN (D) CLK(D) TOP IEW OUT PARALLEL_SERIAL D OUT (D) DE PACKAGE -LEAD (mm mm) PLASTIC DFN T JMAX = C, θ JA = C/W EXPOSED PAD (PIN ) IS, MUST BE SOLDERED TO PCB TOP IEW SHDN IN IN HOLD_THRU CS(D) D IN (D) CLK(D) OUT SENSE NC PARALLEL_SERIAL D OUT (D) GN PACKAGE -LEAD NARROW PLASTIC SSOP T JMAX = C, θ JA = C/W 発注情報 LTCCDE#PBF LTCCDE#TRPBF -Lead (mm mm) Pastic DFN C to C LTCIDE#PBF LTCIDE#TRPBF I -Lead (mm mm) Pastic DFN C to C LTCCGN#PBF LTCCGN#TRPBF -Lead Narrow Pastic SSOP C to C LTCIGN#PBF LTCIGN#TRPBF I -Lead Narrow Pastic SSOP C to C LTCHGN#PBF LTCHGN#TRPBF H -Lead Narrow Pastic SSOP C to C LTCCDE LTCCDE#TR -Lead (mm mm) Pastic DFN C to C LTCIDE LTCIDE#TR I -Lead (mm mm) Pastic DFN C to C LTCCGN LTCCGN#TR -Lead Narrow Pastic SSOP C to C LTCIGN LTCIGN#TR I -Lead Narrow Pastic SSOP C to C LTCHGN LTCHGN#TR H -Lead Narrow Pastic SSOP C to C さらに広い動作温度範囲で規定されるデバイスについては 弊社または弊社代理店にお問い合わせください 鉛フリー仕様の製品マーキングの詳細については をご覧ください テープアンドリールの仕様の詳細については をご覧ください fb

3 LTC 電気的特性 T A = C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS =, =, = m Gain Error (Note ) A = (R L =k).. % Gain Error (Note ) A = to (R L = k).. % Gain Error (Note ) A = to (R L = k)... % Gain Error (Note ) A =, (R L = k).. % Gain Noninearity A = ppm OS Input Offset otage (Note ) CM = m ± µ Average Input Offset Drift (Note ) T A = C to C T A = C to C I B Average Input Bias Current (Note ) CM =. na I OS Average Input Offset Current (Note ) CM =.. na en Input Noise otage DC to Hz. µ P-P =, =, = m CMRR Common Mode Rejection Ratio A =, CM = to, LTCC A =, CM =. to., LTCI A =, CM = to, LTCI A =, CM =. to., LTCH A =, CM = to., LTCH PSRR Power Suppy Rejection Ratio (Note ) S =. to Output otage Swing High (Referenced to ) Sourcing µa Sourcing ma Output otage Swing Low (Referenced to ) Sinking µa Sinking ma Suppy Current, Parae Mode No Load at OUT, CM = m.. ma Suppy Current, Seria Mode (Note ) Suppy Current Shutdown No Load at OUT, Capacitive Load at D OUT (C L ) = pf, Continuous CLK Frequency = MHz, CS = LOW, Gain Contro Code = SHDN =. (Hardware Shutdown) SHDN =, Gain Contro Code = (Software Shutdown).... ± ± n/ C n/ C m m.. ma SHDN Input High. SHDN Input Low SHDN and HOLD_THRU Input Current (Note ) µa Interna Op Amp Gain Bandwidth khz Sew Rate. /µs Interna Samping Frequency khz =, =, = m Gain Error (Note ) A = (R L = k).. % Gain Error (Note ) A = to (R L = k).. % Gain Error (Note ) A = to (R L = k)... % Gain Error (Note ) A =, (R L = k). % Gain Noninearity A = ppm µa µa fb

4 LTC 電気的特性 T A = C OS Input Offset otage (Note ) CM = m ± µ Average Input Offset Drift (Note ) T A = C to C T A = C to C ± ± Average Input Bias Current (Note ) CM =. na I OS Average Input Offset Current (Note ) CM =.. na CMRR Common Mode Rejection Ratio A =, CM = to, LTCC A =, CM =. to., LTCI A =, CM = to, LTCI A =, CM =. to., LTCH A =, CM = to., LTCH PSRR Power Suppy Rejection Ratio (Note ) S =. to Output otage Swing High Sourcing µa Sourcing ma Output otage Swing Low Sinking µa Sinking ma =, =, = m Suppy Current, Parae Mode No Load at OUT, CM = m.. ma Suppy Current, Seria Mode (Note ) Suppy Current, Shutdown No Load at OUT, Capacitive Load at D OUT (C L ) = pf, Continuous CLK Frequency = MHz, CS = LOW, Gain Contro Code = SHDN =. (Hardware Shutdown) SHDN =, Gain Contro Code = (Software Shutdown).... n/ C n/ C m m. ma SHDN Input High. SHDN Input Low SHDN and HOLD_THRU Input Current (Note ) µa Interna Op Amp Gain Bandwidth khz Sew Rate. /µs Interna Samping Frequency khz =, =, = Gain Error (Note ) A = (R L = k).. % Gain Error (Note ) A = to (R L = k).. % Gain Error (Note ) A = to (R L = k)... % Gain Error (Note ) A =, (R L = k). % Gain Noninearity A = ppm OS Input Offset otage (Note ) CM = m ± µ Average Input Offset Drift (Note ) T A = C to C T A = C to C I OS Average Input Bias Current (Note ) CM = na Average Input Offset Current (Note ) CM =. na ± ± µa µa n/ C n/ C fb

5 LTC 電気的特性 T A = C CMRR Common Mode Rejection Ratio A =, CM = to, LTCC A =, CM =. to., LTCI A =, CM = to, LTCI A =, CM =. to., LTCH A =, CM = to., LTCH PSRR Power Suppy Rejection Ratio (Note ) S =. to Output otage Swing High Sourcing µa Sourcing ma Output otage Swing Low Sinking µa Sinking ma Suppy Current, Parae Mode No Load, CM = m.. ma Suppy Current, Seria Mode (Note ) Suppy Current, Shutdown No Load at OUT, Capacitive Load at D OUT (C L ) = pf, Continuous CLK Frequency = MHz, CS = LOW, Gain Contro Code = SHDN = (Hardware Shutdown) SHDN =, Gain Contro Code = (Software Shutdown) ma SHDN Input High SHDN Input Low =, =, = SHDN and HOLD_THRU Input Current (Note ) µa Interna Op Amp Gain Bandwidth khz Sew Rate. /µs Interna Samping Frequency khz Digita I/O, A Digita I/O otage Referenced to IH Digita Input High otage. IL Digita Input Low otage. OH Digita Output High otage Sourcing µa. OL Digita Output Low otage Sinking µa. Digita Input Leakage =, =, IN = to ± µa Timing, =. to., = (Note ) t D IN aid to CLK Setup ns t D IN aid to CLK Hod ns t CLK Low ns t CLK High ns t CS/LD Puse Width ns t LSB CLK to CS/LD ns t CS/LD Low to CLK ns t D OUT Output Deay C L = pf ns t CLK Low to CS/LD Low ns µa µa fb

6 LTC 電気的特性 T A = C Timing, =. to., = (Note ) t D IN aid to CLK Setup ns t D IN aid to CLK Hod ns t CLK Low ns t CLK High ns t CS/LD Puse Width ns t LSB CLK to CS/LD ns t CS/LD Low to CLK ns t D OUT Output Deay C L = pf ns t CLK Low to CS/LD Low ns Timing, Dua. to. Suppies (Note ) t D IN aid to CLK Setup ns t D IN aid to CLK Hod ns t CLK High ns t CLK Low ns t CS/LD Puse Width ns t LSB CLK to CS/LD ns t CS/LD Low to CLK ns t D OUT Output Deay C L = pf ns t CLK Low to CS/LD Low ns Note : 絶対最大定格に記載された値を超えるストレスはデバイスに永続的損傷を与える可能性がある 長期にわたって絶対最大定格条件に曝すと デバイスの信頼性と寿命に悪影響を与える可能性がある Note : これらのパラメータは ± 電源でテストされる 電源と 電源では それらは設計で保証されている Note : これらのパラメータは設計により保証されている 熱電対効果により 高速自動テスト装置ではこれらの電圧レベルの測定は排除されている OS はテスト装置の能力によって設定されるリミットまで測定される Note : 全ソース抵抗が k 未満であれば 入力バイアス電流 または入力バイアス電流の不整合 または IN - と IN に接続された抵抗の不整合による DC 誤差は生じない Note : PSRR の測定精度は電源バイパス コンデンサがテストされるデバイスにどの位近く置かれているかに依存する このため PSRR は最終テストで緩められたリミット値に対して全数検査される ただし この値はデータシートのリミット値を満たすように設計で保証されている Note : 電源電流はクロック周波数に依存する クロック周波数が高いほど電源電流が大きくなる Note : 設計によって保証されているが テストされない fb

7 LTC 標準的性能特性 INPUT OFFSET OLTAGE (µ) S = =. A = A = A = A = G INPUT OFFSET OLTAGE (µ) S = =. A = A = A = A = G INPUT OFFSET OLTAGE (µ) S = ± = A = A = A = A = G INPUT OFFSET OLTAGE (µ) S = =. A = T A = C T A = C T A = C G INPUT OFFSET OLTAGE (µ) S = =. A = T A = C T A = C T A = C G INPUT OFFSET OLTAGE (µ) S = ± = A = T A = C T A = C T A = C G ADDITIONAL OFFSET (µ) R S R S = k R S = k R S = k R S = k S = =. R S R = R = R S C IN < pf C IN A = R S G ADDITIONAL OFFSET (µ) R S S = =. R = R = R S C IN < pf A = R S C IN R S R S = k R S = k R S = k R S = k G ADDITIONAL OFFSET (µ) R S S = ± = R = R = R S C IN < pf A = R S = k R S C IN R S R S = k R S = k R S = k G fb

8 LTC 標準的性能特性 ADDITIONAL OFFSET (µ) R S S = =. C IN < pf R A = = k, R = k R = k, R = k R = k, R = k R C IN R R = k, R = k G ADDITIONAL OFFSET (µ) R S S = =. C IN < pf A = R = k, R = k R = k, R = k R = k, R = k R C IN R R = k, R = k G ADDITIONAL OFFSET (µ) R S S = ± = C IN < pf A = R = k, R = k R = k, R = k R = k, R = k R R = k, R = k C IN R G INPUT OFFSET OLTAGE (µ) OS OS S = S = ± S = OS (µ) S = IN = IN = A = S = OS (µ) S = IN = IN = A = GAIN NONLINEARITY (ppm) TEMPERATURE ( C) G () = > CMRR S = ±. CM = = R L = k A = OUTPUT OLTAGE () G SUPPLY CURRENT (ma) T A = C T A = C T A = C G SUPPLY OLTAGE () G CMRR (db) () S =,, ± IN = P-P R = k, R = k R R G R = R = k R = R = k R = k, R = k FREQUENCY (Hz) G fb

9 LTC 標準的性能特性 INPUT ERRED NOISE DENSITY (n/ Hz) A = S = ± S = S = FREQUENCY (Hz) INPUT FERED NOISE OLTAGE (µ) Hz S = TIME (s) INPUT FERED NOISE OLTAGE (µ) Hz S = TIME (s) G G G OUTPUT OLTAGE SWING ().. S =, SOURCING.. S =, SOURCING..... S =, SINKING. S =, SINKING.. OUTPUT CURRENT (ma) OUTPUT OLTAGE SWING () S = ± SOURCING SINKING.. OUTPUT CURRENT (ma) SETTLING TIME (ms). S = d OUT = G... SETTLING ACCURACY (%) G G G SETTLING TIME (ms).. S = d OUT =.% ACCURACY... A =. A = T A = C.... T A = C A = GAIN (/) SUPPLY OLTAGE () LOAD RESISTANCE R L (k) G CLOCK FREQUENCY (khz) G ADDITIONAL GAIN ERROR (%) G fb

10 LTC ピン機能 DFN /GN IN / : SHDN GN : SHDN IN / : / : CS D / : TTL L LSB D IN D / : TTL LSB HOLD_THRU GN : TTLHOLD_THRU H D CLK D / : TTL LSB D OUT D / : TTL MSB D OUT D OUT ma / : PARALLEL_SERIAL / : PGA D D CS D DATA D CLK D D OUT D PARALLEL_SERIAL PGA / : PGA OUT / : OUT / ma k / : SENSE GN : PGA OUT SENSE fb

11 LTC ブロック図 GN IN IN C S C H C F GAIN CONTROL OUT SENSE RESISTOR ARRAY PARALLEL_SERIAL MUX -BIT LATCH HOLD_THRU CS(D) D IN (D) CLK(D) D OUT (D) Q Q Q Q Q Q Q Q -BIT SHIFT-REGISTER SHDN BD DFN IN IN C S C H C F GAIN CONTROL OUT RESISTOR ARRAY PARALLEL_SERIAL MUX -BIT LATCH CS(D) D IN (D) CLK(D) D OUT (D) Q Q Q Q Q Q Q Q -BIT SHIFT-REGISTER BD fb

12 LTC タイミング図 t t t t t t CLK t D IN D D D D D D D t CS/LD t D OUT D D D D D D D D PREIOUS BYTE CURRENT BYTE TD 動作 LTC C S DC khz k k C H LTC CF LTC.kHz khz.khz LTC AC PARALLEL_SERIAL D D D D HOLD_THRU L D D PGA HOLD_THRU H D D HOLD_THRU H PGA DFN HOLD_THRU D OUT D D OUT D D OUT D k PARALLEL_SERIAL CS L D IN MSB D OUT CS H LSB D CS H CLK CS LL fb

13 LTC 動作 D OUT D OUT SPI ORD OUT CS H LTCLTC D OUT D IN CLK CS IC CS H SPI LTC IN LTC SHDN IN OUT IN SENSE HOLD_THRU NC CS(D) P/S D IN (D) CLK(D) D OUT (D) OUT.µF µp IN D D D LTC SHDN IN OUT IN SENSE HOLD_THRU NC CS(D) P/S D IN (D) CLK(D) D OUT (D) OUT k.µf D = OUT = IN = IN D OUT D k D > F. PGA CS -BIT GAIN CONTROL CODE -BIT LATCH D OUT (D) D IN Q Q Q Q Q Q Q Q -BIT SHIFT-REGISTER (INTERNAL NODE) F CLK D OUT (D) F. D OUT /D. MSB fb

14 LTC 動作.µF CS D µp IN CLK.µF IN LTC SHDN IN IN # OUT SENSE HOLD_THRU NC CS(D) P/S D IN (D) CLK(D) D OUT (D).µF.µF OUT IN LTC SHDN # IN OUT OUT IN SENSE.µF HOLD_THRU NC CS(D) D IN (D) CLK(D) P/S D OUT (D) D OUT.µF CLK D IN D D D D D D D D D D GAIN CODE FOR # GAIN CODE FOR # CS/LD F. PGA D, D, D, D ~ Gain LTC ( IN IN ). IN IN - IN IN < IN < and < IN <. LTC IN IN. IN <. and IN <... fb

15 LTC 動作 khz C S IN μs C S IN C S = C H = pf N μs N N OUT khz GN L μs N LTC H.%.ms [μs ] ms IN C H C S C H C S IN DC IN DC C S C S IN R S C S IN IN k RS DC DC.μF LTC. XR XR SHDN PGA SHDN PGADFN OUT R R kk LTC R = k OUT I = OUT k = OUT ( R R k) R k R OUT R.µF R F fb

16 LTC 標準的応用例 LTC ON Ω k.µf.µf IN SHDN LTC IN # OUT IN SENSE HOLD_THRU CS NC PAR_SER Ω.µF IN.µF SHDN LTC IN # OUT IN SENSE HOLD_THRU CS NC PAR_SER Ω OUT D IN D IN P (TTL LEELS) DATA SELECT CLOCK CLK D OUT CLK D OUT F. LTC : パッケージ DE/UE DFN mm mm (Reference LTC DWG # -- Rev D). ±.. ±. ( SIDES) R =. TYP R =. TYP. ±.. ±.. ±.. ±.. ±.. ±.. BSC. (NOTE ).. ±. ( SIDES). ±.... ±.. ±.. ±.. BSC. R =.. (UE/DE) DFN RE D NOTE:. JEDEC MO- WGED....mm... ±. GN SSOP. (Reference LTC DWG # --)..* (..). (.). MIN.... (..). ±.. BSC. ±. (. ±.) TYP.. (..).. (..)..** (..).. (..) NOTE:... *.".mm **.".mm.. (..).. (..) TYP. (.) BSC GN (SSOP) fb

17 LTC 改訂履歴 Rev B RE B / 電気的特性 の PSRR の単位を改訂 fb

18 LTC 標準的応用例 X MHz C.µF DDPICLF RC/SDO OSC/ CLKIN RC/SDI/SDA RC/SCK/SCL OSC/ CLKOUT RC/CCP RC/TOSI/CCP RB MCLR/ PP RAS/AN/SS RA/TCLK SS SS MOSI MISO SCLK CS CS k ZETEK ZXMPF R < K BRIDGE SENSOR SHDN LTC IN OUT IN SENSE HOLD_THRU NC CS(D) D IN (D) CLK(D) PAR_SER D OUT (D) C.µF. C.µF CC SDO LTC SCK IN IN CS FO GND k MEASURE STANDBY CONTROL SIGNAL C.µF IN OUT LT-. GND GND C µf F. AD μa 関連製品 LTC CMRR LTC μ pa LTC I S < μa LTC G,.n/ Hz LTC I S = µa LTC- I S = μa LTC SOT- LTC MS LTC GN LTC MS OS μ n/ C LTC MS OS μ n/ C - 東京都千代田区紀尾井町 - 紀尾井町パークビル F TEL - - FAX -- fb LT RE B PRINTED IN JAPAN LINEAR TECHNOLOGY CORPORATION