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2 LeCroy Corporation 700 Chestnut Ridge Road Chestnut Ridge, NY, Tel: (845) , Fax: (845) Internet: by LeCroy Corporation. All rights reserved. LeCroy and other product or brand names are trademarks or requested trademarks of their respective holders. Information in this publication supersedes all earlier versions. Specifications are subject to change without notice RevA

3 MIPI D-PHY...1 MIPI D-PHY...1 MIPI D-PHY...1 Enable...1 Show Decode...2 Setup Acquisition...3 MIPI D-PHY Mode...3 Dp, Dn, CLKp, CLKn...3 Test Parameter Summary Eye Diagram...5 Show Eye...5 Eye Source...5 Bit Rate Find Bit Rate...6 HS (High Speed) Tests...7 HS Clock TO Data Timing...7 HS Data Timing...8 HS Clock Timing...9 HS Common Mode...10 HS Levels...10 HS Rise & Fall LP (Low Power) Tests...12 LP Levels...12 LP Rise & Fall...13 LP Timing...13 LP Slew Rate...14

4 MIPI D-PHY MIPI D-PHY QualiPHY QualiPHY Pass/Fail MIPI D-PHY CSI DSI MIPI D-PHY MIPI D-PHY MIPI D-PHY Analysis MIPI D-PHY MIPI D-PHY MIPI D-PHY Enable, Show Decode, Setup Acquisition Enable Enable MIPI D-PHY 1

5 Show Decode MIPI D-PHY D PHY-D)Enable Show Decode 2

Setup Acquisition Setup Acquisition MIPI D-PHY Mode and Input Selection (on page 6) LP(Low Power) HS(High Speed) SETUP ACQUISITION FOR LP LOW POWER MODE 200 mv/div, -600 mv offset ULPS

6 Setup Acquisition Setup Acquisition MIPI D-PHY Mode and Input Selection (on page 6) LP(Low Power) HS(High Speed) SETUP ACQUISITION FOR LP LOW POWER MODE 200 mv/div, -600 mv offset ULPS Qualified-Pattern SETUP ACQUISITION FOR HS HIGH SPEED MODE 200 mv/div, -600 mv offset MIPI D-PHY Mode MIPI D-PHY Mode Setup Acquisition LP(Low Power) HS(High Speed) Test Parameter Switchboard Dp, Dn, CLKp, CLKn Dp (Data Positive), Dn (Data Negative), CLKp (Clock Positive), CLKn (Clock Negative) 3

7 Test Parameter Summary Test Parameter Summary HS LP MIPI D-PHY / / 4

Eye Diagram MIPI D-PHY Show Eye, Eye Source, Bit Rate, Find Bit Rate Mode Dp (Data Positive), Dn (Data Negative), CLKp (Clock Positive), and CLKn (Clock Negative)Eye Diagram MIPI D-PHY Show Eye Eye

8 Eye Diagram MIPI D-PHY Show Eye, Eye Source, Bit Rate, Find Bit Rate Mode Dp (Data Positive), Dn (Data Negative), CLKp (Clock Positive), and CLKn (Clock Negative)Eye Diagram MIPI D-PHY Show Eye Eye Source HS High Speed Mode Input Selection Eye Diagram HS (Dp (Data Positive), Dn (Data Negative), CLKp (Clock Positive), and CLKn (Clock Negative)) Eye Source Eye Diagram Ddiff (Differential Data) CLKdiff 5

9 (Differential Clock) Bit Rate Find Bit Rate Bit Rate 6

10 HS (High Speed) Tests DPHY1-12 On, Category, and MeasureHS Rise & Fall DATA/CLK-VOD1, DATA/CLK-VOD0, and Find Levels MIPI D-PHY Mode and Input Selection Area Mode HS(High Spee) Dphy1-12 Categories and Measurements LP(Low Power) LP(Low Power) Test HS Clock TO Data Timing HS Clock TO Data Timing Category FirstBit DUT HS Clock TCLK-PRE HS Clock LP HS Data Lane TCLK-POST Data Lane LP DUT Clock Lane HS TCLK-POST TSETUP Setup THOLD Hold 7

11 HS Data Timing HS Data Timing Category TLP-01 HS Data Lane LP-01 (TLPX) THS-PREPARE HS LP-00 (THS-PREPARE) THS-ZERO DUT Data Lane HS Sync HS-0 THS-PREPARE+ZERO THS-PREPARE DUT Data Lane HS Sync(THS-ZERO) HS-0 THS-SYNC HS Sync THS-TRAIL DUT Data Lane TX HS-TX (THS-TRAIL) TEOT DUT Data Lane THS-TRAIL TREOT (a.k.a. TEOT) TREOT DUT LP Data Lane 30%-85% Post-EoT Rise Time (TREOT) THS-EXIT Data Lane HS THS-EXIT LP-11(Stop) 8

12 HS Clock Timing HS Clock Timing Category TLP-01 HS Clock Lane LP-01 (TLPX) TCLK-PREPARE HS TCLK-ZERO LP-00 (TCLK-PREPARE) DUT Clock Lane TCLK-ZERO HS-9 DUT Clock Lane TCLK-PREPARE+ZERO HS-0 DUT Clock Lane TCLK-PREPARE TCLK-TRAIL DUT Clock Lane HS (TCLK-TRAIL) HS-0 TREOT DUT LP Clock Lane 30%-85% Post-EoT Rise Time (TREOT) TEOT DUT Clock Lane HS TCLK-TRAIL Clock Lane SP-11 (TEOT) THS-EXIT HS Clock Lane LP-11(Stop) Uiinst DUT HS Clock Instantaneous Unit Interval(UIINST) HS-Bitrate DUT HS Clock 9

13 HS Common Mode HS Common Mode Category VCMTX-DATA-1 DUT Data & Clock Lanes HS Static VCMTX-DATA-0 VCMTX-CLK-1 Common-Mode Voltages (VCMTX(1), and VCMTX(0)) VCMTX-CLK-0 dvcmtxlf-data dvcmtxlf-clk DUT Data & Clock Lanes HS 50 and 450MHz ( VCMTX(LF)) AC Common-Mode Signal Level Variations dvcmtxhf-data dvcmtxhf-clk DUT Data & Clock Lanes HS 450MHz ( VCMTX(HF)) AC Common-Mode Signal Level Variations HS Levels HS Levels Category VOD-DATA-1 VOD-DATA-0 VOD-CLK-1 VOD-CLK-0 VOHHS-Dp VOHHS-Dn VOHHS-CLKp VOHHS-CLKn DUT Data & Clock Lanes HS Differential Voltages (VOD(0) and VOD(1)) DUT Data & Clock Lanes HS Single-Ended Output High Voltages (VOHHS(DP) and VOHHS(DN)) 10

14 HS Rise & Fall HS Rise & Fall Category DATA/CLK-VOD1, DATA/CLK-VOD0, and Find Levels TR-DATA DUT Data & Clock Lanes HS 20%-80% Rise TR-CLK Time (tr) TF-DATA DUT Data & Clock Lanes HS 80%-20% Fall TF-CLK Time (tf) 11

LP (Low Power) Tests DPHY1-12 On, Category, and Measure LS Rise & Fall Dn-VOH, Dn-VOL, and Find Levels MIPI D-PHY Mode and Input Selection Area Mode LP(Low Power) Dphy1-12 Categories and Measurements

15 LP (Low Power) Tests DPHY1-12 On, Category, and Measure LS Rise & Fall Dn-VOH, Dn-VOL, and Find Levels MIPI D-PHY Mode and Input Selection Area Mode LP(Low Power) Dphy1-12 Categories and Measurements HS (High Speed) HS (High Speed)Tests Category and Measure Combinations for LP Dphy1-12 Dialogs LP Levels LP Levels Category VOH-Dp DUT Data & Clock Lanes LP Thevenin VOH-Dn Output High Level Voltage (VOH) VOH-CLKp VOH-CLKn VOL-Dp DUT Data & Clock Lanes LP hevenin Output Low Level VOL-Dn Voltage (VOL) VOL-CLKp VOL-CLKn 12

16 LP Rise & Fall LP Rise & Fall Category Dn-VOH, Dn-VOL, and Find Levels TRLP-Dp DUT Data & Clock Lanes LP 15%-85% Rise TRLP-Dn Time (TRLP) TRLP-CLKp TRLP-CLKn TFLP-Dp DUT Data & Clock Lanes LP 15%-85% Fall TFLP-Dn Time (TFLP) TFLP-CLKp TFLP-CLKn LP Timing LP Timing Category TLP-PER-Data-500 DUT Data Lane LP XOR Clock TLP-PER-Data-930 (TLP-PER-TX) TLP-PULSE-Data-500 DUT Data Lane LP XOR Clock TLP-PULSE-Data-930 (TLP-PULSE-TX) FIRST-TLP-PULSE-Data-500 FIRST-TLP-PULSE-Data-930 LAST-TLP-PULSE-Data-500 LAST-TLP-PULSE-Data

17 LP Slew Rate LP Slew Rate Category SR-MAX-Dp DUT Data & Clock Lanes LP SR-MAX-Dn Slew Rate ( V/ tsr) SR-MAX-CLKp SR-MAX-CLKn SR-FALL-MIN-Dp SR-FALL-MIN-Dn SR-FALL-MIN-CLKp SR-FALL-MIN-CLKn SR-RISE MIN-Dp SR-RISE MIN-Dn SR-RISE MIN-CLKp SR-RISE MIN-CLKn SR-RISE MIN-Dp SR-RISE MIN-Dn SR-RISE MIN-CLKp SR-RISE MIN-CLKn 14

Agilent U7238A MIPI D-PHY Infiniium Data Sheet エンベディッド D-PHY データリンクの検証とデバッグ Agilent U7238A MIPI D-PHY Infiniium D-PHY CSI DSI D-PHY U7238A MIPI D-PHY

Agilent U7238A MIPI D-PHY Infiniium Data Sheet エンベディッド D-PHY データリンクの検証とデバッグ Agilent U7238A MIPI D-PHY Infiniium D-PHY CSI DSI D-PHY MIPI Alliance Specification for D-PHY v0.90.00 Section 8 4 GHz TX MIPI