(CERN) Large Hadron Collider (LHC) 7 TeV ATLAS 2023 High Luminosity Large Hadron Collider (HL-LHC) ATLAS HL-LHC 2 SVX4 ASIC SVX4 SVX4 DAQ SVX4 DAQ
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1 ATLAS
2 (CERN) Large Hadron Collider (LHC) 7 TeV ATLAS 2023 High Luminosity Large Hadron Collider (HL-LHC) ATLAS HL-LHC 2 SVX4 ASIC SVX4 SVX4 DAQ SVX4 DAQ
3 LHC ATLAS LHC HL-LHC HL-LHC ASIC: SVX Front-end Back-end DØ MODE CDF MODE Operation cycle Initialize Mode Acquire Mode Digitize Mode Readout Mode Daisy Chain SVX
4 3.4.1 Daisy Chain Configuration Daisy Chain DAQ SEABAS SEABAS DAQ RBCP DAQ SVX4 BOARD Version 1: DAQ DAQ SEABAS - DAUGHTER BOARD SVX4 BOARD Version 2: A SVX4 Configuration register 90 2
5 1.1 LHC ATLAS SCT LHC HL-LHC ASIC ASIC PC ASIC PC ASIC Pixel SVX SVX4 Front-end Back-end
6 3.3 Preamp FECLK Preamp pipeline Pipeline Wilkinson ADC SVX SVX4 Readout Mode BUS SVX Initialize Mode PRin Configuration parameter FECLK PRin SVX4 Configuration register Pipeline SVX Acquire Mode Digitize Mode Readout Mode Daisy chain SVX Daisy Chain Configuration SVX4 Configuration register Configuration Daisy Chain SVX4 PRin PRout Token SEABAS SEABAS PC bit stream FPGA SVX SEABAS Control RAM bit stream Control RAM Control RAM bit straem Control RAM. 54 4
7 4.6 Config RAM Control RAM Config RAM bit stream Config RAM bit stream DAQ RBCP [6] SVX4 BOARD V1 SEABAS SVX4 BOARD V1 SVX Configuration bit stream SVX4 bit stream SVX Readout Mode BUS 3.1 SVX ADC ADC 48 ADC 128 ADC Ramp Pedestal RampPed AVDD VCAL ADC RMS Data sparsification ADC 120 ADC ADC ADC RMS SEABAS - DAUGHTER BOARD SVX4 BOARD V SVX4 BOARD V2 DAUGHTER BOARD / IC (a), (b), (c), (d)
8 5.18 DAUGHTER BOARD SEABAS SVX4 BOARD V SVX SVX4 SEABAS SVX4 ADC (a): SVX4 (b): SVX4 BOARD V1 SVX4 AGND SVX
9 SVX SVX4 DØ MODE BUS (DØ MODE) SVX4 BOARD V A.1 Configuration parameter A.2 Configuration parameter A.3 Configuration parameter
10 第 1 章 序論 1.1 LHC Large Hadron Collider (LHC) は 欧州原子核研究機構 (CERN) にある陽子 陽子 衝突型の円形加速器である (図 1.1) LHC 実験の最大の特徴は 最高でビームエネ ルギー 7 TeV の陽子同士 重心系エネルギー 14 TeV を衝突させることができる史 上最高エネルギーの素粒子実験であることである LHC は 2009 年から稼働を始め 現在は重心系エネルギー 8 TeV で陽子同士を衝突させている 2013 年からおよそ 1 年半 加速器の調整のため実験を中断した後 重心系エネルギーを 13 TeV 程度まで 上げて実験を再開する予定である 図 1.1: LHC 史上最高のエネルギーまで加速した陽子同士を衝突させることにより 今まで観 測することができなかった物理現象を観測することを目的としている 最も注目され ているのは まだ存在が確認されていないヒッグス粒子についての研究である ヒッ グス機構は ゲージ不変性を保ちつつゲージボソンが質量をもつことを説明する理 論であり ヒッグス場というスカラー場の導入によってゲージボソンやフェルミオン 8
11 が質量を獲得したことを説明するものである LHC ではヒッグス粒子の発見を目指 しており ヒッグス粒子が発見できれば 次にヒッグス粒子の質量や ゲージボソン およびフェルミオンとの結合定数を求め 標準理論で説明されるヒッグス粒子の性 質と一致するかを調べる ヒッグス粒子はその存在が標準理論で予言されているが ヒッグス粒子の質量は 輻射補正によって O(1026 ) GeV2 程度の補正を受けていると考えられる (fine tuning 問題) これを説明する有力な理論が超対称性理論 (SUSY) である 超対称性理論に よると 標準理論で扱う粒子のスーパーパートナーとなる超対称粒子が存在するは ずであり それを LHC によって発見することを目指す また 史上最高エネルギーでの衝突実験では ブラックホール生成や余剰次元な ど SUSY 以外の標準理論を越えた物理現象の探索も行っている 1.2 ATLAS 実験 A Toroidal Lhc ApparatuS (ATLAS) 検出器 [1] は LHC の衝突点の１つに置かれ た大型汎用粒子検出器であり これを用いて前節で述べた物理現象の観測を目指す 実験が ATLAS 実験である ATLAS 検出器は内部飛跡検出器 ソレノイド磁石 カ ロリメータ ミューオン検出器 トロイド磁石で構成している ATLAS 検出器の構 造を図 1.2 に示す The ATLAS detector is nominally forward-backward symmetric with respect to the interaction point. The magnet configuration comprises a thin superconducting solenoid surrounding the inner-detector cavity, and three large superconducting toroids (one barrel and two end-caps) ar9 ranged with an eight-fold azimuthal symmetry around the calorimeters. This fundamental choice has driven the design of the rest of the detector. The inner detector is immersed in a 2 T solenoidal field. Pattern recognition, momentum and vertex measurements, and electron identification are achieved with a combination of discrete, high-resolution semiconductor pixel and strip detectors in the inner part of the tracking volume, and straw-tube tracking detectors with the capability to generate and detect transition radiation in its outer part JINST 3 S0800 Figure 1.1: Cut-away view of the ATLAS detector. The dimensions of the detector are 25 m in 図 1.2: ATLAS 検出器 height and 44 m in length. The overall weight of the detector is approximately 7000 tonnes.
12 2 4 T LHC cm 2 s ATLAS Pixel SCT) (TRT) Hit Occupancy Hit Occupancy 3 Pixel Pixel Hit 10
13 Figure 1.2: Cut-away view of the ATLAS inner detector. 1.3: The layout of the Inner Detector (ID) is illustrated in figure 1.2 and detailed in chapter 4. Its basic parameters are summarised in table 1.2 (also see intrinsic accuracies in table 4.1). The ID is immersed in a 2 T magnetic field generated by the central solenoid, which extends over a length of Occupancy ATLAS 5.3 m with a diameter of 2.5 m. The precision tracking detectors (pixels and SCT) cover the region η < 2.5. In the barrel region, they are arranged on concentric cylinders around the beam axis ATLAS while in the end-cap regions they are located on disks perpendicular to the beam axis. The highest granularity is achieved around the vertex region using silicon pixel detectors. The pixel layers are segmented in R φ and z with typically three pixel layers crossed by each track. All pixel sensors SCTare identical and have a minimum pixel size in R φ z of µm 2. The intrinsic accuracies in the barrel are 10 µm(r φ) and 115 µm(z) and in the disks are 10 µm(r φ) and 115 µm(r). SCThe pixel detector has approximately 80 µm 80.4 million readout channels. 128 For mm the( ) SCT, eight strip layers (four space points) are crossed by each track. In the barrel region, this detector uses small-angle Pixel 1.4 SCT (40 mrad) stereo strips to measure both coordinates, with one set of strips in each layer parallel to 80 the beam direction, measuring R φ. They consist of two 6.4 cm long daisy-chained µm sensors with 768 a strip pitch of 80 µm. In the end-cap region, the detectors have 2 2 a set of strips running radially and a set of stereo strips at an angle of 40 mrad. The40 mean mrad pitch of the strips is also approximately 80 µm. The intrinsic accuracies per module in the barrel are 17 µm(r φ) and 580 µm(z) and in 2 the disks are 17 µm (R φ) and 580 µm (R). The total number of readout channels in the SCT is approximately 6.3 million. A large number of hits (typically 36 per track) is provided by the 4 mm diameter straw tubes TRT of the TRT, which enables track-following up to η = 2.0. The TRT only provides R φ information, for which it has an intrinsic accuracy of 130 µm per straw. In the barrel region, the straws are TRT 4 mm parallel to the beam axis and are 144 cm long, with their wires divided into two halves, approximately at η = 0. In the end-cap region, the 37 cm long straws are arranged radially in wheels. The total number of TRT readout channels is approximately 351, Pixel µm Pixel SCT Hit Occupancy 2008 JINST 3 S
14 1.4: SCT 1.3 LHC HL-LHC LHC cm 2 s 1 High Luminosity Large Hadron Collider (HL-LHC) LHC HL-LHC 3000 fb 1 Higgs Higgs SUSY HL-LHC ATLAS 12
15 ~50 fb ~300 fb Integrated Luminosity s = 13~14 TeV, L=1!10 34 cm -2 s -1 s = 14 TeV, L=2!10 34 cm -2 s -1 s = 14 TeV, L=5!10 34 cm -2 s ~3000 fb : LHC HL-LHC Hit Occupancy 2020 Hit Occupancy Hit Occupancy TRT Pixel SCT 2 HL-LHC Pixel ATLAS µm µm Pixel Hit Occupancy ATLAS Pixel n n + n-in-n HL-LHC Pixel p n + n-in-p 13
16 SCT SCT Hit Ocupancy ATLAS SCT 128 mm HL-LHC 6 SCT 4 24 mm 2 48 mm 80 µm 74.5 µm p-in-n n-in-p HL-LHC HL-LHC HL-LHC 1.4 HL-LHC µm 10 mm 10 14
17 ,, : HL-LHC 15
18 mm 10 µm 10 µm khz HL-LHC 10 µm 10 khz 10 mm 10 mm -40 DAQ ns 10 µm SVX4 Application Specific Integrated Circuit (ASIC) SVX
19 SVX4 2 connector SVX4 Silicon strip sensor 1.7: SVX4 PC SVX4 SVX4 SVX4 PC 4 17
20 ASIC SVX4 sensor PC Telescope Board DAQ System 1.8: ASIC ASIC PC ASIC PC ASIC 18
21 1.6 HL-LHC SVX4 ASIC SVX4 2 3 ASIC SVX4 4 SVX4 5 ASIC
22 2 2.1 ATLAS Pixel SCT ATLAS ATLAS p n p-n p n 3 5 p n p n p-n p n p n p n ev = 20
23 n-type p-type n-type p-type 2.1: p n p-n p-n n p 21
24 2.1.2 ATLAS SCT p-in-n Al readout SiO2 p + n-bulk n + Charged particle 2.2: SCT 2.2 n n p + p n + n n p + p-in-n p + n + p + n n + n + p + p + SiO 2 Al p + Al SiO 2 p + AC p + Al p + 22
25 2 ATLAS SCT ATLAS n p + p-in-n 300 µm MIP 116 kev 80 kev 3.6 ev 22,000 1 MIP 3.5 fc n V HV p + GND 2.5 p + Al AC C coupling 100 V p + GND n p p + 23
26 Figure 4.4: Schematic view of a barrel pixel module (top) illustrating the major pixel hybrid and sensor elements, including the MCC (module-control chip), the front-end (FE) chips, the NTC thermistors, the high-voltage (HV) elements and the Type0 signal connector. Also shown (middle) is a plan view showing the bump-bonding of the silicon pixel sensors to the polyimide electronics substrate. The photograph at the bottom shows a barrel pixel module. A schematic view and photograph of a pixel module are shown in figure 4.4. A pixel module 図 2.4: テレスコープ検出器に用いるシリコンストリップセンサー consists of a stack, from the bottom up, of the following components: (a) 16 front-end electronics chips thinned to 180 µm thickness, each with 2880 electronics channels; 24 (b) bump bonds (In or PbSn), which connect the electronics channels to pixel sensor elements; (c) the sensor tile of area mm2 and approximately 250 µm thick; (d) a flexible polyimide printed-circuit board (flex-hybrid) with a module-control chip glued to the flex-hybrid; 2008 JINST 3 S08003 図 2.3: 内部飛跡検出器の Pixel モジュール 電気回路とシリコンセンサーを重ねて 一体化することで信号読み出しを実現している
27 2.1: 50 µm 15.4 mm 10 µm 1.5 pf 200 MΩ 13 mm 15.4 mm 300 µm p-in-n 80 V ( 1 AC d x Q L Q R x x = Q R Q L + Q R d (2.1) MIP S S = Q L + Q R (2.2) 25
28 Positive pulse ~3.5 fc/mip Al SVX4 input Ccoupling p + Rbias n + ~ 100 V Silicon Strip Sensor (300 μm thick) 2.5: Charged particle QL QR x d 2.6: 26
29 x Q R δx δx δx = ( x Q R ) 2 δq R 2 = x Q R δq R (2.3) δq R, N δx = N S d (2.4) d = 50 µm SVX4 27
30 3 ASIC: SVX4 ASIC SVX4 3.1 SVX4 Fermilab LBL ASIC [2, 3] 128 ADC 1 SVX4 3.1 Preamp, Pipeline, ADC Front-end Back-end 3.2 Front-end Preamp Pipeline Pipeline Pipeline Front-end clock (FECLK) SVX4 Pipeline ADC (Double Correlated Sampling) Back-end Pipeline Wilkinson ADC 8 bit Data sparsification/zero suppression ADC FIFO SVX4 SVX4 ADC 192 bit register SVX4 Configuration SVX4 Configuration 28
31 SVX4 Preamp Pipeline FIFO Input ch 0 ADC Sparsify Input ch 127 FECLK W R! 47 Level 1 trigger Digital threshold Sparsify Output 8 bit BUS Data 3.1: SVX4 Input pulse ~ 6.40 mm Preamp Front end : Analog circuit ~ 9.11 mm Pipeline ADC FIFO Back end : Digital circuit Transceiver I/O Control Output digital data 3.2: SVX4 Front-end Back-end 29
32 3.1.1 Front-end SVX4 Front-end Preamp Pipeline Preamp Preamp 3.3 Preamp Preamp Feedback Capacitor Preamp Feedback Capacitor 220 ff C load 1 pf Preamp 5 Preamp 200 fc ( 57 MIP ) Preamp Preamp Reset Preamp Reset 200ns Preamp Preamp (C t ) C t 25 ff 5 Preamp Configuration Preamp Reset Silicon sensor Cf = 220 ff Sa Sb Pipeline Cload ~ 1 pf Cc Ct = 25 ff Bandwidth Adjust 3.3: Preamp FECLK Preamp pipeline 30
33 Pipeline Preamp FECLK Pipeline 46 Pipeline Pipeline Reset Pipeline Reset 20 ns Pipeline 40 fc ( 10 MIP) SVX4 Level one Accept (L1A) Pipeline Back-end ADC L1A Pipeline ADC Configuration Pipeline Pipeline FECLK 7.6 MHz 132 ns 5.5 µm L1A Pipeline 46 1 L1A L1A ADC Pipeline ADC FECLK Double Correlated Sampling Back-end Back-end ADC FIFO Wilkinson ADC Wilkinson ADC Comparator 3.5 Pipeline Pipeline =SVX4 8 bit Comparator 2 1 = t Comparator 31
34 Preamp C1 ADC (Back-end) C2 C47 (pedestal storage) Pipeline Reset Write amp Pipeline Reset Read amp 3.4: Pipeline 46 1 Comparator ADC FIFO Ramp Pedestal SVX4 Ramp Reference 3.5 ADC Ramp Reference Ramp Pedestal Ramp Reference ADC Ramp Reference Ramp Pedestal Configuration Configuration ADC Comparator FIFO ADC 8 bit FIFO Configuration ADC ADC Configuration ADC ADC 32
35 Voltage Signal Input Level Ramp Reference (0 Signal Level) Level to be Digitized Offset Ramp Pedestal 1 Δt Counter start Counter stop Comparator Time 0 Time 3.5: Wilkinson ADC 33
36 (Read Neighbor mode) FIFO 8 bit BUS : SVX4 Byte no Content Comments 1 Chip ID MSB 1 chip ID Pipeline Cell Number pipeline ID bit 0 3 Channel ID 4 Data for above Channel ID ADC Last - 1 Channel ID Last Data for above Channel ID Chip ID Pipeline cell ID 2 Byte ADC 2 ADC 258 Byte ADC ADC 2 Byte 25MHz 50MHz 8 bit 400Mbps SVX mm 6.40 mm bit Configuration register 34
37 Preamp 200 fc AC Coupling Calibration charge injection Channel Mask/Disable pipeline 4 µm FECLK Double correlated sampling 8 bit Wilkinson ADC Data Sparsification (zero suppression) ADC 8 bit FIFO 2 Preamp, Pipeline 7.6 MHz FECLK duty 20% ADC 53 MHz FIFO 25 MHz BECLK duty 40-50% Daisy chain 1 1W AVDD +2.5V 60 ma DVDD +2.5V ma ma 1 MIP SN SVX4 DØ MODE CDF MODE Initialize Mode, Acquire Mode, Digitize Mode, Readout Mode 4 SVX Preamp, Pipeline, ADC DØ MODE CDF MODE (3.2 ) 4 35
38 SVX4 (3.3 ) SVX4 2 SVX4 3.4 LVDS input Single end input LVDS input LVDS output LVDS inout (Bi-direction) LVDS output Single end: 8 lines LVDS: 13 pairs = 26 lines Total: 34 lines / chip 3.6: SVX DØ MODE CDF MODE SVX4 DØ MODE CDF MODE MODE DØ MODE L1A L1A CDF MODE 4 L1A Pipeline 36
39 L1A Pipeline CDF MODE (Dead timeless operation) DØ MODE 3.3 Operation cycle SVX SVX4 Initialize Mode, Acquire Mode, Digitize Mode, Readout Mode SVX4 3.7 Initialize Mode Configuration Acquire Mode Pipeline L1A Digitize Mode Readout Mode Acquire Mode 4 CHMODE, FEMODE, BEMODE 3 FEMODE BEMODE CHMODE FEMODE BEMODE 3.3 DØ MODE 8 Initialize Mode, Acquire Mode, Digitize Mode SVX4 Readout Mode 8 bit BUS Initialize Mode Initialize Mode 3.8 SVX4 Configuration FE- CLK PRin FECLK 7.6 MHz duty 20% PRin Configuration parameter SVX4 192 bit Configuration register FECLK PRin register Configuration 37
40 3.2: SVX4 DØ MODE BUS Signal Name Description Signal Type PARST Preamp Reset Single ended Input PR1 Pipeline read Single ended Input PR2 Pipeline write (pedestal cell) Single ended Input L1A Level one Accept Single ended Input CALSR Write SEU reg / cal injection Single ended Input FEMODE Mode Selector Single ended Input BEMODE Mode Selector Single ended Input CHMODE Mode Selector Single ended Input FECLK Front end Clock (20 % duty cycle)) LVDS Input BECLK Back end Clock (40-50 % duty cycle) LVDS Input OBDV Odd Byte Data Valid LVDS Output BUS<0> / Comp_rst Data BUS / Comparator Reset LVDS Bi-direction BUS<1> / Ramp_rst Data BUS / Ramp Voltage Reset LVDS Bi-direction BUS<2> / PR2 Data BUS / PR2 LVDS Bi-direction BUS<3> / Rref_sel Data BUS /Ramp Reference Select LVDS Bi-direction BUS<4> / PARST Data BUS /PARST LVDS Bi-direction BUS<5> / L1A Data BUS / L1A LVDS Bi-direction BUS<6> / PR1 Data BUS / PR1 LVDS Bi-direction BUS<7> / CALSR Data BUS / CALSR LVDS Bi-direction PRin Priority in LVDS Input PRout Priority out LVDS Output 3.3: (DØ MODE) FEMODE BEMODE STATE 0 0 Initialize Mode 0 1 Acquire Mode 1 1 Digitize Mode 1 0 Readout Mode 38
41 CHMODE FEMODE BEMODE PRin PRout FECLK BECLK OBDV BUS0/Comp_rst BUS1/Ramp_rst BUS2/PR2 BUS3/Rref_sel BUS4/PARST BUS5/L1A BUS6/PR1 BUS7/CALSR Initialize Mode Acquire Mode Digitize Mode Readout Mode 3.7: SVX4 Readout Mode BUS SVX4 39
42 register FECLK PRout FECLK Configuration register PRout 192 clock FECLK PRin CALSR FECLK PRin Configuration register 192 bit Latch Shadow register 3.8: Initialize Mode PRin Configuration parameter FECLK PRin SVX4 Configuration register SVX4 Configuration register Single Event Upset (SEU) Shadow register Configuration register CALSR PRin 192 bit Configuration parameter CALSR Configuration register 64 bit Shadow register CALSR Pipeline Preamp Pipeline Cell Number 1 Acquire Mode Acquire Mode Preamp Pipeline 40
43 Acquire Mode FECLK Preamp Pipeline FECLK 46 Pipeline FECLK Preamp Pipeline Pipeline Reset 20 ns FECLK 20 ns FECLK Preamp Pipeline Preamp Pipeline Pipeline Reset (>20 ns) FECLK L1A PR2 (Pedestal Acquisition) 5 42 CALSR HIT event / Charge Injection 3.9: Pipeline SVX4 Acquire Mode L1A 3.9 FECLK PR2 Preamp 46 1 FECLK L1A Pipeline ADC Pipeline L1A L1A 1 FECLK 41
44 3.9 FECLK SVX4 L1A L1A 1 42 FECLK Configuration PickDel L1A SVX4 SVX4 L1A Preamp CALSR CALSR Pipeline PickDel CALSR Preamp 200 fc Preamp Preamp Reset Acquire Mode Preamp Reset PARST 200 ns Preamp Preamp Reset Acquire Mode Digitize Mode Pipeline ADC Digitize Mode Digitize Mode L1A ADC FIFO Digitize Mode 3.10 Acquire Mode Pipeline PR1 PR1 FECLK 2 Configuration SVX4 Pipeline ADC PR1 2 Comp_rst Comparator ADC Ramp_rst Rref_sel Comp_rst 50 ns Rref_sel ADC Ramp Pedestal Ramp_rst 42
45 Ramp_rst Rref_sel 2 PR1 ADC BECLK Digitize Mode 53MHz BECLK BECLK PR1 BECLK 255 Configuration Comparator FIFO BECLK 2 Digitize Mode Readout Mode FIFO Pipeline ADC Digitize Mode (FEMODE && BEMODE) BECLK FECLK Comp_rst ~132 ns Ramp_rst > 600 ns Rref_sel 50 ns PR1 4! FECLK PB = 0 : Pedestal - Signal PB = 1 : Signal - Pedestal 3.10: Acquire Mode Digitize Mode 43
46 3.3.4 Readout Mode FIFO SVX4 Readout Mode 3.11 Readout Mode (FEMODE && ~BEMODE) PRin PRout BECLK OBDV BUS[7:0] Chip ID Pipeline Cell ID DATA Channel ID DATA Channel ID 3.11: Readout Mode Digitize Mode Readout Mode PRin PRin SVX4 Readout Mode Readout Mode PRout SVX4 PRin PRout BECLK Readout Mode 25MHz BECLK BECLK OBDV OBDV OBDV Chip ID Pipeline Cell Number Channel ID 44
47 PRout OBDV Acquire Mode Digitize Mode Readout Mode L1A L1A Digitize Mode 2.3 µs Digitize Mode Readout Mode 3.2 µs Readout Mode µs DØ MODE L1A L1A 11 µs DØ MODE 90 khz Data Sparsification 4 µs Data Sparsification 140 khz 3.4 Daisy Chain SVX4 SVX4 1 SVX4 Daisy Chain SVX4 Daisy Chain SVX4 Top Neighbor (TN) Bottom Neighbor (BN) PRin PRout 3.12 TN BN 2 SVX4 Readout Mode SVX Read Neighbor mode SVX4 SVX4 SVX4 Daisy Chain SVX4 1 SVX4 2 Configuration SVX4 2 45
48 Nth chip 2nd chip 1st chip TN BN TN BN PRin PRout PRin PRout Parallel I/O Control Signals 3.12: Daisy chain SVX Daisy Chain Configuration SVX4 PRin Configuration register 192 bit FECLK Configuration register PRout PRout SVX4 PRin SVX4 SVX4 PRin Daisy Chain SVX4 192 bit Configuration PRin SVX4 Configuration SVX4 Configuration SVX4 Chip ID Chip ID Configuration Daisy Chain Daisy Chain 3.14 SVX4 8 8 bit BUS SVX4 BUS 46
49 Nth chip 2nd chip 1st chip TN BN TN BN PRout PRin PRout PRin PRout PRin Output 192! N Configuration parameter Synchronizing All SVX4s with FECLK Input 192! N Configuration parameter 3.13: Daisy Chain Configuration SVX4 Configuration register Configuration PRout PRout PRin SVX4 PRout PRout PRin Token 47
50 Nth chip 2nd chip 1st chip TN BN TN BN Token (PRin) Token (PRout) Token (PRin) Token (PRout) nth 2nd 1st 8 bit BUS Line 3.14: Daisy Chain SVX4 PRin PRout Token 1 48
51 4 DAQ DAQ 4.1 SVX4 SVX4 DAQ SVX4 PC SEABAS SEABAS 4.1 SEABAS Sub Board User FPGA SiTCP FPGA ~100 Mbps Ethernet PC ADC DAC 4.1: SEABAS SEABAS SEABAS IC SEABAS SEABAS 2 FPGA IC User FPGA PC SiTCP FPGA SEABAS PC CAMAC VME DAQ User FPGA 49
52 IC SEABAS DAQ User FPAG PC SEABAS 3.3 SVX4 SVX4 bit stream SVX4 bit stream 4.2 SEABAS bit stream SEABAS SVX4 PC 4.2: PC bit stream FPGA SVX4 DAQ SEABAS DAQ PC SVX4 SEABAS 50
![4.2 SEABAS SEABAS SEABAS DAQ 4.2.1 SEABAS SEABAS Silicon-On-Insulator (SOI) [5] 4.](/docs-images/88/115030996/images/53-0.jpg "3 ~230 mm JTAG Connector PROM ~130 mm NIM I/O Ethernet Power 64 pin Connector (! 4) ADC DAC User FPGA SiTCP FPGA 4.")
53 4.2 SEABAS SEABAS SEABAS DAQ SEABAS SEABAS Silicon-On-Insulator (SOI) [5] 4.3 ~230 mm JTAG Connector PROM ~130 mm NIM I/O Ethernet Power 64 pin Connector (! 4) ADC DAC User FPGA SiTCP FPGA 4.3: SEABAS User FPGA 64 ADC DAC SEABAS FPGA SiTCP FPGA SiTCP[6] TCP/IP Ethernet PC FPGA SiTCP FIFO User FPGA FIFO PC 51
54 SiTCP TCP UDP PC User FPGA Remote Bus Control Protocol (RBCP) User FPGA RBCP 0x0000_0000 0xEFFF_FFFF PC User FPGA RBCP User FPGA PC TCP SEABAS [7] User FPGA Xilinx Virtex-4 (XC4VLX25-10FF668) 120 I/O Max Block RAM : 1,296 Kb SiTCP FPGA Xilinx Virtex-4 (XC4VLX15-10FF668) 100 BASE-T SiTCP Power ± 5.0 V > 1 A > 0.2 A SVX4 (Hardware Description Language: HDL) Verilog HDL SVX4 SVX4 PC 2 SVX4 4.2 bit stream Configuration Control RAM Config RAM CHMode Creator SVX4 8 bit BUS SiTCP FPGA PC FIFO 52
55 SVX4 SEABAS (Firmware) User FPGA SiTCP FPGA PC (Software) Serial bit stream creator Control RAM Config RAM CHMode Creator Register Access Switch Connection State RBCP FIFO TCP 4.4: 53
56 Control RAM SVX4 FPGA Control RAM 2 RAM 8 bit bit stream FPGA (RAM) (ADDRESS ) ADDRESS Clock ADDRESS Control RAM (Block RAM) Bit stream _ X _ 8bit SVX4 8 bit Data width X X X _ X _ X X X X X X X X X X X _ X X X X X X X X _ X _ X X X X X X X _ 4.5: Control RAM bit stream Control RAM Control RAM bit straem Control RAM Control RAM 4.5 RBCP Control RAM Control RAM 16 bit 8 bit RAM 2 SVX4 bit stream Control RAM SVX4 bit stream 54
57 1 Control RAM bit stream Initialize Mode Acquire Mode 38MHz FECLK 5 Digitize Mode Readout Mode 210 MHz Digitize Mode BECLK 4 Control RAM Control RAM 1 16,384 =2 14 ) Config RAM Clock ADDRESS Config RAM (Block RAM) 8 bit Data width ADDRESS Serial bit stream creator FPGA bit stream bit stream SVX4 4.6: Config RAM Control RAM Config RAM bit stream Config RAM bit stream SVX4 Configuration Configuration register RBCP Config RAM Config RAM Control RAM Config RAM RAM Config RAM 38MHz Control RAM bit stream RAM 16 bit SVX4 16 Config RAM 8 bit Config RAM 55
58 bit stream 4.6 Serial bit stream creator CHMode Creator SVX4 4 Initialize Mode Acquire Mode Digitize Mode Readout Mode PC Config RAM Control RAM FIFO SVX4 8 bit FIFO SVX4 50 MHz FIFO SiTCP TCP 25 MHz 8 bit FIFO 8 SVX DAQ PC 2 SVX4 Configuration RBCP SEABAS SEABAS TCP SEABAS TCP/IP C++ TCP/IP DAQ 5.6 PC SEABAS TCP/IP PC Configuration Config.txt RBCP SEABAS User FPGA Config RAM bit stream SVX4 Configuration SVX4 Ctrl_line.txt RBCP SEABAS 56
59 Software FPGA SVX4 Config.txt ctrl_line.txt end config Config RAM EndConfig signal Config bit stream Return bit stream latch shadow reg Decoder Control RAM FIFO Ctrl bit stream Data Repeat : DAQ 57
60 User FPGA Control RAM Control RAM SVX4 SVX4 8 bit User FPGA FIFO PC PC Control RAM SVX4 PC RBCP PC SEABAS UDP UDP TCP TCP SEABAS UDP UDP TCP PC User FPGA RAM UDP RBCP RBCP Config RAM Control RAM 1 Config RAM Control RAM DAQ RAM SVX4 RBCP RBCP 1 8 bit SVX4 TCP ROOT ROOT CERN 3.1 SVX4 Configuration ) Chip ID Pipeline cell ID Channel ID ADC PC Chip ID bit stream 8 bit ADC PC 58
61 4.8: RBCP [6] 59
62 第 5 章 DAQ システムの動作試験 テレスコープ検出器開発に向けて SVX4 からの信号読み出しを確立するために DAQ システムを構築した 第 4 章で述べたファームウェアとソフトウェアに加え SVX4 を 1 チップ搭載するためのプリント基板を設計 開発したので その基板の 説明を最初にしたあと DAQ システムの動作試験の結果を述べる その後 テレス コープ検出器の実機と同様の電気回路をもつ基板の設計 開発を行ったので その 基板についての説明をしたあと 基板の動作試験の結果を述べる 5.1 SVX4 BOARD Version 1: 1 チップ読み出し用 基板 DAQ システムの一部として SVX4 を一つ搭載し SEABAS と接続できる基板 SVX4 BOARD V1 を開発した SVX4 BOARD V1 と SEABAS を接続した写真 を図 5.1 に示す 図 5.1: SVX4 BOARD V1 と SEABAS SVX4 は 裏面をアナログ電源用の GND AGND に接続しておく必要があるの で 導電性の銀ペーストで SVX4 BOARD V1 に接着してある SVX4 上の信号入出 60
63 SVX4 BOARD V1 SVX4 SVX4 5.2 SVX4 SVX4 BOARD V1 4 SEABAS User FPGA SVX4 LVDS 100 Ω ch 0, 32, 63, 96, 127 LEMO 5.2: SVX4 AVDD DVDD 2 VCAL SVX4 SVX4 BOARD V1 5.3 AVDD DVDD 5.1 Configuration AVDD DVDD 61
64 DV CN9 JK-1( ) A 1 B 2 CN10 JK-1( ) A 1 B 2 AV S1 1 3 S2 1 3 JSW3 2 JSW3 2 AV R9 DV C16 4.7U/T R6 51 C13 0.1U C15 4.7U/T 10K C U R8 C U C U C17 0.1U R7 10K U1B L1 VCAL L2 AVDDfe L3 ISET(BIAS) L4 VRest L5 preampbuf127 L6 Ncas L7 gnd L8 gnd L9 gnd L10 ReadBUF127 L11 writebuf127 L12 gnd L13 QVDD L14 AREF L15 10K AVDDadc L16 IQUI L17 VTH L18 gndd L19 vddd L20 D0MODE L21 USESEU L22 ISLOPE L23 Bottom_Neighbor L24 PRout+ L25 PRput- L26 SVDD L27 SGND SVX4 5.3: SVX4 BOARD V1 SVX4 5.1: SVX4 BOARD V1 AVDD 30 ma 130 ma DVDD 20 ma 30 ma 62
65 5.1.1 DAQ Configuration register SVX4 Initialize Mode Configuration Configuration SEABAS User FPGA Config RAM SVX4 Configuration Configuration PRin bit PRin Configuration register PRout 2 1 Configuration PRout 192 bit 192 bit PRin FECLK PRout 5.4: Configuration bit stream Configuration SVX4 PRin FECLK PRout SVX4 BOARD V1 5.4 PRin 192 bit 2 2 PRout 1 PRin DAQ Configuration register 63
66 bit stream SEABAS User FPGA Control RAM SVX4 5.5 SVX4 BOARD V1 SVX4 Initialize Mode Readout Mode CHMODE FEMODE BEMODE FECLK BECLK PRin PRout OBDV Comp_rst / BUS0 Ramp_rst / BUS1 PR2 / BUS2 Rref_sel / BUS3 PARST / BUS4 L1A / BUS5 PR1 / BUS6 CALSR / BUS7 Initialize Mode Acquire Mode Digitize Mode Readout Mode 5.5: SVX4 bit stream SVX4 Initialize Mode Acquire Mode Digitize Mode PRout OBDV SVX4 3.3 bit stream SEABAS SVX4 Configuration DAQ SVX4 64
67 SVX4 DØ MODE 8 BUS Readout Mode 5.5 Initialize Mode Acquire Mode Digitize Mode Readout Mode SVX Chip ID Pipeline Cell Number Channel ID ADC 8 bit DAQ SVX4 SVX4 BUS0 BUS1 BUS2 BUS3 BUS4 BUS5 BUS6 BUS7 Chip ID Pipeline Cell Number Channel ID Data 5.6: Readout Mode BUS 3.1 SVX4 L1A 256 SEABAS PC SVX4 SVX4 128 ADC 5.7 SVX4 SVX4 SEABAS PC 65
68 SVX4 PC # Event hist_ hist_48 Entries 256 Mean RMS histogram_128ch ADC count histogram_128ch Entries Mean x Mean y RMS x RMS y # Event ADC count Channel 0 BW = 4 Isel = 4 Configuration parameter IWsel = 1 IRsel = 1 RTPS = 1 RAll = 1 RampPed = 8 RampRng = 0 5.7: 128 ADC ADC 48 ADC 128 ADC 2 SVX4 Configuration SVX4 Back-end ADC FIFO Front-end Preamp Pipeline ADC Configuration 3.5 Ramp Pedestal Ramp Reference RampPed RampRng Configuration Ramp Pedestal Configuration RampPed 5.8 RampPed RampRng Configuratiion 3 bit r2 r1 r0 66
69 A A = C (4 r0) + (3 r1) + (1 r2) (5.1) C 5.9 RampRng SVX4 SVX4 SVX4 Configuration Configuration SVX4 ADC Front-end Preamp Preamp SVX4 AVDD SVX4 VCAL Preamp 25 ff C t AVDD +0.8 V AVDD SVX4 SVX4 BOARD V1 VCAL C t Configuration VCAL VCAL 5.10 AVDD CALSR C t Preamp ADC ADC RMS Preamp Pipeline 67
70 Meanhist_0 Mean ADC count Meanhist_0 Entries 128 Mean ± RMS Integral Channel Configuration parameter RampPed = 1 RampPed = 4 RampPed = 2 RampPed = 8 BW = 4 Isel = 4 IWsel = 1 IRsel = 1 RTPS = 1 RAll = 1 RampRng = 0 Mean Mean ADC count (All Channels) Mean Entries 4 Mean ± 1.25 RMS Integral χ / ndf / 2 p ± 4.75 p ± RampPed 5.8: Ramp Pedestal RampPed 68
71 0 ADC count histogram_128ch mean_128ch histogram_128ch Entries Mean x Mean y RMS x RMS y histogram_128ch histogram_128ch Entries Mean x Mean y RMS x RMS y RMS Configuration parameter histogram_128ch RampRng = 000 RampRng = 001 RampRng = histogram_128ch Entries Mean x Mean y RMS x RMS y Channel mean_128ch mean_128ch Channel mean_128ch Channel Entries 128 Mean RMS #Event ADC count Entries 128 Mean #Event ADC count #Event BW = 4 Isel = 4 10 IWsel = 1 IRsel = 1 RTPS = 1 RAll = RampPed = 8 5.9: AVDD = +2.5 V VCAL pad Rext = 10 kω VCAL = 0 ~ +2.5 V 5 kω Ct = 25 ff 2.5 kω Controlled by the VCAL bit Controlled by CALSR line 5.10: AVDD VCAL 69
72 SVX4 Front-end ADC count histogram_128ch histogram_128ch Entries Mean x Mean y RMS x RMS y RMS_128ch Mean RMS Channel RMS_128ch Entries 128 Mean RMS Configuration parameter BW = 4 Isel = 4 RTPS = 1 RAll = 1 IWsel = 1 IRsel = 1 RampPed = 0 RampRng = Channel 5.11: ADC RMS Data Sparsification FIFO FIFO SVX4 ADC FIFO FIFO Data sparsification 5.12 ADC 120 ADC Data sparsification FIFO 70
73 Data size: ~2,000 bit (50 MHz Readout speed) Data size: 272 bit (50 MHz Readout speed) mean_128ch Mean ADC count Threshold mean_128ch Entries 128 Mean RMS mean_128ch Mean ADC count mean_128ch Entries 128 Mean RMS Channel Channel Configuration parameter Configuration parameter BW = 4 Isel = 4 IWsel = 1 IRsel = 1 RTPS = 1 RAll = 1 RampPed = 0 RampRng = 2 BW = 4 Isel = 4 IWsel = 1 IRsel = 1 RTPS = 1 RAll = 0 RampPed = 0 RampRng = : Data sparsification ADC 120 ADC 71
74 SVX4 BOARD V1 DAQ SEABAS SVX DAQ ADC 1 SVX4 ADC 1 Preamp VCAL Q cal = C t V cal (5.2) C t 25 ff V cal ADC V cal 300 mv ADC 5.13 ADC ADC ADC ADC 1 2,130e ,000 e ADC ,000 e 16% 5.11 RMS 5.14 RMS 0.53 RMS 1,130 ± 90 e [3] DØ MODE 700 e SEABAS SEABAS SEABAS SVX4 72
75 Mean ADC count ADC count Meanhist_ plot_ Meanhist_0 Entries 128 Mean RMS Channel plot_0 Entries 8 Mean 1.977e+05 RMS # e e : ADC 73
76 ChannelRMS_0V # Entry ChannelRMS_0V Entries 128 Mean RMS χ 2 / ndf / 9 Constant ± 2.78 Mean ± Sigma ± RMS/channel 5.14: ADC RMS 74
77 IC IC SEABAS DAUGHTER BOARD SEABAS SVX4 4 Daisy Chain SVX4 2 SVX4 Daisy Chain SVX4 BOARD V2 DAUGHTER BOARD SEABAS SVX4 BOARD V2 SVX4 DAUGHTER BOARD SVX4 BOARD V SEABAS - DAUGHTER BOARD DAUGHTER BOARD 5.15 SEABAS User FPGA DAUGHTER BOARD IC IC SEABAS SVX4 BOARD V mm 10 cm DAUGHTER BOARD IC +3.3 V +3.3 V GND 80 SVX4 BOARD V2 SVX4 DAUGHTER BOARD 80 DAUGHTER BOARD SVX4 BOARD V2 100 mm 110 mm 75
78 80 VCAL GND +3.3 V 100 mm LVDS & Single ended Driver / Receiver Transceiver 110 mm SEABAS 5.15: SEABAS - DAUGHTER BOARD SVX4 BOARD Version 2: 2 SVX4 2 DAUGHTER BOARD SEABAS SVX4 BOARD V SVX4 Daisy Chain 2 SVX4 Version 1 Version 1 SVX4 Version 2 2 SVX4 DAUGHTER BOARD 80 DAUGHTER BOARD SVX4 BOARD V V VCAL DAUGHTER BOADR IC SVX4 AVDD DVDD +2.5 V 2 Regulator +3.3 V +2.6 V SVX4 DAUGHTER BOARD SVX4 BOARD V2 76
79 D0 MODE CDF MODE SVX4! mm 100 mm Regulator! 2 AVDD, DVDD) Transceiver LVDS & Single ended Driver / Receiver : SVX4 BOARD V2 700 ma 1500 ma 100 mm 100 mm SVX4 BOARD V2 DAUGHTER BOARD IC IC 5.17 SVX4 LVDS (a) IC IC EN EN SEABAS (b) LVDS (c) SVX4 BOARD V2 DAUGHTER BOARD LVDS Single-end LVCMOS IC IC LVDS LVCMOS +3.3 V IC +3.3 V SVX V (d) DAUGHTER BOARD Single-end LVDS IC 2 SEABAS DAQ
80 (a) LVDS Driver / Receiver SVX4 BOARD V2 / DAUGHTER BOARD) (b) LVDS Driver / Receiver SVX4 BOARD V2 / DAUGHTER BOARD) EN EN Receiver TI SN75LVDT390 Driver TI SN75LVDS391 EN EN Transceiver TI DS91M040! 2 (c) Single-end Receiver SVX4 BOARD V2) +3.3 V +2.5 V (d) Single-end Driver DAUGHTER BOARD) Receiver TI SN75LVDT388A EN Driver TI SN74LVC541A Driver TI SN75LVDS389A 5.17: SVX4 BOARD V2 DAUGHTER BOARD / IC (a), (b), (c), (d) 78
81 SEABAS Power supply SVX4 BOARD V2 SVX4 Driver / Receiver DAUGHTER BOARD 5.18: DAUGHTER BOARD SEABAS SVX4 BOARD V2 79
82 SVX4 Configuration SVX4 Daisy Chain DAQ PC Configuration SVX4 Configuration SVX4 SVX4 bit pattern DAQ / IC SEABAS 2 SVX4 SEABAS SVX4 BOARD V2 SVX4 / 5.19 Acquire Mode Readout Mode bit stream SVX4 DAUGHTER BOARD SVX4 BOARD V2 SEABAS SVX4 Readout Mode 2 SVX4 2 SVX4 Daisy Chain SVX4 2 SEABAS 5.20 SVX4 SVX4 Probe. 1 SEABAS Probe. 2 Probe. 1 Probe. 2 SVX4 SEABAS SEABAS 80
83 OBDV FECLK PRin PRout Comp_rst / BUS0 Ramp_rst / BUS1 PR2 / BUS2 Rref_sel / BUS3 PARST / BUS4 L1A / BUS5 PR1 / BUS6 CALSR / BUS7 Acquire Mode Digitize Mode Readout Mode 1st chip data 2nd chip data 5.19: SVX4 81
![SVX4 SEABAS SVX4 BOARD V2 Regulator +2.6 V 2 SVX4 DAUGHTER BOARD Probe. 2 Data BUS Probe. 1 Data BUS Probe. 1 BUS[2] Probe. 2 BUS[2] Probe. 2 SEABAS Probe.](/docs-images/88/115030996/images/84-0.jpg "1 SVX4 5.20: SVX4 SEABAS SVX4 2 SVX4 ADC 2 5.21 2 SVX4 8 L1A 256 ADC Configuration ADC 1 ADC = Preamp FIFO SVX4 5.21 2 SVX4 100 ADC 0 SVX4 BOARD V1 AVDD +2.")
84 SVX4 SEABAS SVX4 BOARD V2 Regulator +2.6 V 2 SVX4 DAUGHTER BOARD Probe. 2 Data BUS Probe. 1 Data BUS Probe. 1 BUS[2] Probe. 2 BUS[2] Probe. 2 SEABAS Probe.1 SVX4 5.20: SVX4 SEABAS SVX4 2 SVX4 ADC SVX4 8 L1A 256 ADC Configuration ADC 1 ADC = Preamp FIFO SVX SVX4 100 ADC 0 SVX4 BOARD V1 AVDD
85 ADC count hist_256ch hist_256ch Entries Mean x Mean y RMS x 73.9 RMS y #Event mean_128ch 1st Chip 2nd Chip Channel 0 mean_128ch Entries 256 Mean RMS BW = 4 Isel 150= 4 IWsel = 1 IRsel = 1 RTPS = 1 RAll = 1 RampPed = 0 RampRng = : 2 SVX4 ADC
86 V SVX4 SVX4 AVDD +2.6 V SVX ADC 45 SVX4 SVX4 DAUGHTER BOARD SVX4 BOARD V2 84
87 6 SVX4 BOARD V ADC ch 0, 32, 63, 96, SVX4 AGND SVX4 BOARD V1 SVX4 AGND SVX4 SVX4 AGND SVX4 AGND 2.4 MIP 22,000 e SVX4 SVX4 BOARD V1 DAQ 1,130 e µm SVX4 85
88 0 (a) (b) histogram_128ch histogram_128ch Entries Mean x Mean y RMS x RMS y AGND : (a): SVX4 (b): SVX4 BOARD V1 SVX4 AGND SVX4-40 SVX4 bit stream SEABAS SVX4 SVX4 Acquire Mode Digitize Mode User FPGA Pipeline ADC HL-LHC SEABAS DAQ DAQ DAQ DAQ PC 86
89 PC 10 khz SVX4 BOARD V cm 5 m DAQ SVX4 BOARD V2 DAUGHTER BOARD LVDS SVX4 BOARD V2 DAUGHTER BOARD SVX4 BOARD V2 DAUGHTER BOARD DAUGHTER BOARD SVX4 BOARD V2 SVX4 AVDD DVDD +3.3 V 2 Regulator Regulator AVDD DVDD SVX4 BOARD V1 SVX4 SVX4 AGND SVX4 BOARD V2 SVX4 87
90 0.3 Ω SVX4 88
91 7 HL-LHC SVX4 SEABAS DAQ SEABAS SVX4 SVX4 BOARD V1 SEABAS DAQ DAQ 2 SVX4 SVX4 BOARD V2 DAUGHTER BOARD DAQ 89
92 A SVX4 Configuration register A.1: Configuration parameter 1 Bit No. Mask[127:0] 0:127 disable spare 128 spare VCAL 129 Disable Mask Preamp Reset disable BW[0:3] 131:134 Preamp Isel[0:3] 135:138 Preamp IWsel[0:1] 139:140 Pipeline amp IRsel[0:1] 141:142 Pipeline amp 0 = mask/disable 0 = 1 = 0 = mask, 1 = disable BW 164 µa + (Isel 32 µa 26 µa + (IWsel[0] 26 µa + (IWsel[1] 26 µa 26 µa + (IRsel 13 µa 90
93 A.2: Configuration parameter 2 Bit No. PickDel[0:5] 143:148 L1A FECLK PB 149 Pipeline = 1 = ID[6:0] 150:156 Chip ID RTPS 157 Real Time Pedestal Subtraction 0 = RTPS on, 1 = RTPS off disable Rd ADC 127 Rd ADC 63 RdAll 160 ADC RdNeigh 161 ADC RampPed[0:3] 162:165 ADC Ramp Pedestal RampDir = Rd127 off, 1 = Rd127 on 0 = Rd63 off, 1 = Rd63 on 0 = RdAll off, 1 = RdAll on 0 = RdNeigh off, 1 = Rd- Neigh on V ped = V ref - (11 - RampPed) 23 mv V ref Ramp Reference 0 = ramp up, 1 = ramp down CompPol 167 Comparator 0 = 0 1 (RampDir = 0), 1 = 1 0 (RampDir = 1) RampRng[0:2] 168: mv/ns [1 + (2 r0) + (2 r1) + (1 r2) ] 1 91
94 A.3: Configuration parameter 3 Bit No. Thresh[7:0] 171:178 ADC CntrMod[7:0] 179:186 ADC FC 187 LC 188 DriverI[2:0] 189: = 1 = R [(d2/43) + (d1/86) + (d0/172)] 1, 0 = 92
95 KEK CERN 4 KEK KEK Openit KEK ALTAS Jason Sang Hun Lee Teoh Jia Jian Lee Jong-won Jong-won 4 93
96 94
97 [1] The ATLAS Collaboration [The ATLAS Experiment at the CERN Large Hadron Collider], JINST 3 S08003 (2008). [2] L. Christofek, K. Hanagaki, et al. [SVX4 User s Manual], DØ Note 4252 (2005). [3] L. Christofek, K. Hanagaki, et al. [Preliminary Test Results for the SVX4], DØ Note 4250 (2005). [4] B. Krieger, et al. [SVX4: A New Deep-Submicron Readout IC for the Tevatron Collider at Fermilab]. [5] T. Uchida, Y.Arai [Soi EvAluation BoArd with Sitcp) User s Manual]. [6] T. Uchida [Hardware-Based TCP Processor for Gigabit Ethernet], IEEE Transactions on Nuclear Science, Vol. 55, No 3 (2008). [7] Xilinx [Virtex_4 Family Overview], DS112 v3.1 (2010). 95
ATLAS 2011/3/25-26
ATLAS 2011/3/25-26 2 LHC (Large Hadron Collider)/ATLAS LHC - CERN - s=7 TeV ATLAS - LHC 1 Higgs 44 m 44m 22m 7000t 22 m 3 SCT( ) SCT(SemiConductor Tracker) - - 100 fb -1 SCT 3 SCT( ) R eta=1.0 eta=1.5
Operation_test_of_SOFIST
ILC :SOFIST 2 29 1 18 SOI ILC SOI SOFIST SOFISTver.1 SOFISTver.1 SOFIST SOFISTver.1 S/N BPW 1 1 4 1.1............... 4 1.1.1... 4 1.1.2... 5 1.2 ILC... 6 1.2.1 ILC... 6 1.2.2 ILD...........................
ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp)
ADC121S625 ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Literature Number: JAJSAB8 ADC121S625 12 50kSPS 200kSPS A/D ADC121S625 50kSPS 200kSPS 12 A/D 500mV
R1RW0408D シリーズ
お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
16-Bit, Serial Input Multiplying Digital-to-Analog Converter (Rev. B
DAC8811 www.tij.co.jp ± ± µ ± µ ± V REF CS Power-On Reset DAC8811 D/A Converter 16 DAC Register 16 R FB I OUT CLK SDI Shift Register GND DAC8811C ±1 ±1 MSOP-8 (DGK) 4to 85 D11 DAC8811ICDGKT DAC8811C ±1
LM35 高精度・摂氏直読温度センサIC
Precision Centigrade Temperature Sensors Literature Number: JAJSB56 IC A IC D IC IC ( ) IC ( K) 1/4 55 150 3/4 60 A 0.1 55 150 C 40 110 ( 10 ) TO-46 C CA D TO-92 C IC CA IC 19831026 24120 11800 ds005516
R1RP0416D シリーズ
お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
AN15880A
DATA SHEET 品種名 パッケージコード QFH064-P-1414H 発行年月 : 2008 年 12 月 1 目次 概要.. 3 特長.. 3 用途.. 3 外形.. 3 構造...... 3 応用回路例.. 4 ブロック図.... 5 端子.. 6 絶対最大定格.. 8 動作電源電圧範囲.. 8 電気的特性. 9 電気的特性 ( 設計参考値 )... 10 技術資料.. 11 入出力部の回路図および端子機能の
LMC555 CMOSタイマ
CMOS 555 CMOS (SOIC MSOP MDIP) micro SMD (8 micro SMD) LM555 2 1 LMCMOS TM CMOS 19850925 24100 ds008669 Converted to nat2000 DTD added title to the 2 avos on the first page Edited for 2001 Databook fixed
R1LV0416Dシリーズ データシート
Wide Temperature Range Version 4M SRAM (256-kword 16-bit) RJJ03C0237-0100 Rev. 1.00 2007.05.24 262,144 16 4M RAM TFT 44 TSOP II 48 CSP 0.75mm 3.0V 2.7V 3.6V 55/70ns max 3µW typ V CC =3.0V 2CS 40 +85 C
R1RW0416DI シリーズ
お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
ANJ_1092A
Application Note SBAA066 ± ± ± ± µ ± ± ± ± 24 Bits 20/24MSB 2 s f S 768 khz 25 MHz (1) V IH 2.0 5.0 V (1) V IL 0 0.8 V (2) V IH 3.0 0 V (2) V IL 5.0 4.2 V (1) I IH V IH = V DD ±10 µa (1) I IL V IL = 0V
LTC ビット、200ksps シリアル・サンプリングADC
µ CBUSY ANALOG INPUT 10V TO 10V 2. 2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 V DIG V ANA PWRD BUSY CS R/C TAG SB/BTC DATA EXT/INT DATACLK DGND SY 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10µF 0.1µF SERIAL INTERFACE
Unidirectional Measurement Current-Shunt Monitor with Dual Comparators (Rev. B
www.tij.co.jp INA206 INA207 INA208 INA206-INA208 INA206-INA208 V S 1 14 V IN+ V S 1 10 V IN+ OUT CMP1 IN /0.6V REF 2 3 1.2V REF 13 12 V IN 1.2V REF OUT OUT CMP1 IN+ 2 3 9 8 V IN CMP1 OUT CMP1 IN+ 4 11
dr-timing-furukawa4.pptx[読み取り専用]
![dr-timing-furukawa4.pptx[読み取り専用]](/thumbs/93/112106674.jpg "dr-timing-furukawa4.pptx[読み取り専用]")
< kazuro.furukawa @ kek.jp > 1 2 Remote controlled automatic pattern arbitrator" Manual pattern generator" Recent typical operation. ~37Hz for KEKB LER (3.5GeV e+) ~12.5Hz for KEKB HER (8GeV e ) ~0.5Hz
DS90LV011A 3V LVDS 1 回路入り高速差動出力ドライバ
3V LVDS Single High Speed Differential Driver Literature Number: JAJS962 Single High Speed Differential Driver 19961015 23685 ds200149 Input Voltage changed to 3.6V from 5V Updated DC and AC typs basic
LM193/LM293/LM393/LM 回路入り低動作電圧低オフセット電圧コンパレータ
LM193,LM2903,LM293,LM393 LM193/ Low Power Low Offset Voltage Dual Comparators Literature Number: JAJSB74 2 LM293 2.0mV 2 A/D VCO MOS LM293 TTL CMOS LM293 MOS LM393 LM2903 Micro SMD 8 ( 0.3mm) Squarewave
R1LV1616H-I シリーズ
お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
LEPS
LEPS2 2016 2 17 LEPS2 SPring-8 γ 3 GeV γ 10 Mcps LEPS2 7 120 LEPS Λ(1405) LEPS2 LEPS2 Silicon Strip Detector (SSD) SSD 100 µm 512 ch 6 cm 3 x y 2 SSD 6 3072 ch APV25-s1 APVDAQ VME APV25-s1 SSD 128 ch
OPA134/2134/4134('98.03)
OPA OPA OPA OPA OPA OPA OPA OPA OPA TM µ Ω ± ± ± ± + OPA OPA OPA Offset Trim Offset Trim Out A V+ Out A Out D In +In V+ Output In A +In A A B Out B In B In A +In A A D In D +In D V NC V +In B V+ V +In
Δ Δ Δ 250
高エネルギー粒子用 Si検出器 第 10 章 1 特性 1-1 1-2 1-3 有感エリア 暗電流 接合容量 応答速度 2 シンチレータ式Si検出器 3 ダイレクト式Si検出器 3-1 3-2 3-3 3-4 3-5 空乏層の厚さ チャネリング効果 出力波高のばらつき ノイズとエネルギー分解能 位置検出用Si検出器 章 4 新たな取り組み 10 高エネルギー粒子用 5 応用例 粒子衝突実験 FGST
Triple 2:1 High-Speed Video Multiplexer (Rev. C
www.tij.co.jp OPA3875 µ ± +5V µ RGB Channel OPA3875 OPA3875 (Patented) RGB Out SELECT ENABLE RED OUT GREEN OUT BLUE OUT 1 R G B RGB Channel 1 R1 G1 B1 X 1 Off Off Off 5V Channel Select EN OPA875 OPA4872
ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp)
8-Channel, 500 ksps, 12-Bit A/D Converter Literature Number: JAJSA63 8 500kSPS 12 A/D 8 12 CMOS A/D 500kSPS / AIN1 AIN8 8 SPI QSPI MICROWIRE DSP (AV DD ) 2.7V 5.25V (DV DD ) 2.7V AV DD 3V 1.5mW 5V 8.3mW
LM358
LM358 2 DC LM358 5V DC 15V DC micro SMD (8 micro SMD) LM358 LM2904 LM258 LM158 20000801 19870224 33020 23900 11800 2002 3 ds007787 Converted to nat2000 DTD added avo -23 to the first page Edited for 2001
LT 低コスト、シャットダウン機能付き デュアルおよびトリプル300MHz 電流帰還アンプ
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