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1 Mentor Graphics High Speed Board 2002 January 2002 Electronic Design and Solution Fair
2 Agenda AutoActive / DRC Interconnectix / IBIS SPICE AutoActive + Interconnectix + EMI Sigrity SPEED2000 ( 2
3 AutoActive / DRC Interconnectix / IBIS SPICE AutoActive + Interconnectix + EMI Sigrity SPEED2000 ( 3
4 AutoActive 1/2 DRC DRC Common Data AutoActive 4
5 AutoActive 2/2 CAD Zuken PWS I/F Expedition PCB Mentor BS RE Board Station Cadence Allegro I/F AutoActive AutoActive SFX DestinyRE SFX RE 5
6 AutoActive / DRC Interconnectix / IBIS SPICE AutoActive + Interconnectix + EMI Sigrity SPEED2000 ( 6
7 Interconnectix 1/2 Common Data Interconnectix 7
8 Interconnectix 2/2 CAD Expedition PCB Mentor Board Station Interconnectix Interconnectix Allegro 3 rd Party CR5000 BD 8
9 AutoActive / DRC Interconnectix / IBIS SPICE AutoActive + Interconnectix + EMI Sigrity SPEED2000 ( 9
10 1/2 IBIS SPICE Common Data 10
11 2/2 Interconnectix ICX2.6 SPICE IBIS ICX3.0 ICX Series L,R,C ) 11
12 AutoActive / DRC Interconnectix / IBIS SPICE AutoActive + Interconnectix + EMI Sigrity SPEED2000 ( 12
13 1/3 AutoActive + Interconnectix AutoActive Interconnectix Interconnectix AutoActive 13
14 2/3 Auto Active ICX Rule Constraint storage 14
15 3/3 IBIS Interconnectix SPICE AutoActive Common Data 15
16 AutoActive / DRC Interconnectix / IBIS SPICE AutoActive + Interconnectix + EMI Sigrity SPEED2000 ( 16
17 EMI & Open Door Interconnectix SPEED2000 Interconnectix EMI / / 17
18 Interconnectix GUI 18
19 SPEED
20 Sigrity, Inc. January 2002 Electronic Design and Solution Fair
21 Agenda Sigrity Mentor Graphics Interconnectix SPEED2000 SPDGEN : SPDSIM : 21
22 Sigrity 1994 Dr.Jiayuan Fang / 1997 SPEED SPEED2000 (PI) PCB/LSI : Santa Clara (U.S.) : 22
23 Mentor Graphics Open Door Interconnectix Mentor Graphics /SI SPEED2000 PI / EMI 23
24 Interconnectix IBIS IBIS 24
25 SPDGEN / / / PCB IC /, r, tan, SkinEffect / 25
26 SPDSIM / LC /GND 26
27 /GND 2D 3D SPDSIM / 27
28 SPDSIM / 28
29 SPDSIM / / etc. 29
30 SPDSIM EMI 30
31 / (Delta-I noise, SSN) I/O /GND /GND /GND capacitor chip capacitor chip signal traces power/ground plan vias Printed Circuit Board 31
32 SPEED2000 / / 32
33 /GND ASIC Keep out Area C C C C C C Caps just outside the ASIC C C C C C C C C C C C C C C C C C C Current Sources Representing drivers Plane size 12 inch by 8 inch Plane separation 15 mils 33
34 /GND (V) 34
35 /GND (V) 35
36 /GND caps caps caps caps No caps 12 IDC caps 36
37 No decoupling caps 36 decoupling caps Edge radiation was calculated corresponding to waveforms in the previous slides. The higher power-ground noise without decoupling caps leads to much higher edge radiation. This was measured at a horizontal distance of 3m and a vertical distance of 3m from the board 37
38 <MCM+ > /GND Bernd Garben, Michael McAllister, IBM Germany, EPEP Conf., October
39 /GND 12 layers traces vias Power and ground planes and all other components are simulated together 39
40 /GND Z (Ohm) Measurement Simulation Frequency (MHz) 40
41 SPEED2000 Interconnectix 2002 Mentor Graphics PI / EMI PowerSI S, Y, Z ICX2SPD ndd 41
42 42
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