スライド 1

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なぎさおうじ
5 years ago
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1 SoC -SWG ATE -SWG

2 SEAJ 2

3 VLSI 3

4 How can we improve manageability of the divergence between validation and manufacturing equipment? What is the cost and capability optimal SOC test approach? How can we make test of complex SIP designs more cost effective? Can DFT and BIST mitigate the mixed signal tester capability treadmill? What other opportunities exist? Can ATE instruments catch up and keep up with high speed serial performance trends? Will increasing test data volume lead to increased focus on Logic BIST architectures? What are the other solutions? Can DFT mitigate analog test cost as it does in the digital domain? What happens when high speed serial interfaces become buses? Will market dynamics justify development of next generation functional test capabilities? 4

5 SoC WG2 5

6 SoC ATEDFT DFT WLBI BIST ATE IODC 6

7 SoC BIST (1)IO (2) DUT A No/Go 64M 7

8 DFT ATE BIST pass/fail WLBI pass/fail pass/fail ATE 10 STARC 8

9 00 ATPG STARC 9

10 BIST STARC 10

11 01 x 0 x x ATPG x x 0 x x 0 x xx x xx x 0 x STARC 11

12 DFT ITRS Fix 12 ITRS

13 Year of Production Embedded Cores BIST Standardization of core Standard format Standard format Standard format Extension to Extension to Extension to test data on EDA/ATE on EDA/ATE BIST on EDA/ATE analog cores analog cores analog cores Embedded Cores: Logic Test logic insertion at RTL design Partially Partially Fully Fully Fully Fully BISR for logic cores Minimal Minimal Minimal Some Some Some Embedded Cores: Memory Embedded non-volatile memory BIST SoC Level Testing Fault model for SoC level fault coverage Yes Yes Yes Yes Yes Yes Single stuck-at fault model/ transition ITRS2005 BIST Yes Yes Yes Yes Yes : 13

14 BIST SoCSRAM DRAMSRAM-BIST BIRABuilt-In Redundancy AllocationBISRBuilt-In Self Repair BISTBIRA/BISR SRAMR/D SRAMR/D SRAM BIST SRAM (R/D) BIST BIST SRAMR/D SRAM BIST BIST + BIRA/BISR BIST BIST+ BISR BIST BISR(eFuse BIST+ BISR BIST 90nm 65nm 45nm 14

15 BIST SoCITRS DFTBISTBIRA/BISR Year of Production BIST Technology Node hp90 hp65 SRAM Technology Node - Feature Size (F) [1] T bit(f 2 )[1] 140F 2 140F 2 140F 2 140F 2 140F 2 140F 2 140F 2 140F 2 SoC(%) [2] (Kbit) 4,293 [3] 9,135 9,326 9,504 19,322 20,397 21,498 46,111 BISR BISR BISR BISR BISR BISR BISR BISR BIST/BIRA/BISR TBD TBD TBD TBD TBD TBD TBD TBD [1] ITRS 2003 System Drivers Table 11a/b, Embedded Memory Requirements [2] Figure 11, Power Gap Effect on Chip Composition [3] TF/PIDS/FEP(2002) hp45 15

16 At-speed BIST 90nm 65nm 45nm 16

17 -SoC - 17

18 specification 18

19 BIST / BIST BIRABISR BIST DFT ATE 19

20 - 20

21 - DFT-BIST Device Test Requirements Table 30 DFT-BIST Device Test Requirements Near-term Year of Production Driver Technology Node hp90 hp65 DRAM ½ Pitch (nm) MPU / ASIC ½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Number of parallel sites Cost Scan data volume(giga-pin-vectors available per site) Logic Density Data capture volume (M bits-per-pin) Scan/BIST debug Scan pin (available per site / system) 384/2K 384/2K 512/4K 512/4K 512/4K 512/4K 512/4K Logic Density Scan vector rate (MT or MHz) Test Time Full function pin (available per site / system) 128/ / / / / / /512 Test Time Functional vector depth (M-Vectors) Logic Density Functional data rate (MHz) Test Time 21

22 / / / / / BIST / / / I -II 22

23 Table 30b DFT-BIST Device Test Requirements on SoC Production Table 30 DFT-BIST Device Test Requirements in SoC Production Near-term Year of Production Driver Technology Node hp90 hp65 DRAM ½ Pitch (nm) MPU / ASIC ½ Pitch (nm) MPU Printed Gate Length (nm) MPU Physical Gate Length (nm) Number of parallel sites Scan data volume(giga-pin-vectors available per site) Data capture volume (M bits-per-pin) Scan pin (available per site / system) Scan vector rate (MT or MHz) Full function pin (available per site / system) Functional vector depth (M-Vectors) Functional data rate (MHz) Cost Logic Density Scan/BIST debug Logic Density Test Time Test Time Logic Density Test Time 23

24 Packaging Package Burn-in Final Test Conventional Mounting Probe Test Wafer Voltage Stress Test Pattern Wafer Voltage Stress Burn-in & Test Integrated into WLBI WLBI Probing Heating Heating Test Pattern Dicing KGD High Density Mounting CSP SiP 24

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26 Year mm 300mm 200mm 300mm 1.2k 2.4k 40k 90k 1.2k 2.4k 40k 90k 2.5k 5.0k 40k 90k 2.5k 5.0k 60k 135k 2.5k 2.5k 5.0k 5.0k 10k 10k 10k 10k 60k 60k 135k 135k 135k 135k 135k 135k PCB PCR PCR Conductive particle Bump Pad Bump s Al Pads Si Substrate 26

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28 WG 28

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テストコスト抑制のための技術課題－DFTとATEの観点から

テストコスト抑制のための技術課題－DFTとATEの観点から 2 -at -talk -talk -drop 3 4 5 6 7 Year of Production 2003 2004 2005 2006 2007 2008 Embedded Cores Standardization of core Standard format Standard format Standard format Extension to Extension to test