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1 A. Matsuzawa,Titech
2 A/D A/D A/D A/D OP A. Matsuzawa,Titech
3 A/D A. Matsuzawa,Titech 3
4 AD 0G onersion frequency (Hz) G 00M 0M M 00k Flash Successie approximation Pipeline Sub-range 0k Resolution (bit) Multi-bit sigma-delta Single-bit sigma-delta Integrating A. Matsuzawa,Titech 4
5 A. Matsuzawa,Titech 5 AD S - in ref R x - in - in x ref ref x 0 in T ( ) in x ( T ) dτ 0 R T in R T
6 A. Matsuzawa,Titech 6 AD AD ISS 006
7 AD バイナリーサーチのアルゴリズムを用いたものが逐次比較型 AD である in S/H omparator Successie-approximation resistor and control logic 6bit OP b b b 3 B out DA Binary search DA ref FS in MSB LSB b b b 3 b 4 b 5 b 6 DA FS in FS 4 FS FS 8 FS FS 8 FS 6 FS MP in b b b 0 b b 3 b 0 b b 3 b 4 b A. Matsuzawa,Titech 7
8 SA AD SA AD FoM/00 FoM FoM /00 ourtesy Y. Kuramochi 0000 SAR AD Power s Sampling Freq. 000 FoM 000 Power[mW] ISS008 4bit bit FoM[fJ/con.step] 0-9bit 7-5bit 00 0 / Sampling Freq.[MSps] Year A. Matsuzawa,Titech 8
9 A. Matsuzawa,Titech 9 AD() x 0 S out S in ref
10 A. Matsuzawa,Titech 0 AD() 6 x - in 8 4 out S in ref
11 A. Matsuzawa,Titech AD() 6 x ref in out 8 4 S in ref MSBLSB
12 AD 65fJ/con. AD QP, QN INp TP QP M N- 4 J. raninckx and G. an der Plas, A 65fJ/onersion-Step 0-to-0.7mW 9b harge- Sharing SAR AD in 90nm Digital MOS, IEEE ISS 0007, Dig. of Tech. Papers, pp.46-47, Feb TP SP U INn TN TN SN QN cn cp Q REF i i U DD LK Track Sample Reset cp[0..n-] Precharge omp cn[0..n-] Result SAR ontroller B[0..N-] A. Matsuzawa,Titech
13 . sp, sn QP, QN MSB. MSB8u sp, sn 3. MSB- bit QP SP c0n c0p 8 U SN QN c0p c0n Precharge Precharge Track Sample Precharge ompare c0n c0p Qn S Q IN Qp 8 U DD S Q IN 8 U DD 64 U DD A. Matsuzawa,Titech ±... 3
14 A. Matsuzawa,Titech 4 k 0k 00k M 0M Input frequency [Hz] ENOB Fs 50MS/s P 75µW 0MHz 7.8bit 0MHz0.3mW FoM65fJ/stepFoM FoM65fJ/stepFoM 90nm MOS - Yes Yes SSAR This work - Yes No SAR Flash PL.7 - No No SAR PLBS Subr PL. No No Σ 3.4 Yes Yes T Σ 3. Dec. lock Ref. FoM includes FoM [fj] P [mw] ENOB Fs [MS/s] Arch. ISS06 Paper # - Yes Yes SSAR This work - Yes No SAR Flash PL.7 - No No SAR PLBS Subr PL. No No Σ 3.4 Yes Yes T Σ 3. Dec. lock Ref. FoM includes FoM [fj] P [mw] ENOB Fs [MS/s] Arch. ISS06 Paper #
15 FoM AD A. Matsuzawa,Titech 5 FoM 4.4fJ/on-step. M. an Elzakker, Ed an Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta, A.9uW 4.4fJ/onersion-step 0b MS/s harge-redistribution AD, IEEE ISS 008, Dig. of Tech. Papers, pp.44-45, Feb Simple SA architecture Multi-step charging can reduce energy more E diss n eq n b n eq b Multi-step charging ()
16 FoM, 4.4fJ/con-step..9uW, 0bit, 90nm MOS SNR (db) THD (db) DNL (LSB) INL (LSB) SNDR (db) ENOB (bit) E conersion (pj/conersion) Figure Of Merit (fj / conersion-step) Aerage FOM (fj / conersion-step) FoM This work ISS 007 ISS A. Matsuzawa,Titech 6
17 A. Matsuzawa,Titech 7 Ultra-high speed (--GHz) Low resolution (<8bit) Large power consumption D A LSB (4m, 8b, pp)
18 A. Matsuzawa,Titech 8 殆どの場合 比較器のミスマッチにより決定される
19 AD A. Matsuzawa,Titech 9
20 A. Matsuzawa,Titech 0 AD AD AD) DA 0.75 st out nd out stage stage
21 A. Matsuzawa,Titech Sample f, s OP Amplify (Hold) f : OP s : OPDA DA/- ref,0 out in ref,0, ref in out out in DA ( ref, 0, - ref )
22 A. Matsuzawa,Titech bit AD ref ref - ref ref - ref DA ref DA - ref ref - ref - ref
23 A. Matsuzawa,Titech 3 OP bitop ref ref - ref ref - ref ref - ref - ref
24 A. Matsuzawa,Titech 4 bit ref A/D - ref ref -ref ref
25 A. Matsuzawa,Titech out ref A B AB - ref /4 ref /4 - ref ref sig A AB - ref B
26 A. Matsuzawa,Titech 6.5bit MSB in.5bit.5bit.5bit.5bit bit stage stage stage3 stage4 stage5 LSB Q Q 0 Q Q 0 Q 3 Q 30 Q 4 Q 5 Q D-FF D-FF D-FF D-FFQ D-FF D-FF D-FF D-FF D-FF D-FF D-FF D-FF D-FF D-FF D-FF HA FA FA FA HA S 5 4 S 4 3 S 3 S S Q 5 Q 4 Q 3 Q Q Q 0
27 A. Matsuzawa,Titech 7 out ref - ref ref - ref sig - ref
28 A. Matsuzawa,Titech 8.5b /- 0.5 ref f pf s pf
29 A. Matsuzawa,Titech 9 f 0.9pF s.0pf
30 A. Matsuzawa,Titech 30 f.pf s pf
31 A/D A. Matsuzawa,Titech 3
32 A. Matsuzawa,Titech 3 AD OP OP OP DFF
33 A. Matsuzawa,Titech 33 D OP out _ op i _ op i in R R OPG G op _ i out in out R R G R R R R G R R R R G
34 A. Matsuzawa,Titech 34.5bitOP s f - f - Sample Amplify q f f in, q s s in, q p 0 q s ' s ( DA io ), q ' f ( out io ), q p' pio f ( q q ) q ( q ' q ' ) q ' f s p f s p out G f s io out in DA G p f
35 A. Matsuzawa,Titech 35 out 0 out ref - ref /4 ref /4 ref δ δ ref G pi o - ref ref in.5 LSB ref < G 4 4 ref N - ref G >.5 G ( db) > 6N 0 N 858dB, 070dB 8dB,494dB
36 A. Matsuzawa,Titech 36 - ref ref s DA - os Op Amp G q q f s f ( in os ) q f ' f ( out os ) ( ) q ' ( ) in out out s ( ) s f in f os s s s DA ( q q ) ( q ' q ' ) f s f DA in DA s os f s os out out s s out f f s s f f ( ) in DA DA out out DA DA s f DA DA in DA
37 bit in/- ref out ref MSB0 MSB / A B sig - ref ref sig A B / - ref N 0.0% for bit reflsb ref LSB( N ref ref LSB N N 4 4 ref δ δ ref N N LSB/ A. Matsuzawa,Titech 37
38 A. Matsuzawa,Titech 38.5bit in /- ref, 0 out ref ref - ref /4 ref /4 - ref ref in f s f s 4 out s δ δ s δ δ δ f f ref ref ( ) in LSB ref DA ( ) DA ref ( DA 0) - ref N (.5b/4LSB
39 A. Matsuzawa,Titech 39 AD 3 (3σ ) ( pf ) N 3 0bit: 0.4pF 0.pF bit: pf pf 4bit: 40pF 0pF 3 MIM
40 A. Matsuzawa,Titech 40 OUT IN IN.5B AD
41 A. Matsuzawa,Titech 4 / Pipe Stage and required spec Stage [pf] Islew [ma] D gain [db] GBW [MHz] st nd rd th th Is, apacitance,,d gain GBW Pipe Stage and Required spec urrent apacitance D gain GBW st nd 3rd 4th 5th 6th 7th 8th 9th 0th Pipe Stage
42 A. Matsuzawa,Titech 4 - FS / FS / Op Amp in nt s DA n n - q F os n G c th : OP out / f nt q c th / f : : kt : : OP : OP/ f
43 A. Matsuzawa,Titech 43 A/D q / q 3 q N ref N ref qn N ref N ref qn
44 A. Matsuzawa,Titech 44 SNR q 3 q N ref N ref qn N ref N ref qn log N ref th 0.5bit
45 A. Matsuzawa,Titech 45 f s pi po /g o g g m g n i o L m n L m o n o o g L o n g m o s g i s g g i, s g i g β β β o g β ( ) ( ) ( ) ( ) ( ) a 4 df f a 3 kt n df g i ktg 3 8 n i, g i / Hz 0 L 0 L m n no m n L m n no π β γ ω β γ ω β Q n: ascode n3: Folded ascode f L no kt 3 kt n β γ f
46 A. Matsuzawa,Titech : : : kt no γ n kt 3β n L n n kt β β L ni L ni nt kt 3 γnkt β L nt N i N kt kt i i i i i kt γnkt 3βL kt kt γnkt 3 β L
47 A. Matsuzawa,Titech 47 kt/ ref.0 0bit: 0.pF bit: pf 4bit: 30pF ref.0 0bit: 0.05pF bit: 0.5pF 4bit: 8pF N ref
48 in g m p in r out out g m r Gain (db) out ( 3) GBW e t τ out in out in e τ t 0db Log f GBW A. Matsuzawa,Titech 48
49 A. Matsuzawa,Titech 49 out ref - ref /4 ref /4 ref δ δ δ δ 4 ref ref e e t τ ss t ss τ < N ref 4 ω close GBW gmβ close L gmβ π L - ref ref in τ < t ss 0.7N t ss 3f c τ πgbw close ω close - ref GBW ω close close > >.f 3f c N c 0.7N π Nf 3 c, f c < 3GBW N close
50 A/D A. Matsuzawa,Titech 50
51 A. Matsuzawa,Titech 5 AD : sig : sig kt SNR sig L L m u g ref dd sig 4 sig AD
52 A. Matsuzawa,Titech 5 GBW _close g R GBW s p m, s ol pi L / : : :, :, : p f po : GBW gm GBW _close _close f f s pi L po ol g m o L ol o s pi o f f GBW _ close L ( ) s f s pi po o pi s f ol pi o
53 A. Matsuzawa,Titech 53 GBW _close gm o pi o GBW _close I ds, po o pi po pi o GBW _ I ds o Ids:4Ids) eff close α pii o I g m ds eff ds α poi o pi pi ds ds α pii o α I, α po pi, po o o sig Sim5% gd N po ds I ds
54 A. Matsuzawa,Titech 54 g m G gd gs D Ids db sb db B 000 I g m ds eff G gd gs D S I ds db sb db B f T S L W ox eff I ds [ff/ma],f T [GHz] W[m/mA] 00 0 S L[m] gs W gd f T eff m90nm
55 A. Matsuzawa,Titech 55 MOS eff 0.75 (a)w N,W P [m/ma], A_N, A_P [] (b) pi_n, pi_p, po [ff/ma], p_n, p_p [GHz] W N W P A_N A_P 90nm m m m m pi_n pi_p po p_n p_p 90nm m m m m
56 A. Matsuzawa,Titech 56 AD o pi, po f c o pi, po f c pi, po o f c pp 8bit f c 3GBW < N _ close GBW _ close g gm I o pi ds m, pi ii ds, eff o po po α α I o o ds pi o o po, pi Ids GBW_ close o eff I 3 ds pi < o po GBW _ close o eff 3 o o po o pi GBW_ close 3 I o eff i o ds I ds
57 A. Matsuzawa,Titech 57 AD dd o GBW _close 4 sig eff 0.75 sig 90nm 0.3m 0.8m 0.5m 0.35m dd sig pp eff eff dd eff o [pf] o bit bit bit 0bit 9 [m] N sig F5F
58 AD PMOS bit 0bit bit A. Matsuzawa,Titech 58 4bit
59 NMOS,PMOS GBW _close p NMOS,PMOS X X NMOS pi p PMOS pi p 90nm 0.3m 0.8m 0.5m 0.35m f p_n GHz f p_p GHz A. Matsuzawa,Titech 59
60 A. Matsuzawa,Titech 60 NMOS,PMOS NMOS NMOS 000 GBW _close [MHz] NMOS PMOS I ds [ma]
61 AD NMOS NMOS bit 0bit bit A. Matsuzawa,Titech 6 4bit
62 A. Matsuzawa,Titech 6 MHz 00 90nm 0.3µm 0.8µm 0.5µm 0.35µm 0 P d /f c [mw/mhz] I ds [ma]
63 A. Matsuzawa,Titech 63 eff eff GBW _ close I ds ' o eff ' α pi ' I o ds α ' I po o ds α pi ' I o ds 0.8m dd.8 N bit f c [MHz] eff [] eff [] I ds [ma] I ds [ma]
64 A. Matsuzawa,Titech 64 90nm eff eff 0.8m90nm 8bit 0bit f c [MHz] f c [MHz] eff [] I ds [ma] eff [] I ds [ma]
65 OP A. Matsuzawa,Titech 65
66 A. Matsuzawa,Titech 66 OP PMOS NMOS NMOS NMOS 40dB PMOS/ eff out out dd-4eff dd-0.7 out- out eff %
67 A. Matsuzawa,Titech 67 OP OP dd eff dd-5eff dd-.0 T eff 3 eff
68 A. Matsuzawa,Titech 68 OP out out S 3 M S, S 3 com a, b a c b cm bc I out a S 4 b S S a b cm I ss out M b, b OP S 3 M S, S 3 out S4S4 M S 3 bc M a, b a, b cm 4 0
69 A. Matsuzawa,Titech 69
70 A. Matsuzawa,Titech 70 eff dd Q Q f s ( sig com _ out com _ in ) ( ) sig com _ out com _ in 3 eff T eff GND Q f Q ' s ' ( out com _ in ) ( ) DA com _ out com _ in Q f Qs Q f ' Q s ' out com _ out sig DA
71 A. Matsuzawa,Titech 7 MOS OP ) ( ) /g g ( g g L s m 0 o o3 p ω s m p g ω ) ( L s m u g ω m 0 o p ) /g g ( g ω c s L s L s s m p ) ( g ω m u g ω
72 A. Matsuzawa,Titech 7 D ds
73 A. Matsuzawa,Titech 73 A NMOS eff 0. A G I g g g ds m ds ds eff A
74 D G0 ( db) > 6N 0 90nm 3540dB N,PMOS PMOS I ds NMOS A. Matsuzawa,Titech 74
75 A. Matsuzawa,Titech 75 Gain(log) A tot (s) ( (0)) A (0) A tot ( 0) Aadd org A add A org (s) (s) Gain enhancement ω > ω p_ add p_ tot GBW ω p _ tot ω p _ add ω p _ org ω u _ add ω u _ tot ω(log)
76 A. Matsuzawa,Titech 76 s L Impedance (log) pole-zero(doublet) Z tot R out ( Aadd ( s) ) Rout _ org A add (s) ω z _ doublet R out _ org ω p _ doublet f pole-zero (doublet) ω p _ tot ω p _ add ω p _ org ωu _ add ω u _ tot ω(log)
77 A. Matsuzawa,Titech 77 Pole-zero (doublet) pole-zerodoublet) out slewing period ω ω ( t) in exp u _ tot ωz ωu _ tot ( ) p _ doublet z _ doublet ω t exp( t) pole-zero _ doublet in ω p _ doublet ω ω u _ tot z _ doublet in pole-zero time
78 A. Matsuzawa,Titech 78 pole-zero A add (s) Gain(log) out ( t) β in exp ω p _ doublet z _ doublet ( βω t ) exp( ω t ) u _ tot βω u _ tot βω < ω u _ tot ω β : z _ doublet < ω p _ tot zero z _ doublet β ω u _ add γβω ω u _ tot z _ doublet ( γ.5) ω u _ add zero ω p _ tot ω(log) ω p _ add βωu _ tot ω u _ add ω u _ tot
79 A. Matsuzawa,Titech 79 0bit0.8m60MH3.5ns (0.ns.45ns.85ns /4LSB ω u _ add γ βω u _ tot
80 A. Matsuzawa,Titech 80
81 A. Matsuzawa,Titech 8 omp INp INn DD Dynamic comparators use the fast oltage fall depended on input oltage difference Fast oltage fall OUTn OUTp FN INP LK LK GND INN FP. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. an der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant Dynamic-SAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.38-39, Feb LK SN SP LK M. an Elzakker, Ed an Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, A.9uW 4.4fJ/onersion-step 0b MS/s harge- Redistribution AD, IEEE ISS 008, Dig. of Tech. Papers, pp.44-45, Feb. 008.
82 A. Matsuzawa,Titech 8 T mismatch T ミスマッチを小さくするには大きなトランジスタサイズが必要微細化により同一面積では T T (m ) T T ox LW ( T ) TOX LW δ δ δ 0.4um Nch 0.3um Nch Boron, w. Halo 0.3um Nch In w/o Halo*. LW ( µ m )
83 A. Matsuzawa,Titech 83 in in a - A - o Latch out ( a os) o a ( A) A A o os a LK Offset cancel at input nodes in - A Latch in - out A Q os os _ in Q os _ in A osl A osl LK os : Offset of the amplifier Offset cancel at output nodes Q: Feed through oltage osl : Offset in the latch
84 A. Matsuzawa,Titech 84 x y g m g m x0 y0 GND 0 τ t e 0 s s g s s g y x m y x y m x , y x y x g s m 0 m t g e τ τ, 0 g m t
85 A. Matsuzawa,Titech 85 SA AD SA-AD 5b harge Redistribution (R) SAR AD ref INp b0 b b b3 b4 OK! in INp INn 0/ SAR 7. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. an der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant Dynamic-SAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.38-39, Feb ref LK Noise Distribution INn INp 0 b0 b b b3 ERROR! b4 8 3σ σ σ omparator Threshold 3σ INn 0 0
86 A. Matsuzawa,Titech 86 ENOB SA AD0.LSB σ σ < < 0.5LSB 0.5LSB : bit deg rade : 0.5bit deg rade Ideal σ LSB/3 σ >σ σ/lsb0.4 ENOB8.09 Binary Output 0.5 ENOB d/lsb. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. an der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant Dynamic-SAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.38-39, Feb σ/lsb
87 A. Matsuzawa,Titech 87 INp σln σhn compl OUTp OUTn alid Monte arlo on 9b S-SAR ENOB0.75 INn omp Noise comph. Giannini, P. Nuzzo,. hironi, A. Baschirotto, G. an der Plas, and J. raninckx, An 80uW 9b 40MS/s Noise Tolerant Dynamic-SAR AD in 90nm Digital MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.38-39, Feb ENOB Standard Redundant NoiseTolerant ENOB0.3 ENOB8. omparators are sized so that HN ~/6 LSB and LN ~/ LSB Good ENOB improement with Noise Tolerant correction 7.75 σ/lsb σ/lsb
88 A. Matsuzawa,Titech 88
89 & 0 in S DD H out MOSFET ) Pch, Nch ON ONOFF clock ) Qinj oxwl inj ( DD THN ( in) A. Matsuzawa,Titech 89 H ox WL o H clock inj DD H T in )
90 /5 DD M M M M ( M M ) L MM M A. Matsuzawa,Titech 90
91 A. Matsuzawa,Titech 9 S OP g H S S 3 in H S S x T d S S g out T d S 3
92 A. Matsuzawa,Titech 9 G H x Q G H G G G H H H Q Q Q Q, G H G G G H H H in H Q Q Q Q Q Q Q Q H in H H in H Q Q H H in out x G H G x Q Q H G x G x
93 A. Matsuzawa,Titech 93 MOS ON T
94 ブートストラップによりスイッチのオン抵抗を下げて 信号依存性を無くし 歪みを押さえることができる Input oltage () A. Matsuzawa,Titech 94
95 A. Matsuzawa,Titech 95
96 A. Matsuzawa,Titech 96 kt/ noise SNR R n L L out dω 4kTR π n ( ωr ) ( ),, SNR (db) ( ),, ( ) 3,, ( ) 5,, kt n nkt n: configuration coefficient FS SNR( db ) 0 log 8nkT 4bit bit n 0bit apacitance (pf) FS 5 FS 3 FS FS
97 A. Matsuzawa,Titech 97 FoM AD Resolution o (pf) ADSA ADFoM FoM63fJ/on. step I dd (ma) P d (mw) FoM(fJ) M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A. 4.5mW 0b, 00MS/s Pipeline AD in a 65nm MOS, IEEE ISS 008, Dig. of Tech. Papers, pp.50-5, Feb SAAD Resolution 0 4 FoM4.4fJ/on. step L (ff) P d (mw) FoM(fJ) M. an Elzakker, Ed an Tujil, P. Geraedts, D. Schinkel, E. Klumperink, B.Nauta, A.9uW 4.4fJ/onersion-step 0b MS/s harge-redistribution AD, IEEE ISS 008, Dig. of Tech. Papers, pp.44-45, Feb. 008.
98 AD A. Matsuzawa,Titech 98 SA AD
99 A. Matsuzawa,Titech 99
100 A. Matsuzawa,Titech 00 0 f f s - s G DA s i - out G
101 f f s - G s DA s i pi - out G s ( ) Q f s ( DA i ) f ( out i ) pii Q ' A. Matsuzawa,Titech 0 s Q Q' out G i out s s s f f s pi f f G DA
102 A. Matsuzawa,Titech 0, out ref ref /4 LSB - ref /4 ref /4 f s f s - ref ref in : DA ref s - ref /4 : DA 0 s- ref /4 DA - ref DA 0 DA ref δ δ < LSB 4 ref N 4 - ref
103 A. Matsuzawa,Titech 03 ( ) ( ) DA c c s f pi f s DA f s f s s out G ( ) f c s ( ) DA s c δ 4 4 < δ δ N ref LSB ref c ref ref c δ ref c ref c δ 4 4 N c <
104 A. Matsuzawa,Titech 04 0bit/4LSB
105 A. Matsuzawa,Titech 05 /8LSB0bit AD pi f out s s s f f s pi f f G DA
106 δ δ out δ out s 3 G 3 ref 3 4 G ref 3 4 G DA ( ) s δ δ 3 G N G > 6 ref G ref < 3 ( ) DA ref G N s 3 ref 8 ref G DA 3 G δ δ - ref pi f LSB < 8 ref N 8 out ref ref - ref /4 ref /4 ref in N0 76dB - ref A. Matsuzawa,Titech 06
107 A. Matsuzawa,Titech 07 τ f f_close fs50mhz, /3 0bit, /8LSB 00MHz ω _ close _close ω_ close π t ss out T 3 3f e t τ in s ln N 0.7N t ss T/f s error e t τ in /8LSB
108 A. Matsuzawa,Titech 08 out ref - ref /4 ref /4 ref ref δ δ e 4 δ δ ref e tss τ < 0.7 ( N ) t τ ss t τ ss < ref N 8 - ref ref in τ πf f _ close πf _ close _ close > 3f > s < 3f 3f s s 0.7 π 0.7 ( N ) ( N ) ( N ) f ( N ) 0.7 s 3 - ref 00 f _ close > ( MHz) 3 370( MHz)
ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp)
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1 CMOS 0.35um CMOS, 3V CMOS 2 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4 5 f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz]
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http://www.ike-dyn.ritsumei.ac.jp/ hyoo/wave.html 1 1, 5 3 1.1 1..................................... 3 1.2 5.1................................... 4 1.3.......................... 5 1.4 5.2, 5.3....................
AD5302/AD5312/AD5322: 2.5 ～ 5.5 V 電源、230 μA 消費電流、デュアル、レール to レール電圧出力の 8 ／ 10 ／ 12 ビット D/A コンバータ
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positron 1930 Dirac 1933 Anderson m 22Na(hl=2.6years), 58Co(hl=71days), 64Cu(hl=12hour) 68Ge(hl=288days) MeV : thermalization m psec 100
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TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA Vac/10 A [85-AA-0003] m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A [ ] 2016
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No. IB028901 Nov. 2016 1. 11 TOS7200 2. 14 3. 19 4. 23 5. 39 6. 49 7. 51 TOS7200 CD-ROM DUT PC 1.0X p.15 NEMA5-15 125 Vac/10 A [85-AA-0003] 1 2.5 m : CEE7/7 : 250Vac/10 A [85-AA-0005] : GB1002 : 250Vac/10A
AD8515: 1.8 V 低電力 CMOS レール to レール入力／出力オペアンプ
REV. REVISION 15-6891 1-16-1 3 542 82 532-3 3-5-36 MT 2 6 635 6868 AD8515 1.8V CMOS to 1.8 5V 6mV SOT23 2.7V/µs 5MH to 2pA 1.8V 45µA PCMCIA PDA AD8515 1.8Vto SOT23-5L AD8515 5MHz 1.8V1mV to 2.7V/µs ASIC
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AN5637
IC SECAM IC SECAM IC 1 SECAM Unit : mm 19.2±0.3 16 9 1 8 (0.71) 0.5±0.1 Seating plane 2.54 1.22±0.25 DIP016-P-0300D 6.2±0.3 5.20±0.25 1.10±0.25 3.05±0.25 7.62±0.25 3 to 15 0.30 +0.10 ) (DIP016- P-0300M)
2012 September 21, 2012, Rev.2.2
212 September 21, 212, Rev.2.2 4................. 4 1 6 1.1.................. 6 1.2.................... 7 1.3 s................... 8 1.4....................... 9 1.5..................... 11 2 12 2.1.........................
(1) (2) (1) (2) 2 3 {a n } a 2 + a 4 + a a n S n S n = n = S n
. 99 () 0 0 0 () 0 00 0 350 300 () 5 0 () 3 {a n } a + a 4 + a 6 + + a 40 30 53 47 77 95 30 83 4 n S n S n = n = S n 303 9 k d 9 45 k =, d = 99 a d n a n d n a n = a + (n )d a n a n S n S n = n(a + a n
V 0 = + r pv (H) + qv (T ) = + r ps (H) + qs (T ) = S 0 X n+ (T ) = n S n+ (T ) + ( + r)(x n n S n ) = ( + r)x n + n (d r)s n = ( + r)v n + V n+(h) V
I (..2) (0 < d < + r < u) X 0, X X = 0 S + ( + r)(x 0 0 S 0 ) () X 0 = 0, P (X 0) =, P (X > 0) > 0 0 H, T () X 0 = 0, X (H) = 0 us 0 ( + r) 0 S 0 = 0 S 0 (u r) X (T ) = 0 ds 0 ( + r) 0 S 0 = 0 S 0 (d r)
news
ETL NEWS 1999.9 ETL NEWS 1999.11 Establishment of an Evaluation Technique for Laser Pulse Timing Fluctuations Optoelectronics Division Hidemi Tsuchida e-mail:tsuchida@etl.go.jp A new technique has been
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機器用センサ Grid-EYE Grid-EYE Grid-EYE Grid-EYE Grid-EYE 着座検知 扉開閉 洗濯機の水位検知 電子レンジ PS-A 微圧タイプ 水位検知 Grid-EYE 温度計測 位置検知 熱 軸GF 赤外線アレイセンサ Grid-EYE 設計 仕様について予告なく変更する場合があります ご購入及びご使用前に当社の技術仕様書などをお求め願い それらに基づいて購入及び使用していただきますようお願いします
AD9833: 低消費電力 20 mW 2.3 〜 5.5 V プログラマブル波形発生器
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7 V typ 7 0 V MSOP : 40 V+ V SENSE DC/DC BIAS CIRCUIT CURRENT COMPENSATION I OUT COM BIAS ALPHA 094-00 V PNP 0 7 V typ PNP PNP REV. A REVISION 007 Analog Devices, Inc. All rights reserved. 0-9 -- 0 40
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Dual High Speed, Low Power, Low Distortion, Voltage Feedback Amplifiers Literature Number: JAJS854 100MHz 3000V/ s 50mA 2.3mA/ 15V ADSL 5V VIP III (Vertically Integrated PNP) LM6171 Dual High Speed, Low
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