THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS TECHNICAL REPORT OF IEICE. [ ] I/O Abstr

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1 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS TECHNICAL REPORT OF IEICE. [ ] fukushima@nitech.ac.jp I/O Abstract [Invited] High-Performance Computing Programming for Image Processing Based on Computer Architecture Norishige FUKUSHIMA Nagoya Institute of Technology Gokiso-cho, Showa-ku, Nagoya, Aichi fukushima@nitech.ac.jp In this report, we review a parallelized and vectorized programming for high performance image processing and its design pattern. Moore s indecates the number of transisters in a chip are exponentially increasing, but computer archtechture is also formming complex. For high performance computing, programming utilizing the knowledge of the archecture is essential. Beside, incresing of memory transfar speed is moderate than the computaion performance. The fact is also imortant for image processing programming. Experimentatl results show that simple image transformation, convolution, and complex upsampling are accelerated with effective programming. Key words Image Processing Programming, Design Pattern, High Performance Computing, Parallerization, Vectorization. [] 2004 Pentium 4 SMT Intel Core Core i9 7980XE 8 52 AVX-52

2 FMA FLOPS : SMT L2 CPU OpenCV 999 Image Processing Library (IPL) 997 AMD Ryzen Intel CPU CPU CPU Intel x Intel Pentium GHz 207 CPU 4 GHz 2000 Pentium Pendium D CPU Pentium Core CPU 2009 Core i SIMD [2] Intel SIMD 997 MMX 64 SSE AVX AVX Intel AMD 3D Now! SSE ARM NEON SIMD 28 SIMD Pentium III (999 ) SSE SSE 2 SIMD SIMD FPU 2 3 Pentium 4 (2000 ) 2 Core GFLOPS 4 コア 6 コア 2 コアバンド幅 [GB/S] 8 コア AVX2/FMA 8 コア AVX-52 クアッドチャネル FSBの廃止 AVX Intel CPU FLOPS SSE Core i 2 20, Sandy Bridge AVX 8 FMA Core i 4 Haswell Xeon Phi 6 AVX CPU FMA FLOPS add, sub, mul, div max/min rcp rsqrt cmp dp ceil, floor, round popcount SIMD RGB gather AVX2 204 scatter AVX Intel CPU FLOPS 990 I/O Core i L 4 L2 2 L

3 2. 4 FLOPS FLOP I/O FLOPS F/B B/F B/F 2 28FLOPS/64GB/s=0.5 B/F Core i9 7980XE 748.8GFLOPS/85.3GB/s=0.4 B/F [3] 2 Core i9 7980XE F/B y = x I/O I/O Intel Parallel Studio CPU パフォーマンス [GFLOPS] マシンの理論演算強度演算能力の理論上限 (493.3GFLOPS) 各メモリ帯域の上限メモリ最適化プログラムを天井に近づけるように最適化並列化低演算強度処理ベクトル化メモリアクセスでバウンド演算強度 [flop/byte] メモリ最適化並列化ベクトル化中演算強度処理パフォーマンスが下がるアルゴリズムに変更してでも演算強度を上げる並列化高演算強度処理理論値まで高速化ベクトル化 Intel CPU FLOPS [4] N S(N) = ( P ) + P N N P S(N) = () ( P ) + P N + f(n) (2) 3 P = 0.8, 0.9 f(n) = 0, 0.0N 3. 2 R G B N N 3

4 Speed up ratio p=0.9, f(n)=0) p=0.9, f(n)=0.00n p=0.8, f(n)=0) p=0.8, f(n)=0.00n The numper of cores 3 [5] IIR Pthreads OpenMP Intel Cilk Plus Intel TBB Microsoft Parallel Patterns Library Concurency 3. 4 load 6, 32, 64 I/O SIMD Intrinsic function Visual Studio GCC ICC OpenMP OpenMP4.0 SIMD SIMD OpenMP Visual Studio OpenMP2.0 set shuffle, permute blend gather/scatter gather scatter shuffle, permute, blend gather/scatter x, (x + ) 3 set

5 r O(r 2 ) O(r) L CPU SIMD GPU CUDA FPGA HDL OpenCL CPU GPU FPGA CPU (Domain Spesific Language: DSL) [6], [7] Halide DSL C++ Halide OpenCV FPGA ax + b f(x) = a 0 + a x + a 2x a n x n (3) C++ AVX OpenMP exp C++ C++ exp C++ 2 exp I/O 8MB L L L2 map 4. 2 [8] = {r, g, b} J J p = 2 p q Ip Iq 2 exp( ) exp( )I q (4) N 2σ s 2σ r q ω p p, q ω σ s,r 5

6 4 速度向上比速度向上比 ax+b-mem ax+b-c++ exp-mem exp-c 画像サイズ [pixel] C OMP math lut3set lut3gather lutset lutgather 画像サイズ [pixel] N exp( Ip Iq 2 2σ r )=exp( (rp rq)2 2σ r ) exp( (gp gq)2 ) exp( (bp bq)2 ) (5) 2σ r 2σ r exp( Ip Iq 2 )=exp( ( (rp r q) 2 + (g p g q) 2 + (b p b q) 2 ) 2 ) (6) 2σ r 2σ r EXP2[ d ] = exp( d2 2σ ) round( ) = C++ FIR set gather LUT [9] 2 2 C ms 0.3 ms 0.52 ms 0.33 ms OpenCV Cubic 5. CPU GPU JP7H0764 [] G.E. Moore, Cramming more components onto integrated circuits, Electronics Magazine, vol.9, 965. [2] M. Flynn, Some computer organizations and their effectiveness, IEEE Trans. on Computers, vol.c-2, no.9, pp , 972. [3] S. Williams, A. Waterman, and D. Patterson, Roofline: an insightful visual performance model for multicore architectures, Communications of the ACM, vol.52, no.4, pp.65 76, [4] G.M. Amdahl, Validity of the single processor approach to achieving large scale computing capabilities, Proc. Spring Joint Computer Conference, pp , AFIPS 67, 967. [5] M.D. McCool, A.D. Robison, and J. Reinders, Structured parallel programming: patterns for efficient computation, Elsevier, 202. [6] J. Ragan-Kelley, C. Barnes, A. Adams, S. Paris, F. Durand, and S. Amarasinghe, Halide: a language and compiler for optimizing parallelism, locality, and recomputation in image processing pipelines, ACM SIGPLAN Notices, vol.48, no.6, pp , 203. [7] J. Hegarty, J. Brunhaver, Z. DeVito, J. Ragan-Kelley, N. Cohen, S. Bell, A. Vasilyev, M. Horowitz, and P. Hanrahan, Darkroom: compiling high-level image processing code into hardware pipelines., ACM Trans. Graph., vol.33, no.4, pp.44, 204. [8] C. Tomasi and R. Manduchi, Bilateral filtering for gray and color images, Proc. International Conference on Computer Vision, pp , 998. [9] D. Zhou, X. Shen, and W. Dong, Image zooming using directional cubic convolution interpolation, IET image processing, vol.6, no.6, pp ,

23 Fig. 2: hwmodulev2 3. Reconfigurable HPC 3.1 hw/sw hw/sw hw/sw FPGA PC FPGA PC FPGA HPC FPGA FPGA hw/sw hw/sw hw- Module FPGA hwmodule hw/sw FPGA h

23 Fig. 2: hwmodulev2 3. Reconfigurable HPC 3.1 hw/sw hw/sw hw/sw FPGA PC FPGA PC FPGA HPC FPGA FPGA hw/sw hw/sw hw- Module FPGA hwmodule hw/sw FPGA h 23 FPGA CUDA Performance Comparison of FPGA Array with CUDA on Poisson Equation (lijiang@sekine-lab.ei.tuat.ac.jp), (kazuki@sekine-lab.ei.tuat.ac.jp), (takahashi@sekine-lab.ei.tuat.ac.jp), (tamukoh@cc.tuat.ac.jp),