ネットリストおよびフィジカル・シンセシスの最適化

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1 11. QII Quartus II Quartus II atom atom Electronic Design Interchange Format (.edf) Verilog Quartus (.vqm) Quartus II Quartus II Quartus II Quartus II 1 Quartus II Quartus II Altera Corporation 11 1

2 Quartus II Volume 2 LogicLock SignalTap II HDL Quartus II atom Quartus II Preserve Register preserve Keep Combinational Logic keep Quartus II Quartus II Volume 1Quartus II 11 2 Altera Corporation

3 Assignments Settings 11-1 Category Analysis & Synthesis Settings Synthesis Netlist Optimizations Synthesis Netlist Optimizations WYSIWYG 11 6 Altera Corporation 11 3

4 Quartus II Volume 2 WYSIWYG atom Perform WYSIWYG primitive resynthesis (using optimization technique specified in Analysis & Synthesis settings) atom Electronic Design Interchange Format Verilog Quartus Assignments Settings Category Analysis & Synthesis Settings Synthesis Netlist Optimizations Perform WYSIWYG primitive resynthesis (using optimization technique specified in Analysis & Synthesis settings) WYSIWYG Perform WYSIWYG primitive resynthesis HardCopy Stratix Cyclone MAX II APEX Perform WYSIWYG primitive resynthesis Quartus II atom LE Quartus II Optimization Technique Assignments Settings Category Analysis & Synthesis Settings Analysis & Synthesis Settings Optimization Technique Speed Area Balanced Quartus II Balanced Optimization Technique Quartus II Volume 1Quartus II 11-2 Quartus II 11 4 Altera Corporation

5 11-2. WYSIWYG Un-Map LE Atom Netlist LE LE Re-Map LE LE Place & Route Quartus II Perform WYSIWYG primitive resynthesis Quartus II WYSIWYG PerformWYSIWYG primitive resynthesis LCELL LE I/O DDR Double Data Rate I/O DSP / IP Intellectual Property Verilog Quartus Electronic Design Interchange Format atom Quartus II Verilog Quartus Electronic Design Interchange Format Altera Corporation 11 5

6 Quartus II Volume 2 Netlist Optimizations Never Allow WYSIWYG Assignments Assignment Editor WYSIWYG Perform gate-level register retiming Quartus II Arria GX HardCopy Stratix Cyclone MAX II APEX Assignments Settings Category Analysis & Synthesis Settings Synthesis Netlist Optimizations Synthesis Netlist Optimizations Perform gate-level register retiming Perform gate-level register retiming Power-Up Don t Care Power-Up Don t Care Assignments Settings Category Analysis & Synthesis Settings Analysis & Synthesis Settings More Settings Power-Up Don't Care Power-Up Level ns 11 6 Altera Corporation

7 11-3. atom Perform WYSIWYG primitive resynthesis Quartus II Quartus II 11-4 Quartus II atom LCELL DSP / / Altera Corporation 11 7

8 Quartus II Volume VCC GND Processing Compilation Report Analysis & Synthesis Optimization Results Netlist Optimizations Gate-level Retiming Altera Corporation

9 11-6. Netlist Optimizations Never Allow f MAX t SU t CO / SERDES Netlist Optimizations Never Allow 2 2 Altera Corporation 11 9

10 Quartus II Volume 2 Retiming Meta-Stability Register Sequence Length 2 0 Assignments Settings Settings Analysis & Synthesis Settings More Settings 1 n > n Netlist Optimizations Always Allow t SU /t CO f MAX Quartus II t SU t CO f MAX Assignments Settings Category Analysis & Synthesis Settings Synthesis Netlist Optimizations Synthesis Netlist Optimizations Allow register retiming to trade off Tsu/Tco with Fmax Perform gate-level register retiming Allow register retiming to trade off Tsu/Tco with Fmax I/O I/O 1 I/O Altera Corporation

11 Quartus II Analysis & Synthesis quartus_map Quartus II Post-Synthesis LogicLock Quartus II Volume 1Quartus II LogicLock / 1 LogicLock Quartus II Assignments Settings Category Compilation Process Settings Compilation Process Settings Save a node-level netlist of the entire design into a persistent source file Verilog Quartus Quartus II atom_netlists Verilog Quartus Quartus II Verilog Quartus Assignments Altera Corporation 11 11

12 Quartus II Volume 2 Settings Category Compilation Process Settings Compilation Process Settings File name Verilog Quartus Quartus II Verilog Quartus Assignments Back-Annotate Assignments HDL Verilog Quartus Verilog Quartus Quartus II Quartus II Stratix Cyclone HardCopy II HardCopy II FPGA FPGA HardCopy HardCopy II Altera Corporation

13 HardCopy Quartus II Volume 1Quartus II Support of HardCopy Series Devices Assignments Settings 11-7 Category Fitter Settings Physical Synthesis Optimizations Altera Corporation 11 13

14 Quartus II Volume 2 Physical synthesis effort Normal Extra effort Fast effort Normal Netlist Optimizations Processing Compilation Report Category Fitter and select Compilation Report Netlist Optimizations Never Allow Assignments Assignment Editor Settings Fitter Settings Physical Synthesis Optimizations Perform automatic asynchronous signal pipelining Quartus II Altera Corporation

15 Perform automatic asynchronous signal pipelining Quartus II Recovery/Removal Analysis Recovery/Removal Analysis Assignments Settings Category Timing Requirements & Options Timing Requirements & Options More Settings Quartus II Netlist Optimization logic Never Allow Quartus II Assignments Settings Category Fitter Settings Physical Synthesis Optimizations Physical Synthesis Optimizations Perform physical synthesis for combinational logic LE LUT Altera Corporation 11 15

16 Quartus II Volume LUT LUT 2 LUT Quartus II LUT 2 LUT LUT LUT Physical synthesis for combinational logic LUT DSP I/O IOE Quartus II LAB Netlist Optimizations Never Allow Netlist Optimizations Always Allow Altera Corporation

17 Settings Fitter Settings Physical Synthesis Optimizations Perform register duplication fitter Quartus II Quartus II 1 LAB t SU I/O Netlist OptimizationsNever Allow Altera Corporation 11 17

18 Quartus II Volume 2 I/O Quartus II Volume 2 LogicLock Design Methodology Netlist Optimizations Always Allow Settings Fitter Settings Physical Synthesis Optimizations Perform register retiming fitter Quartus II Perform gate-level register retiming 11 6 Quartus II 1 LAB SERDES I/O Netlist Optimizations Never Allow I/O Quartus II Volume 2 LogicLock Design Methodology Netlist Optimizations Always Allow Altera Corporation

19 Quartus II Post-fit LogicLock Quartus II Volume 1 Quartus II LogicLock / 1 LogicLock Quartus II Settings Compilation Process Settings Save a node-level netlist into a persistent source file (Verilog Quartus Mapping File) Verilog Quartus Quartus II atom_netlists Verilog Quartus Quartus II Verilog Quartus Settings Compilation Process Settings File name Altera Corporation 11 19

20 Quartus II Volume 2 Back-Annotate Assignments LE Verilog Quartus Assignments Back-Annotate Assignments Quartus II Verilog Quartus HDL Quartus II Verilog Quartus Verilog Quartus Verilog Quartus Verilog Quartus Netlist Optimizations Netlist Optimizations = Never Allow LogicLock LogicLock Altera Corporation

21 LogicLock SignalTap II Extra effort Physical synthesis effort atom Verilog Quartus Electronic Design Interchange Format Gate-level Register Retiming WYSIWYG Primitive Resynthesis Quartus II Design Space Explorer DSE Tcl /Tk DSE Quartus II Volume 2 Quartus II Volume 2 Altera Corporation 11 21

22 Quartus II Volume 2 Tcl Quartus II Command-Line Tcl API Help Help quartus_sh --qhelp Scripting Reference Manual PDF Tcl Quartus II Volume 2 Tcl Quartus II Quartus II Settings File Reference Manual Quartus IIVolume 2Command- Line Scripting Tcl set_global_assignment -name <QSF variable name> <value> Tcl set_instance_assignment -name <QSF variable name> <value> -to <instance name> Altera Corporation

23 11 1 Quartus II (.qsf) 11 3 Quartus II Tcl Type Quartus II Perform WYSIWYG Primitive Resynthesis Optimization Technique Perform Gate-Level Register Retiming ADV_NETLIST_OPT_SYNTH_WYSIWYG_ REMAP < >_ OPTIMIZATION_TECHNIQUE ADV_NETLIST_OPT_SYNTH_GATE_ RETIME ON, OFF AREA, SPEED, BALANCED ON, OFF Power-Up Don't Care ALLOW_POWER_UP_DONT_CARE ON, OFF Allow Register Retiming to trade off Tsu/Tco with Fmax ADV_NETLIST_OPT_RETIME_CORE_ AND_IO ON, OFF Save a node-level netlist into a persistent source file Allow Netlist Optimizations LOGICLOCK_INCREMENTAL_COMPILE_ ASSIGNMENT LOGICLOCK_INCREMENTAL_COMPILE_ FILE ADV_NETLIST_OPT_ALLOWED ON, OFF <filename> "ALWAYS ALLOW", DEFAULT, "NEVER ALLOW" Altera Corporation 11 23

24 Quartus II Volume Quartus II Quartus II Tcl Type Quartus II Physical Synthesis for Combinational Logic Automatic Asynchronous Signal Pipelining Perform Register Duplication Perform Register Retiming PHYSICAL_SYNTHESIS_COMBO_LOGIC ON, OFF PHYSICAL_SYNTHESIS_ASYNCHRONOUS_ SIGNAL_PIPELINING PHYSICAL_SYNTHESIS_REGISTER_ DUPLICATION PHYSICAL_SYNTHESIS_REGISTER_ RETIMING ON, OFF ON, OFF ON, OFF Power-Up Don't Care ALLOW_POWER_UP_DONT_CARE ON, OFF Power-Up Level POWER_UP_LEVEL HIGH, LOW Allow Netlist Optimizations Save a node-level netlist into a persistent source file ADV_NETLIST_OPT_ALLOWED LOGICLOCK_INCREMENTAL_COMPILE_ ASSIGNMENT LOGICLOCK_INCREMENTAL_COMPILE_ FILE "ALWAYS ALLOW", DEFAULT, "NEVER ALLOW" ON, OFF <filename> Quartus II Volume 1 Quartus II Altera Corporation

25 logiclock_back_annotatetcl LogicLock LogicLock Tcl logiclock_back_annotate -resource_filter "REGISTER" logiclock_back_annotate backannotate Quartus II Quartus II Volume 1Integrated Synthesis Quartus II Volume 1Hierarchical & Team Based Design Quartus II Volume 1Quartus II Support of HardCopy Series Devices Quartus II Volume 2LogicLock Design Methodology Quartus II Volume 2Design Space Explorer Quartus II Volume 2Tcl Scripting Quartus II Settings File Reference Manual Quartus II Volume 2Command-Line Scripting Altera Corporation 11 25

26 Quartus II Volume 2 v7.1.0 Arria GX Arria GX v v v6.0.0 Quartus II v v v2.1 Quartus II 4.2 : APEX atom v2.0 Quaruts II v Altera Corporation

デザイン・スペース・エクスプローラ

デザイン・スペース・エクスプローラ 12. QII52008-6.1.0 Quartus II Quartus II FPGA Tcl/Tk DSEDSE DSE DSE DSE DSE Quartus II Synthesis Fitter 1 DSE Quartus II Fitter Quartus II Altera Corporation 12 1 2006 11 Quartus II Volume 2 DSE DSE 1