NCP349

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28 V NMOS PCB (OVLO) (UVLO)R ON NMOS (65 m) (En= )V in t on V out (FLAG).0 F ESD (5 kv) 28 V 65 mr DS(on) NMOS (OVLO) (UVLO) FLAG EN IEC6000 4 2( 4) 8.0 kv() 5 kv() ESDB 2 DFN6.

1 28 V NMOS PCB (OVLO) (UVLO)R ON NMOS (65 m) (En= )V in t on V out (FLAG).0 F ESD (5 kv) 28 V 65 mr DS(on) NMOS (OVLO) (UVLO) FLAG EN IEC ( 4) 8.0 kv() 5 kv() ESDB 2 DFN6.6 x 2 mm MP3 XX M IN GND FLAG DFN6 MN SUFFIX CASE 506BM MARKING DIAGRAM = Specific Device Code = Date Code = Pb Free Package PIN CONNECTIONS 2 3 XX M PAD IN (Top View) EN OUT OUT ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page of this data sheet. 6 Q Semiconductor Components Industries, LLC, 202 September, 202 Rev. 3 Publication Order Number: JP/D

2 Wall Adapter AC/DC USB F 7 IN OUT 5 IN OUT EN FLAG ENABLE/ GND Microprocessor 2 0 k V Bat P CC/CV Charger or System BATTERY 0 0 Figure. Typical Application Circuit 7 4 INPUT Gate Driver OUTPUT 5 V REF Charge Pump EN Block UVLO OVLO Control Logic and Timer 3 EN 6 FLAG Figure 2. Functional Block Diagram 2 GND 2

3 PIN FUNCTION DESCRIPTION Pin No. Symbol Function Description, 7 IN INPUT Input Voltage Pins. These pins are connected to the Wall Adapoter (AC DC, Vbus..). A F low ESR ceramic capacitor, or larger, must be connected between these pins and GND, as close as possible to the DUT. The two IN pins must be connected together to power supply. (See PCB recommendation for the pin7). 2 GND POWER Ground 3 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on the IN pins. The FLAG pin goes low when input voltage exceeds OVLO threshold or drops below UVLO threshold. Since the FLAG pin is open drain functionality, an external pull up resistor to V CC must be added. (Minimum 0 k). 4, 5 OUT OUTPUT Output Voltage Pins. These pins follow IN pins when no fault is detected. The two OUT pins must be hardwired together. 6 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection. MAXIMUM RATINGS Rating Symbol Value Unit Minimum Voltage (IN to GND) Vmin in 0.3 V Minimum Voltage (All others to GND) Vmin 0.3 V Maximum Voltage (IN to GND) Vmax in 30 V Maximum Voltage (All others to GND) Vmax 7.0 V Maximum Current (UVLO<V IN <OVLO) Imax 2.0 A Maximum Peak Current (t ms, T A = 85 C) Imax peak 4.0 A Thermal Resistance, Junction to Air (Note ) R JA 80 C/W Operating Ambient Temperature Range T A 40 to +85 C Storage Temperature Range T stg 65 to +50 C Junction Operating Temperature T J 50 C ESD Withstand Voltage (IEC ) (input only) when bypassed with.0 F capacitor Human Body Model (HBM), Model = 2 (Note 2) Machine Model (MM) Model = B (Note 3) Vesd 5 Air, 8.0 Contact Moisture Sensitivity MSL Level Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.. The R JA is highly dependent on the PCB heat sink area (connected to pin 7). 2. Human Body Model, 00 pf discharged through a.5 k resistor following specification JESD22/A4. 3. Machine Model, 200 pf discharged through all pins following specification JESD22/A5. kv V V 3

4 ELECTRICAL CHARACTERISTICS (Min/Max limits values ( 40 C < T A < +85 C) and V in = +5.0 V. Typical values are T A = +25 C, unless otherwise noted.) Characteristic Symbol Conditions Min Typ Max Unit Input Voltage Range V in.2 28 V Undervoltage Lockout Threshold (Note 4) MN, MNAE, MNAM MNBG, MNBK UVLO V in falls below UVLO threshold from 5 V to 2.7 V Undervoltage Lockout Hysteresis UVLO hyst V in rises above UVLO + UVLO hyst mv Overvoltage Lockout Threshold (Note 4) MNAE MNBG MNBK MN MNAM Overvoltage Lockout Hysteresis MN, MNAE, MNBG MNBK MNAM OVLO V in rises above OVLO threshold hyst in hyst V in versus V out Resistance R DS(on) V in = 5.0 V, EN = GND, Load connected to V out 65 0 m Supply Quiescent Current Idd No load. EN = 5.0 V A No load. EN = Gnd A UVLO Supply Current Idd uvlo V IN = 2.7 V 60 A FLAG Output Low Voltage Vol flag.2 V < V IN < UVLO Sink 50 A on/flag pin V V mv mv V IN > OVLO Sink.0 ma on FLAG pin 400 mv FLAG Leakage Current FLAG leak FLAG level = 5.0 V.0 na EN Voltage High Vih.2 V EN Voltage Low Vol 0.4 V EN Leakage Current EN leak EN = 5.0 V or GND.0 na TIMINGS Startup Delay MN MNAE MNBG, MNBK, MNAM FLAG Going Up Delay MN MNAE MNBG, MNBK, MNAM ton tstart From V in > UVLO to V out = 0.3 V (See Figures 3 & 7) From V out = 0.3 V to FLAG =.2 V (See Figures 3 & 9) Output Turn Off Time toff From V in > OVLO to V out < = 0.3 V (See Figures 4 & 8) V in increasing from 5.0 V to 8.0 V at 3.0 V/s Rload connected on V out Alert Delay tstop From V in > OVLO to FLAG < = 0.4 V (See Figures 4 & 0) V in increasing from 5.0 V to 8.0 V at 3.0 V/s Rload connected on V out Disable Time tdis From EN > =.2 V to V out < 0.3 V Rload = 5.0 (See Figures 5 & 2) ms ms s.0 s s NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature. 4. Additional UVLO and OVLO thresholds ranging from UVLO and from OVLO can be manufactured. Contact your ON Semiconductor representative for availability. 4

5 TIMING DIAGRAMS V in V out UVLO t on 0.3 V t start <OVLO V in (R DS(on) I) OVLO V in t off V out V in (R DS(on) I) FLAG t stop 0.3 V FLAG.2 V 0.4 V Figure 3. Startup Figure 4. Shutdown on Overvoltage Detection EN.2 V EN V out V in (R DS(on) I).2 V t dis 0.3 V V in FLAG OVLO UVLO t on + t start FLAG Figure 5. Disable on EN = Figure 6. FLAG Response with EN = 5

6 TYPICAL OPERATING CHARACTERISTICS 50 ms t on and t start version Figure 7. Startup V in = Ch, V out = Ch3 Figure 8. Output Turn Off Time V in = Ch, V out = Ch2 Figure 9. FLAG Going Up Delay V out = Ch3, FLAG = Ch2 Figure 0. Alert Delay V out = Ch, FLAG = Ch3 Figure. Initial Overvoltage Delay V in = Ch, V out = Ch2, FLAG = Ch3 Figure 2. Disable Time EN = Ch, V out = Ch2, FLAG = Ch3 6

7 TYPICAL OPERATING CHARACTERISTICS Figure 3. Inrush Current with C out = 00 F, I charge = A, Output Wall Adaptor Inductance H Figure 4. Output Short Circuit Figure 5. Output Short Circuit (Zoom Fig. 4) 7

8 IN OUT CONDITIONS V IN > OVLO 0 < V IN < UVLO And/Or VOLTAGE DETECTION /EN = Figure 6. Simplified Diagram IN OUT CONDITIONS /EN = 0 & VOLTAGE DETECTION UVLO < V IN < OVLO Figure 7. Simplified Diagram 28 V R DS(on) NMOSFETVout () En= UVLO(Figure 3)t on FLAG t start (Figure 3) FLAG FLAG 8

9 V out = 0 FLAG = Low Reset Timer V in < UVLO or V in > OVLO V out = 0 FLAG = Low Timer Count OVLO > V in > UVLO Timer Check T < t on T = t on Reset Timer V in < UVLO or V in > OVLO Check V in FLAG = Low Timer Count UVLO < V in < OVLO V out = Open EN = Check EN EN = 0 V out = V in V in < UVLO or V in > OVLO Timer Check T < t on T = t on UVLO < V in < OVLO Check EN UVLO < V in < OVLO EN = EN = 0 V out = Open FLAG = High Check V in V in < UVLO or V in > OVLO V out = V in FLAG = High Check V in Figure 8. State Machine 9

10 (UVLO) (UVLO) V in V in UVLO+ () V in UVLO FLAG UVLO UVLO ESD IEC F() V in GND V in ±5 kv ESD V in ±8.0 kvesd Figure 9IEC (OVLO) V out (OVLO) OVLO OVLO OVLO V in OVLOFLAG FLAG FLAG V in OVLO UVLO V in FLAG FLAG t start V bat ( M0 k) V bat 2.5 V (EN=) FLAGV in EN EN OUTIN ENOVLOUVLO NMOS FET OUTR DS(on) NMOS FET R DS(on) V out R load = 8.0 V in = 5.0 V R DS(on) = 65 m I out = 68 ma V out = 8 x 0.68 = 4.95 V NMOS= R DS(on) x Iout 2 = x = 25 mw Figure 9. Electrostatic Discharge Waveform PCB 2 ANMOSFET PCB 7() NMOS() Theta JA (C/W) Theta JA curve with PCB cu thk.0 oz Theta JA curve with PCB cu thk 2.0 oz Power curve with PCB cu thk 2.0 oz Power curve with PCB cu thk.0 oz Copper heat spreader area (mm^2) Figure Max Power (W) 0

11 ORDERING INFORMATION MNTBG MNAETBG MNBGTBG MNBKTBG MNAMTBG Device Marking Package Shipping AC AE AG AK AM DFN6 (Pb Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. SELECTION GUIDE The can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows: MNxxTxG a b c Code a b c Contents UVLO Typical Threshold a: = 2.95 V a: A = 2.95 V a: B = 3.25 V OVLO Typical Threshold b: E = 5.68 V b: G = 6.02 V b: K = 6.40 V b: = 6.85 V b: M = 7.2 V Tape & Reel Type c: B = 3000

12 PACKAGE DIMENSIONS DFN6,.6x2, 0.5P CASE 506BM 0 ISSUE O PIN ONE REFERENCE 2X 2X NOTE 4 DETAIL A D ÉÉ ÉÉ TOP VIEW DETAIL B SIDE VIEW D2 3 A A B E (A3) A 6X L L C SEATING PLANE EXPOSED Cu A L DETAIL A OPTIONAL CONSTRUCTIONS ÇÇÇ DETAIL B OPTIONAL CONSTRUCTION L MOLD CMPD A3 NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.5 AND 0.20 mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A A A REF b D.60 BSC D E 2.00 BSC E e 0.50 BSC K 0.20 L L 0.0 MOUNTING FOOTPRINT.30 E2 6X K 6 5 e BOTTOM VIEW 6X b NOTE 3 6X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your loca Sales Representative

LB IC Semiconductor Components Industries, LLC, 2013 August, 2013

LB IC Semiconductor Components Industries, LLC, 2013 August, 2013 http://onsemi.jp IC Semiconductor Components Industries, LLC, 2013 August, 2013 Δ Δ Δ μ μ μ Δ μ Δ μ μ μ μ μ μ μ μ μ Δ Δ μ μ μ μ μ μ μ μ μ μ μ 36 19 0.5 5.6 7.6 1 0.3 18 0.2 15.0 1.5 1.7max (0.7) 0.8 0.1