R1LV1616Rシリーズ

Transcription

1 お客様各位 カタログ等資料中の旧社名の扱いについて 2 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ ( 2 年 4 月 1 日ルネサスエレクトロニクス株式会社 発行 ルネサスエレクトロニクス株式会社 ( 問い合わせ先

2 OA AV RoS

3 R1V1616R 16Mb Advanced SRAM (1M word x 16bit / 2M word x 8bit) RJJ3C473Z Rev R1V1616R.1 µmcmos RAM TFT R1V1616R R1V1616R µtsop/.79mm x.49mm [.4mm] TSOP/ 12mm x 2mm [.mm] 7.mm x 8.mm BGA(fBGA [.7mm,6x8 48 ]) 2.7V 3.6V 2 =3.V 2.V TT,, B#, UB# OR OE# I/O.1µm CMOS page 1 of 1

4 Type No. R1V1616RSDS% R1V1616RSD7S% R1V1616RSD8S% R1V1616RBGS% R1V1616RBG7S% R1V1616RBG8S% R1V1616RSAS% R1V1616RSA7S% R1V1616RSA8S% Access time (Note) 7 8 (Note) 7 8 (Note) 7 8 Package 3mil 2pin plastic µ TSOP(II) (normalbend type) (2PTG) 7.mmx8.mm fbga.7mm pitch 48ball 12mm x 2mm plastic TSOP(I) (normalbend type) (48P3R). SRAM % R I Temperature Range ~ +7 ºC 4 ~ +8 ºC page 2 of 1

5 page 3 of 1 48pin TSOP BYTE# DQ A OE# DQ8 DQ1 DQ9 DQ2 DQ DQ3 DQ11 DQ4 DQ12 DQ DQ13 DQ6 DQ14 DQ7 DQ1/A A7 A6 A11 A A A13 A12 A14 A9 A8 A A4 A3 A2 A1 WE# A19 UB# 26 2 B# A18 A17 A16 2pin µtsop 48pin fbga A B C D E F G DQ2 A7 DQ DQ A2 DQ1 DQ3 DQ4 DQ6 A1 A4 A6 A A17 A16 A1 A A3 A14 OE# UB# DQ14 DQ12 DQ11 DQ9 B# DQ1 DQ13 DQ DQ7 WE# A13 A12 A19 DQ8 N.C. A11 A A9 A8 A18 or BYTE# A16 DQ A OE# DQ8 DQ1 DQ9 DQ2 DQ DQ3 DQ11 DQ4 DQ12 DQ DQ13 DQ6 DQ14 DQ7 DQ1/A A18 A17 A11 A A A13 A12 A14 A9 A8 A7 A6 A A4 A1 A2 A3 WE# A B# UB#

6 Pin name A to A19 DQ to DQ1 & WE# OE# B# UB# BYTE# Function Address input Data input/output Chip select Write enable Output enable ower byte select Upper byte select Power supply Ground Byte (x8 mode) enable input Non connection A A19 B# UB# BYTE# ADDRESS BUFFER DECODER Memory Array 4876 Words x 16BITS OR Words x 8BITS COCK GENERATOR x8/x16 SWITCING CIRCUIT SENSE Amp. SENSE Amp. DATA SEECTOR DATA SEECTOR OUTPUT BUFFER OUTPUT BUFFER DATA INPUT BUFFER DATA INPUT BUFFER DQ DQ7 DQ8 DQ1 / A1 WE# OE# BYTE# 2pin utsop 48pin TSOP page 4 of 1

7 BYTE# B# UB# WE# OE# DQ7 DQ814 DQ1 Operation ighz ighz ighz Stand by ighz ighz ighz Stand by ighz ighz ighz Stand by Din ighz ighz Write in lower byte Dout ighz ighz Read from lower byte ighz ighz ighz Output disable ighz Din Din Write in upper byte ighz Dout Dout Read from upper byte Din Din Din Write Dout Dout Dout Read Din ighz A1 Write Dout ighz A1 Read Parameter Symbol Value Unit Power supply voltage relative to. to +4.6 V Terminal voltage on any pin relation to VT.* 1 to +.3* 2 V Power dissipation PT.7 W Operation temperature Topr R ver. I ver. to +7 4 to +8 ºC ºC Storage temperature Tstg 6 to + ºC Storage temperature range under bias Tbias R ver. I ver. to +7 4 to +8 ºC ºC 1: 3 2.V(MIN) 2: +4.6V page of 1

8 Parameter Symbol Typ. Unit Note Supply voltage V V Input high voltage VI V Input low voltage VI.2.4 V 1 Ambient temperature range R ver. I ver. Ta ºC ºC 2 2 1: 3 2.V Min) 2: R/I DC Parameter Symbol Typ. *1 Unit Test conditio *2 Input leakage current II 1 Vin= to Output leakage current Io 1 =VI or =VI or OE# = VI or WE# =VI or B# =UB# =VI,VI/O= to Average operating current Icc1 Icc ma ma cycle, duty =% I I/O = ma, =VI, =VI Others = VI / VI Cycle time = 1 µs, I I/O = ma,.2v, VCC.2V VI VCC.2V, VI.2V, duty=% Standby current ISB.1.3 ma =VI Standby current ISB ~+2ºC ~+4ºC ~+7ºC ~+8ºC V in V (1) V.2V or (2).2V,.2V or (3)B# =UB#.2V,.2V,.2V Average value Output hige voltage VO 2.4 V IO = 1mA Output ow voltage VO.4 V IO = 2mA 1: Typ =3.V Ta=+2 ºC 2: BYTE# 2pin utsop 48pin TSOP BYTE#.2V or BYTE#.2V page 6 of 1

9 (Ta=+2ºC, f=1mz) Parameter Symbol Typ. Unit Test conditio Note Input capacitance C in pf V in = V 1 Input / output capacitance C I/O pf V I/O = V 1 1: AC º º 1.4V DQ C=3pF R=Ω 1: R/I page 7 of 1

10 Parameter Symbol R1V1616R** S (Note) R1V1616R** 7S R1V1616R** 8S Unit Notes Read cycle time trc 7 8 Address access time taa Chip select access time tacs1 ta Output enable to output valid toe Output hold from address change to B#,UB# access time tba 7 8 Chip select to output in lowz tcz 2,3 B#,UB# enable to lowz tbz 2,3 Output enable to output in lowz toz 2,3 Chip deselect to output in highz tcz1 tcz ,2,3 1,2,3 B#,UB# disable to highz tbz ,2,3 Output disable to output in highz toz ,2,3 page 8 of 1

11 Parameter Symbol R1V1616R** S (Note) R1V1616R** 7S R1V1616R** 8S Unit Notes Write cycle time twc 7 8 Address valid to end of write taw 6 7 Chip selection to end of write tcw 6 7 Write pulse width twp B#,UB# valid to end of write tbw 6 7 Address setup time tas 6 Write recovery time twr 7 Data to write time overlap tdw Data hold from write time td Output active from end of write tow 2 Output disable to output in highz Write to output in highz toz twz ,2 1,2. SRAM taa 7 trc 7 1. tcz, toz,twz,tbz tz max tz min 4. ow igh WE# ow B# UB# ow twp ow igh WE# ow B# UB# ow igh ow WE# igh B# UB# igh twp. tcw ow igh 6. tas 7. twr WE# igh ow page 9 of 1

12 BYTE# (2pin µtsop 48pin TSOP Parameter Symbol R1V1616R** S R1V1616R** 7S R1V1616R** 8S Unit Notes Byte setup time tbs ms Byte recovery time tbr ms BYTE# tbs tbr BYTE# page of 1

13 trc A~19 (Word Mode) A1~19 (Byte Mode) B#,UB# Valid address taa tba to tacs1 tbz tcz1 OE# WE# = "" level DQ~1 (Word Mode) DQ~7 (Byte Mode) ta toe toz tcz tbz toz Valid data tcz2 page 11 of 1

14 (1) WE# COCK) A~19 (Word Mode) A1~19 (Byte Mode) B#,UB# twc Valid address tbw tcw tcw taw WE# tas twp twz twr tow tdw td DQ~1 (Word Mode) Valid data DQ~7 (Byte Mode) page 12 of 1

15 (2) (, COCK, OE#=VI) twc A~19 (Word Mode) A1~19 (Byte Mode) B#,UB# Valid address tbw tas tcw twr tcw WE# twp DQ~1 (Word Mode) DQ~7 (Byte Mode) tdw Valid data td page 13 of 1

16 (3) (B#,UB# COCK, OE#=VI) A~19 (Word Mode) A1~19 (Byte Mode) twc Valid address tas tbw twr B#,UB# tcw tcw WE# twp DQ~1 (Word Mode) DQ~7 (Byte Mode) tdw Valid data td page 14 of 1

17 *1 Parameter Symbol MIn. Typ. *1 Unit Test conditio *2,3 for data retention VDR V V in V (1) V.2V or (2).2V,.2V or (3) B# =UB#.2V,.2V,.2V Data retention current IccDR ~+2ºC ~+4ºC ~+7ºC ~+8ºC =3.V,Vin V (1) V.2V or (2).2V,.2V or (3) B# =UB#.2V,.2V,.2V Average value Chip deselect to data retention time Operation recovery time tcdr tr ms See retention waveform 1. =3. V Ta=+2ºC 2. BYTE# 2pin utsop 48pin TSOP BYTE#.2V or BYTE.2V 3. WE# OE# B# UB# Din Vin WE# OE# B# UB# I/O ighz.2v V.2V Vin WE# OE# B# UB# I/O ighz B#,UB# tcdr 2.7V tr B# UB# 2.4V 2.4V B# =UB#.2V tcdr 2.7V tr 2.4V 2.4V.2V tcdr 2.7V tr.2v.2v page 1 of 1 V.2V

18 ( ) 8912 () 2223 ( 2F) 112 (13F) 49 ( ) 8322 ( 1F) 142 ( 3F) 1211 ( 7F) 229 ( ) 411 ( ) 311 (8F) 2 ( 8F) 221 ( ) 2171 ( F) (3) 213 (44) (42) (22) (246) (29) (2) (263) (2) (6) (76) (82) (87) (92) csc@renesas.com 27. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 8.