SystemC言語概論

Size: px

Start display at page:

Download "SystemC言語概論"

たみえきちや
4 years ago
Views:

1 SystemC CPU S/W 2004/01/29 4 SystemC 1

2 SystemC CPU S/W 3 ISS SystemC Co-Simulation 2004/01/29 4 SystemC 2

3 ISS SystemC Co-Simulation GenericCPU_Base ( ) GenericCPU_ISS GenericCPU_Prog GenericCPU_CoSim 2004/01/29 4 SystemC 3

4 sc_main Interface busmaster_read_write_if reset / load / store busmaster_adapter IO GenericCPU I/F Channel: busmaster_adapter IO nrst Port bus CLK 2004/01/29 4 SystemC 4

5 BCA UTF BCA UTF GenericCPU IO GenericCPU IO CLK Addr ncs Ready noe Data nwe Data 7CLK(140ns) CLK Addr Data Addr Data 0ns 2004/01/29 4 SystemC 5

6 Timed (Clock Clock Timed (Clock ) Timed Clock GenericCPU IO GenericCPU IO CLK(20ns) CLK CLK 7CLK(140ns) 140ns 2004/01/29 4 SystemC 6

7 (Timed :Clock ) main.cpp #include "systemc.h #include "GenericCPU.hpp #include "IO.hpp #include "busmaster_adapter.hpp int sc_main(int argc, char *argv[]) // signal<bool> nrst; sc_link_mp<int> PORT; // GenericCPU GenericCPU cpu("genericcpu"); cpu.clk(clk); cpu.nrst(nrst); cpu.bus(adapter); // IO IO io("io"); io.sp(port); // sc_clock CLK("CLK", 20, SC_NS, 0.5, 0.0, SC_NS, true); // // nrst = false; sc_start(40, SC_NS); nrst = true; // busmaster_adapter sc_start(-1); busmaster_adapter adapter("adapter"); return 0; /* this is necessary */ adapter.mp(port); 2004/01/29 4 SystemC 7

8 (GenericCPU) #include "systemc.h #include "busmaster_read_write_if.hpp class GenericCPU : public sc_module private : void init( void ); void reset( void ); void program( void ); void clock_posedge( void ); public : sc_in_clk CLK; sc_in<bool> nrst; sc_port<busmaster_read_write_if> bus; ; void GenericCPU::clock_posedge( void ) init(); while(true) /* Loop */ wait(); if( nrst.read() == false ) /* Reset */ reset(); else program(); SC_THREAD(clock_posegde); sensitive << CLK.pos(); 2004/01/29 4 SystemC 8

9 ISS SystemC Co-Simulation GenericCPU_Base ( ) GenericCPU_ISS GenericCPU_Prog GenericCPU_CoSim 2004/01/29 4 SystemC 9

ISS ROM ROM ROM init dump GenericCPU reset ROM S/W C/C++ fetch ROM SETHI reg1 0x1234 SETLO reg1 0x5678 SETLO reg2 0x0000 SETLO reg3 0x0001 SETHI reg4 0x0001

10 ISS ROM ROM ROM init dump GenericCPU reset ROM S/W C/C++ fetch ROM SETHI reg1 0x1234 SETLO reg1 0x5678 SETLO reg2 0x0000 SETLO reg3 0x0001 SETHI reg4 0x0001 STORE reg2 reg1 LOAD reg2 reg6 ADD reg2 reg3 SUB reg4 reg3 CMP reg4 reg0 JGT 0xfffb FINISH decode execute program load store SystemC nrst CLK 2004/01/29 4 SystemC 10

11 ISS iss_tf tf/genericcpu.hpp class GenericCPU : public sc_module public : private : static const int MSIZE = 0x100000; sc_string hex_file; bool dump; int memory[msize]; int Reg[8], pc, eq, lt, gt; int fetch( int p ); void decode( int decode, int &code, int &r0, int &r1, int &imm ); int execute( int code, int r0, int r1, int imm ); void dumpreg( void ); int readmem( const char *file, int *mem, int size ); int analyze_buffer( char *buffer, int *val); SC_HAS_PROCESS(GenericCPU); GenericCPU(const sc_module_name name, char *_hex_file = "test.hex", bool _dump = false) : sc_module(name), hex_file(_hex_file), dump(_dump), CLK("CLK"), nrst("nrst"), bus("bus") SC_THREAD(clock_posedge); sensitive << CLK.pos(); ; 2004/01/29 4 SystemC 11

12 ISS iss_tf tf/genericcpu.cppcpp void GenericCPU::init( void ) reset(); if(readmem( hex_file.c_str(), memory, MSIZE ) ) exit(1); void GenericCPU::program( void ) int code, r0, r1, imm; decode( fetch(pc), code, r0, r1, imm ); pc += execute( code, r0, r1, imm ); void GenericCPU::reset( void ) bus->reset(); if( dump ) dumpreg(); for(int i=0 ; i<8 ; i++) Reg[i] = 0; pc = 0; eq = 0; lt = 0; gt = 0; 2004/01/29 4 SystemC 12

13 SystemC SystemC S/W (clock_posegde) int data, exp, addr, max; init GenericCPU reset nrst CLK data = 0x ; addr = 0x ; max = 0x ; program do bus->store( addr, data ); bus->load( addr, exp ); addr++; while( --max > 0 ); cout << "Generic CPU Model : exit at << sc_simulation_time() << endl; sc_stop(); 2004/01/29 4 SystemC 13

14 SystemC prog_tf tf/genericcpu.hpp class GenericCPU : public sc_module public : private : SC_HAS_PROCESS(GenericCPU); GenericCPU(const sc_module_name name ) : sc_module(name), CLK("CLK"), nrst("nrst"), bus("bus") SC_THREAD(clock_posedge); sensitive << CLK.pos(); ; 2004/01/29 4 SystemC 14

15 SystemC prog_tf tf/genericcpu.cppcpp void GenericCPU::init( void ) reset(); void GenericCPU::reset( void ) bus->reset(); void GenericCPU::program( void ) int data, exp, addr, max; data = 0x ; addr = 0x ; max = 0x ; do bus->store( addr, data ); bus->load( addr, exp ); addr++; while( --max > 0 ); cout << "Generic CPU Model : exit at << sc_simulation_time() << endl; sc_stop(); 2004/01/29 4 SystemC 15

Co-Simulation Simulation S/W GenericCPU SystemC int data, exp, addr, max; data = 0x12345678; addr = 0x00000000; max = 0x00010000; do hw_store( addr, data ); hw_load( addr, exp ); addr++; while( --max

16 Co-Simulation Simulation S/W GenericCPU SystemC int data, exp, addr, max; data = 0x ; addr = 0x ; max = 0x ; do hw_store( addr, data ); hw_load( addr, exp ); addr++; while( --max > 0 ); hw_load/hw_store init reset program int cmd, addr, data; while(1) if(server.get(cmd,addr,data)) break; switch(cmd) case HW_LOAD: bus->load( addr, data ); break; case HW_STORE: bus->store( addr, data ); break; if(server.put(cmd,addr,data)) break; nrst CLK CoSimClient CoSimServer 2004/01/29 4 SystemC 16

17 Co-Simulation Simulation cosim_tf tf/genericcpu.hpp #include "CoSimServer.h public : class GenericCPU : public sc_module private : CoSimServer server; SC_HAS_PROCESS(GenericCPU); GenericCPU(const sc_module_name name ) : sc_module(name), server(), CLK("CLK"), nrst("nrst"), bus("bus") SC_THREAD(clock_posedge); sensitive << CLK.pos(); ; 2004/01/29 4 SystemC 17

18 Co-Simulation Simulation cosim_tf tf/genericcpu.cppcpp void GenericCPU::init( void ) server.init(); void GenericCPU::reset( void ) bus->reset(); S/W void main(int ac, char *av[]) int data, exp, addr, max; data = 0x ; addr = 0x ; max = 0x ; do hw_store( addr, data ); hw_load( addr, exp ); addr++; while( --max > 0 ); void GenericCPU::program( void ) int cmd, addr, data; while(true) if(server.get(cmd,addr,data)) break; switch(cmd) case HW_LOAD: bus->load( addr, data ); break; case HW_STORE: bus->store( addr, data ); break; if(server.put(cmd,addr,data)) break; 2004/01/29 4 SystemC 18

19 ISS SystemC Co-Simulation GenericCPU_Base ( ) GenericCPU_ISS GenericCPU_Prog GenericCPU_CoSim 2004/01/29 4 SystemC 19

20 (Inheritance) Inheritance) GenericCPU GenericCPU_XXX C++ GenericCPU GenericCPU_ISS GenericCPU_Prog GenericCPU_CoSim 2004/01/29 4 SystemC 20

21 inherit/ inherit/genericcpu_base. _Base.hpp class GenericCPU_Base : public sc_module protected : virtual void init( void ) = 0; virtual void reset( void ) = 0; virtual void program( void ) = 0; void clock_posedge( void ); public : sc_in_clk CLK; sc_in<bool> nrst; sc_port<busmaster_read_write_if> bus; SC_HAS_PROCESS(GenericCPU_Base); GenericCPU_Base(const sc_module_name name ) : sc_module(name), CLK("CLK"), nrst("nrst"), bus("bus") SC_THREAD(clock_posedge); sensitive << CLK.pos(); ; void GenericCPU_Base::clock_posedge( void ) init(); while(true) /* Loop */ wait(); if( nrst.read() == false ) /* Reset */ reset(); else program(); 2004/01/29 4 SystemC 21

22 private/public/protected C++ ( ) / public : protected : private : 2004/01/29 4 SystemC 22

23 (GenericCPU_Base) protected : virtual void init( void ) = 0; virtual void reset( void ) = 0; virtual void program( void ) = 0; (GenericCPU_XXX) private : void init( void ); void reset( void ); void program( void ); 2004/01/29 4 SystemC 23

24 GenericCPU_ISS inherit/genericcpu GenericCPU_ISS. _ISS.hpp #include GenericCPU_Base.hpp class GenericCPU_ISS : public GenericCPU_Base private : static const int MSIZE = 0x100000; sc_string hex_file; bool dump; int memory[msize]; int Reg[8], pc, eq, lt, gt; int fetch( int p ); void decode( int decode, int &code, int &r0, int &r1, int &imm ); int execute( int code, int r0, int r1, int imm ); void dumpreg( void ); int readmem( const char *file, int *mem, int size ); int analyze_buffer( char *buffer, int *val); void init( void ); void reset( void ); void program( void ); public : SC_HAS_PROCESS(GenericCPU_ISS); GenericCPU_ISS(const sc_module_name name, char *_hex_file = "test.hex", bool _dump = false) : GenericCPU_Base(name), hex_file(_hex_file), dump(_dump) ; 2004/01/29 4 SystemC 24

25 GenericCPU_Prog Prog inherit/genericcpu GenericCPU_Prog.hpp #include GenericCPU_Base.hpp class GenericCPU_Prog : public GenericCPU_Base private : void init( void ); void reset( void ); void program( void ); public : SC_HAS_PROCESS(GenericCPU_Prog); GenericCPU_Prog(const sc_module_name name) : GenericCPU_Base(name) ; 2004/01/29 4 SystemC 25

26 GenericCPU_CoSim CoSim inherit/genericcpu GenericCPU_CoSim.hpp #include GenericCPU_Base.hpp #include "CoSimServer.h class GenericCPU_CoSim : public GenericCPU_Base private : CoSimServer server; void init( void ); void reset( void ); void program( void ); public : SC_HAS_PROCESS(GenericCPU_CoSim); GenericCPU_CoSim(const sc_module_name name) : GenericCPU_Base(name) server() ; 2004/01/29 4 SystemC 26

27 inherit/main.cpp ( 1) GenericCPU cpu( GenericCPU ); cpu.clk(clk); cpu.nrst(nrst); cpu.bus(adapter); ( 2) GenericCPU *cpu; cpu = new GenericCPU( CPU ); cpu->clk(clk); cpu->nrst(nrst); cpu->bus(adapter); GenericCPU_Base *cpu; if(!strcmp(argv[1], "Prog") ) cpu = new GenericCPU_Prog("Prog"); else if(!strcmp(argv[1], "CoSim") ) cpu = new GenericCPU_CoSim("CoSim"); else if(!strcmp(argv[1], "ISS") ) else cpu = new GenericCPU_ISS("ISS"); Usage(argv[0]); cpu->clk(clk); cpu->nrst(nrst); cpu->bus(adapter); 2004/01/29 4 SystemC 27

28 ISS SystemC Co-Simulation 2004/01/29 4 SystemC 28

SystemC 2.0を用いた簡易CPUバスモデルの設計

SystemC 2.0を用いた簡易CPUバスモデルの設計 SystemC 2.0 CPU CPU CTD&SW CT-PF 2002/1/23 1 CPU BCA UTF GenericCPU IO (sc_main) 2002/1/23 2 CPU CPU CQ 1997 11 Page 207 4 Perl Verilog-HDL CPU / Verilog-HDL SystemC 2.0 (asm) ROM (test.hex) 2002/1/23