SCV in User Forum Japan 2003
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1 Open SystemC Initiative (OSCI) SystemC - The SystemC Verification Standard (SCV) - Stuart Swan & Cadence Design Systems, Inc.
2 Q0 Q1 Q2 Q3 Q4 Q5 2
3 SystemC Q0 Q1 Q2 Q3 Q4 Q5 3
4 Verification Working Group (VWG), ST, Motorola SystemC SystemC SystemC API (Formal Verification) etc. ARM, Elixent,, Infineon, Motorola, Philips Axys, Cadence, Forte, Synopsys Chemnitz, Tübingen 4
5 SystemC Verification Standard (SCV) OSCI SCV 1.0 TestBuilder(Cadence), QuickBench(Forte) OSCI WEB SCV SCV 1.0 SCV 1.0 SystemC SCV SCV (Temporal Expressions) 5
6 SCV 1.0 (Data Introspection) C/C++ Verilog PLI PLI Verilog (module, signal, event etc.) Randomization (Weighted randomization) (Constrained randomization) Sparse Array API PLI, VPI, VHDI SCV 1.0 IP 6
7 SystemC 2.0 SystemC SCV SCV C++ SystemC Standard Channels for Various MOCs Kahn Process Networks Static Dataflow, etc. Core Language Modules Ports Processes Interfaces Channels Events Add-On Libraries Verification Standard Library etc. Elementary Channels Signal, Clock, Mutex, Semaphore, Fifo, etc. Data Types Logic Type (01XZ) Logic Vectors Bits and Bit Vectors Arbitrary Precision Integers Fixed Point Numbers C++ Built-In Types (int, char, double, etc.) C++ User-Defined Types C++ Language Standard (C++) (SystemC) (SystemC) (SystemC) FIFO etc. (SystemC) (SystemC 2.1) (associative array) etc. (C++ STL) HDL Co-Sim (SystemC / EDA vendors) 7
8 SystemC CPU / Bus Master DSP / Bus Master Monitor Bus Arbiter FastMem / Slave SlowMem / Slave HW Accel / Slave ( ) Read: Addr: 0xFF12 Data: 0x0123 Write: Addr: 0xFF14 Data: 0xBEEF SystemC Simple Bus 8
9 SystemC SystemC SW(C/C++) 9
10 (Transactors) Abstract or TLM Transactor Transactor test transactor design 10
11 SystemC class transactor_if : public virtual sc_interface { public: virtual int read ( unsigned addr ) = 0; }; class transactor : public design_ports, public transactor_if { public: int read ( unsigned addr ) { wait ( clk.posedge_event() ) return data; } }; class design_ports : public sc_module { public: sc_in < bool > clk; sc_inout < sc_int<48> > data; }; test transactor design 11
12 SCV (RAND, RAND32, RAND48, CUSTOM) (RANDOM, SCAN, RANDOM_AVOID_DUPLICATE) 12
13 ( ) ( ) scv_smart_ptr<int> p; p->keep_only(0,100); p->keep_out(3,98); p->next(); ( p->set_mode(random)) RANDOM : SCAN : RANDOM_AVOID_DUPLICATE : DISTRIBUTION scv_bag<> 13
14 scv_bag<int> dist; dist.add(0,15); dist.add(1,8); dist.add(2,4); dist.add(3,2); dist.add(4,1); = 15/( ) = 50% scv_smart_ptr<int> p; p->set_mode(dist); p->next();
15 #2 scv_bag<pair<int, int> > dist; dist.add(pair<int,int>(1,3), 100); dist.add(pair<int,int>(4, 10), 30); dist.add(pair<int,int>(11, 20), 20); dist.add(pair<int,int>(21, 80), 80); scv_smart_ptr<int> p; p->set_mode(dist); p->next();
16 class packet_t { sc_uint<8> src; sc_uint<8> dest; sc_uint<32> data[8]; } // scv_smart_ptr < packet_t > p ; p->next( ); // src scv_smart_ptr < packet_t > p ; p->src.disable_randomization(); p->next( ); // my_constraint c( constraint ); c.p->next( ); // new_constraint c( constraint ); c.p->next( ); 7 // class my_constraint : public scv_constraint_base { public: scv_smart_ptr < packet_t > p ; SCV_CONSTRAINT_CTOR( my_constraint ) { SCV_CONSTRAINT ( p -> src ( )!= p -> dest ( ) ); for ( int i = 0; i < 8 ; ++ i ) SCV_CONSTRAINT ( p -> data [ i ]() < 10 ); } }; // my_constraint 6 class new_constraint : public my_constraint { public: SCV_CONSTRAINT_CTOR( new_constraint ) { SCV_CONSTRAINT_BASE( my_constraint ) SCV_CONSTRAINT ( p -> data [ 0 ]()!= p -> data [ 1 ]() ); } }; 16
17 (scv_tr_db, scv_tr_stream, scv_tr_generator) ; ; ( ) ASCII () read : addr : 0xFF data : 0xabcd read : addr : 0xFE data : 0x1234 addr : 0xFF addr : 0xFE data : 0xabcd data : 0x
18 API scv_tr_db scv_tr_stream scv_tr_generator scv_tr_handle 18
19 examples/overview int sc_main (int argc, char *argv[]) { scv_tr_db db("my_db"); scv_tr_db::set_default_db(&db); class rw_pipelined_transactor : { scv_tr_stream pipelined_stream; scv_tr_stream addr_stream; scv_tr_stream data_stream; scv_tr_generator<sc_uint<8>, sc_uint<8> > read_gen; scv_tr_generator<sc_uint<8> > addr_gen; scv_tr_generator<sc_uint<8> > data_gen; public: rw_pipelined_transactor(sc_module_name nm) : pipelined_stream("pipelined_stream", "transactor"), addr_stream("addr_stream", "transactor"), data_stream("data_stream", "transactor"), read_gen("read",pipelined_stream,"addr","data"), addr_gen("addr",addr_stream,"addr"), data_gen("data",data_stream,"data") {} virtual data_t read(const addr_t* p_addr); }; rw_pipelined_transactor::read(const rw_task_if::addr_t* addr) { addr_phase.lock(); scv_tr_handle h = read_gen.begin_transaction(*addr); scv_tr_handle h1 = addr_gen.begin_transaction(*addr,"addr_phase",h); h1.record_attribute("osci", 777); // <- Added wait(clk->posedge_event()); bus_addr = *addr; addr_req = 1; wait(addr_ack->posedge_event()); wait(clk->negedge_event()); addr_req = 0; wait(addr_ack->negedge_event()); addr_gen.end_transaction(h1); addr_phase.unlock(); data_phase.lock(); scv_tr_handle h2 = data_gen.begin_transaction("data_phase",h); h2.add_relation("related address phase", h1); // <- Added wait(data_rdy->posedge_event()); data_t data = bus_data.read(); wait(data_rdy->negedge_event()); data_gen.end_transaction(h2); read_gen.end_transaction(h,data); data_phase.unlock(); return data; } 19
20 #2 examples/overview scv_tr_stream (ID 1, name "pipelined_stream", ) scv_tr_stream (ID 2, name "addr_stream", ) scv_tr_stream (ID 3, name "data_stream", ) scv_tr_generator (ID 4, name "read", scv_tr_stream 1, begin_attribute (ID 0, name "addr", type "UNSIGNED") end_attribute (ID 1, name "data", type "UNSIGNED") ) scv_tr_generator (ID 6, name "addr", scv_tr_stream 2, begin_attribute (ID 0, name "addr", type "UNSIGNED") ) scv_tr_generator (ID 7, name "data", scv_tr_stream 3, begin_attribute (ID 0, name "data", type "UNSIGNED") ) tx_begin s tx_begin s tx_relation "addr_phase" 2 1 tx_record_attribute 2 "OSCI" INTEGER = 777 tx_end ns tx_begin ns tx_relation "data_phase" 3 1 tx_relation "Related address phase" 3 2 tx_end ns tx_end ns my_db rw_pipelined_transactor::read(const rw_task_if::addr_t* addr) { addr_phase.lock(); [ns] scv_tr_handle h = read_gen.begin_transaction(*addr); } scv_tr_handle h1 = addr_gen.begin_transaction(*addr,"addr_phase",h); piplelined h1.record_attribute("osci", 777); read// <- Added wait(clk->posedge_event()); stream bus_addr = *addr; addr_req = 1; wait(addr_ack->posedge_event()); wait(clk->negedge_event()); addr Addr addr_req = 0; stream OSCI = 777 wait(addr_ack->negedge_event()); addr_gen.end_transaction(h1); addr_phase.unlock(); data data data_phase.lock(); scv_tr_handle stream h2 = data_gen.begin_transaction("data_phase",h); h2.add_relation("related address phase", h1); // <- Added wait(data_rdy->posedge_event()); data_t data = bus_data.read(); wait(data_rdy->negedge_event()); data_gen.end_transaction(h2); tx_(begin) (end) <TransID> <GenID> <Time> read_gen.end_transaction(h,data); data_phase.unlock(); tx_relation RelName <TransID#1> <TransID#2> return tx_record_addtibute data; <TransID> AttName <Value> 20
21 SCV 1 = SystemC = SystemC or HDL (Abstract or TLM) High->Low SysC TLM or RTL HDL Low->High 2 TLM (Validation) Tr->Sig RTL HDL Sig->Tr 21
22 TLM RTL 22
23 SystemC? 23
24 SCV SystemC SystemC SCV!! SystemC SystemC SystemC Primer ( ) C++ SystemC 24
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