SI-7321M

Transcription

1 2 SPM IC SI-7321M Ver IC SI-7321M VREF / 36

2 (1) VBB=46V max10v44v (2) Logic VDD3V5.5V (3) IO(max) 1.5A (4) Clock (5) 2 4W1-2 (6) HSOP40 (7) OFF PWM OFF 3 (8) PWM OFF (9) PWM (10) Sleep (11) (12) (13) POSPOSNEG 2 / 36

3 TA=+25 VM 46 V VBB 46 V Logic VDD 6 V IO 1.5 A tw<1µs Logic VIN -0.3 VDD+0.3 V REF VREF -0.3 VDD+0.3 V VRS 2 V tw<1µs PD 3.5 W TJ 150 C TA C Tstg C Duty TJ PD 3-2 TA=+25 Min Max VM 44 V VBB V Logic VDD V VDD 0.5V REF VREF V V TC 85 C VM OUT 100V min OUT 3 / 36

4 3-3 TA=+25VBB=24V VDD=5V Min. Typ. Max. IBB 15 ma IBBS 100 µa Sleep1Sleep2 Logic IDD 5 ma MOSFET VDSS 100 V VBB=44VID=1mA MOS FET ON RDS(on) Ω ID=1.5A MOS FET Di VF V IF=1.5A fclk 250 KHz Clock Duty=50 POS Logic VIL 0.25VDD V VIH 0.75VDD V Logic IIL 1 µa IIH 1 µa V P_SEL=H VREF REF V P_SEL=L VREFS 2.0 VDD V Sleep1 REF IREF 10 µa SENSE VSENSE 0.2 V VREF=0.2V 100 SENSE ISENSE 10 µa VOCP V VSENSEVOCP topp µs PWM Flag VFlagL 1.25 V IFlagL=1.25mA VFlagH VDD-1.25 V IFlagH=-1.25mA Flag IFlagL 1.25 ma IFlagH ma SleepEnable tse 100 µs Sleep1 Sleep2 tcon 2.0 µs Clock Out ON tcoff 1.5 µs Clock Out OFF VREF 6 4VREF Sleep1 IBBSOFF Enable 4 / 36

5 3-3 TA=+25VBB=24V VDD=5V Min. Typ. Max. Mode F 100 % Mode E 98.1 % Mode D 95.7 % Mode C 92.4 % Mode B 88.2 % Mode A 83.1 % Mode % VREFVSENSE100 Mode % VREF0V1.0V Mode % Mode % Mode % Mode % Mode 3 29 % Mode % Mode % MO VMOL 1.25 V IMOL1.25 VMOH VDD-1.25 V IMOH1.25 MO IMOL 1.25 ma IMOH 1.25 ma PWM ton(min) 1.8 µs B_SEL=L 3.6 µs B_SEL=H toff 1 13 µs Mode 8 Mode F PWM toff µs Mode 4 Mode 7 toff µs Mode 1 Mode 3 5 / 36

6 4. V REF VREF OCPVSENSE 0.7V 4-1VREF Sleep1 1.75V VREF1.75V VREF / 36

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8 7. mm Cu Ni *1. Type number *2.(3 ) Lot Number(three digit) 1 1 st letter The last digit of year 2 2 nd letter Month 19 Arabic Numerals 10 O 11 N 12 D 3 3 rd letter Week Code 13 Arabic Numerals *3.(4 ) Control number(four digit 8 / 36

9 A-PET mm mm 9 / 36

10 OutB OutB OutB OutB GB GB VBB Reset Clock CW/CCW M1 M2 M3 E_SEL P_SEL B_SEL Mo Flag Ref/Sleep1 VDD GA GA OutA OutA OutA OutA MIC Reg. Pre- Driver Protect Sequencer & Sleep Circuit Pre- Driver Protect DAC DAC + Comp - OSC PWM Control Synchro Control PWM Control Comp + - OSC RsA RsA Gnd2 Gnd3 Gnd4 Sync Gnd1 Gnd1 Gnd1 Gnd1 N.C. N.C. N.C. N.C. N.C. N.C. RsB RsB Pin 1 Out/A /A 2 Out/A /A 3 N.C. 4 RsA A Pin 23 OutB B 24 OutB B 25 N.C. 26 RsB B 5 G/A /A MOS FET 27 GB B MOS FET 6 Gnd1 Gnd1 7 E_SEL 8 P_SEL 9 Sync PWM 28 Gnd1 Gnd1 29 Gnd2 Gnd2 30 Flag 31 Mo 2 10 CW/CCW 32 VDD Logic 11 Reset Logic 33 Ref/Sleep1 Sleep1 12 Clock Step Clock 13 M1 14 M2 15 M3 16 B_SEL 17 Gnd1 Gnd1 34 Gnd3 Gnd3 35 N.C. 36 VBB 37 N.C. 38 Gnd4 Gnd4 39 Gnd1 Gnd1 18 G/B /B MOS FET 40 GA A MOS FET 19 RsB B 20 N.C. 21 Out /B /B 22 Out /B /B 41 RsA A 42 N.C. 43 Out A A 44 Out A A 10 / 36

11 R110KΩ CA100µF50V R21KΩ (VR) CB10µF10V R310KΩ C10.1µF C20.1µF 2 P Io Rs Rs Ω3W Rs Ω2W (VOCP) VDD VDD 0.5V Gnd Gnd VDD GndSGndVBB GndPGnd Logic CWCCWM1M2M3ResetSyncE_SELP_SEL B_SELVDD Gnd Logic MoFlag 11 / 36

12 Low Level High Level Clock POS Edge W Edge Reset CWCCW (CW) (CCW) M1 M2 M3 Sleep RefSleep1 1 Sync PWM PWM E_SEL W POS P_SEL ON OFF B_SEL Reset Reset High Logic RefSleep1 Enable Reset Disable RefSleep1 PWM Sleep1 2 VREF<1.5VLow VREF>2.0VHigh OFFDisable Sleep1 IBB Logic Clock Sync 2 2 A B PWM 1 Sync 2 A B 8 F 12 / 36

13 2Sleep M1 M2 M3 L L L 2 Mode 8 H L L 2 Mode F L H L H H L 1-2 Mode F L L H W1-2 4 H L H 2W1-2 8 L H H 4W H H H 2 2Sleep21 OFFDisable Sleep2 Logic Hold Clock 2 Clock 100µs 3 SI-7321M Mo 2 A B High Flag P_SELLow High Low Level High Level Mo 2 2 Flag OFF Logic 12. ClockCWCCWM1M2M3ResetSyncE_SELP_SEL B_SEL (LPF) CMOS Low High 13 / 36

14 13. (1)Clock Clock W 2µs Clock 250kHz Clock Sequencer Logic Clock Clock POS W 2 CW/CCWM1M2M3E_SEL Clock 1µs 13-1 Sequencer Logic 13-1 POS E_SEL=H Reset 2µs(min) 5µs(min) 4µs(min) Clock 2µs(min) 2µs(min) CW/CCW M1 M2 M3 E_SEL 1µs(min) 1µs(min) 1µs(min) 1µs(min) W E_SEL=L Reset 2µs(min) 5µs(min) 4µs(min) Clock 2µs(min) 2µs(min) CW/CCW M1 M2 M3 E_SEL 1µs(min) 1µs(min) 1µs(min) 1µs(min) 1µs(min) 1µs(min) Sleep12 Clock 100µs (2)Reset Reset Reset Clock 2µs Reset Clock Reset )Clock Reset µs Clock 14 / 36

15 (3) CW/CCWM1M2M3 Mode Clock (4) 15 / 36

16 M1LM2LM3LMode8 M1HM2LM3LModeF Clock POS W_Egde POS NEG 16 / 36

17 M1LM2HM3LMode8,F M1 HM2 HM3 LMode F Clock POS W_Egde POS NEG 17 / 36

18 14-3W1-2 M1LM2LM3H Clock POS W_Egde POS NEG 18 / 36

19 14-42W1-2 M1HM2LM3H Clock POS W_Egde POS NEG 19 / 36

20 14-54W1-2 M1LM2HM3H Clock POS W_Egde POS NEG 20 / 36

21 Mode SLA7070M 2 Mode F Mode F100PWM 13µs 21 / 36

22 15. ()ICMIC Sequencer Logic 1Clock CWCCW M1M2M3 PWM Control OFF PWM OSCPWM SLA7070M Synchro Control Sync High A B OFF SLA7070M 2 2 A B PWM DAC DA Sequencer Logic REF Reg MOS FET Pre-Drive Protect Rs OUT Gnd PWM Disable Logic ()MOS FET 4 MOS FET MIC 22 / 36

23 16. (1)PWM Sense PWM Sense 5µs/div 500ns/div PWM µs Sense SI-7321M VRS DAC Vtrip (PWM )PWM Sense Vtirp PWM PWM PWM SENSE 23 / 36

24 16-3 Sense 16-3 Itrip REF 16-1 PWM () 20μs/div PWM ON ton(min) PWM ON ON PWM ON ON PWM ON 24 / 36

25 Itrip Itrip Itrip PWM Itrip Itrip tconv tclkmode t CONV t clk Itrip tconv ON tclk Itrip µs Sense 3.2µs SENSE 1.7μs(typ) 3.2μs(typ) Clock SenseA SenseB 500μs/div 500μs/div 25 / 36

26 PWM SI-7321M PWM PWM PWM MOS FET 16-5 SI-7321M PWM MOS FET OFFON MOSFET ON 0.5µs MOS FET / 36

27 (2) SI-7321M SI-7321M VRS VOCP 0.7V Disable VRSVOCP 16-6 VDD 1 MOS FET PWM MOS FET SI-7321M MOS FET PWM MOS FET SI-7321M PWM MOS FET VRS PWM PWM VRS SI-7321M / 36

28 28 / PWM topp topp 1 Out-Gnd

29 17. (1) Io 10-1 R1R2Rs Io r2 Io VDD Rs r1 r2 2 VREF VREF 0.1V Itrip DAC I trip V Rs REF (Mode ) (2) SI-7321M OFF PWM PWM 17-1 PWM Lm tc VM 1 R I O min 1 R t exp OFF R Rm RDS ( on) RS t C VM Rm RDS(on) MOS FET Lm toff PWM RS / 36

30 (3) SI-7321M MOS FET MOS FET VDS(AV)=140V ID=1A t=0.5µs EAV EAVVDS(AV)1/2IDt 140V1/21A [mJ] EAV 17-4 MOS FET 17-4EAV Eav [mj] 30 / 36

31 (4)VBBVDDON/OFF VBB VDD ON/OFF (5)VMVBB 9-1 ICMIC MOSFET (6) a VDDON Reset Reset Reset b Step W E_SEL 11-1 Hold c Hold Sync 2 Mode8F1 Hold 17-5 Sync 17-5 Sync Sync RC 17-6 W / 36

32 ddisablesleep1,2 DisableREF 2V Sleep1M1M2M3 High Sleep2 2 Sleep Sleep1 Enable Sleep2 HOLD Sleep2 Clock Sleep DisableSleep1sleep2 Disable Disable Clock 100µs (min) W Disable Clock NEG erefsleep1 REF 11-1 d Low VREF V EnableDisable High VREF2.0V 2 EnableDisable 1.75V REF REF V typref OCP REF Enable Disable 32 / 36

33 17-8REF f CWCCWM1M2M3ResetSyncE_SELP_SELB_SEL VDD GND gmoflag 17-9 Mo Flag / 36

34 18. SI-7321M 2 P I R 2 DS(on) P I Io RDS(on) MOSFET () (ΔTC-A)18-1 P Tj ΔTC-A ΔTJ ΔTJΔTC-APθJ-C MOSFETICMIC IC / 36

35 19. (1)MOS FET VDS(on) (2)MOS FET VF 35 / 36

36 36 / 36 RoHS DSGN-CJZ-16001