デジタルICの電源ノイズ対策・デカップリング
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- みそら いしなみ
- 4 years ago
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2 RoHS RoHS 2011/65/EU RoHS Web RoHS
3
4
5 IC 1-1 IC Power Distribution Network PDN 1-2 Power Integrity PI 1) 2) 1-3 3) 4) 5) 1-4 1
6 2
7 IC IC IC (1) (2) (3) 3
8 IC IC 2.1 IC C-MOS 2-1 C-MOS C-MOS C-MOS IC (VDD) GND 1 0 6) C-MOS ) 8) IC IC IC
9 IC 2-1 (1) (2) IC (3) IC 2-2 IC (1) (2) 5
10 (3) (1) IC IC 2-3 PDN A) IC IC B) 9) (2) (3) 2-4 IC 2-4 IC B' C B' C 6
11 2.3 6) 2-5 Insertion Loss I.L. db 50 S S21 S IC 2-6 (a) 2-6 (b) IC via 7
12 2-6 IC PDN db dB MHz 8
13 2.5 9) IC 2-9(b) (c) IC IC IC (b) (c) (a)
14 2-9 IC 2-9 (c) via 2-9 IC (b) (c) 2-9 (a) IC IC 2-9(b) L C (2-2) 2 Z T C (F) L (H) ZT IC ZT IC I(A) V(V) 10) 10
15 Z T V I = (2-3) I =0.1AV=200mV IC L =1H (2-3) ZT =2 (2-2) C 0.25F IC 0.25F (2-2) (2-2) 11
16 10MHz 3.1 MultiLayer Ceramic Capacitor MLCC 3-1 1) 3-1 ESR ESL 3-2 V Z = 1 2 π f Cap Z = 2 π f ESL 1 f 0 = 2 π Cap ESL Z ESR ESR ESL ESR ESL
17 V MLCC mm(GRM21 ) 25 (3dB) MLCC ESL ESL MLCC ESL via ESL(PCB)) 3-5 ESL(PCB)) ESL(PCB) 13
18 3.3 ESL(PCB) 3-6(a) ESL(PCB) via 3-6 ESL(PCB) ESL(PCB) 10mm MSL Micro Strip Line MHz 20dB 14
19 MHz IC 6mm FMLCC 15mm 3-8 (a) (b) 15
20 (c) 3-8(b)(c) 1/ level (V) level (V) level (V) time (ns) time (ns) time (ns) m H V 3-8 (a) (b) (c) 3-9 (b) (c) 10dB 10dB 6mm 3-8 (a)(b) 1/5 3-9 (a)(b) 8dB 1/2.5 ESL(PCB) 16
21 H V H V H V
22 3.5 ESL ESR ) 3-11 (b) 3-13 impedance (Ω) frequencymh 18
23 10 impedance (Ω) frequency MH (1) (2) (3) 10 (1) 2.6 (2) (3) 3-14 (d) ESL ESR 4 19
24 3-15~17 4MHz IC FET 3-15 MLCC F1000pF level (mv) level (mv) time (ns) level (mv) time (ns) time (ns) level (mv) level (mv) level (mv) time (ns) time (ns) time (ns) MLCC 3-14 (b) 3-14 (c) 20
25 level (mv) level (mv) time (ns) level (mv) level (mv) time (ns) time (ns) level (mv) level (mv) time (ns) time (ns) time (ns) (d) ESL MLCC ESL ESL 4 21
26 level (mv) level (mv) time (ns) level (mv) level (mv) time (ns) time (ns) level (mv) time (ns) level (mv) time (ns) time (ns) 22
27 IC ESL 4.1 ESL MLCC ESL 4-1 ESL ESL (a) LW 4-3 (a) MLCC 4-2 (b)(c) 4-3 (b) (c) 23
28 4-4 ESL L part 2L 2M = MLCC ESL mm 1F 100MHz LW 1/5 1/2 MLCC ESL 1/ MSL S ESL via ESLPCB 24
29 4-6 via via ESL PCB MLCC via via
30 4.2 ESL ESL 4.3 ESL 4-7 MLCC ESL 4-8 T ESL ESL MLCC pH MLCC 1/30 1GHz 4-9 MLCC mm 26
31 27 F 100MHz 35dB
32 via ESLPCB T ESLPCB via 2) via via IC via via IC via via via via ESL ESR via via via via ESL ESR ESL ESR via via IC via via IC via via via via ESL ESR via via via via ESL ESR ESL ESR MLCC ESLPCB MLCC F GHz 30dB 1GHz 4-8 ESL T
33 4-12 (a) 60(b) 3 100MHz 40mm30mm 4-12 MLCC (a) 60 (b) 3 (a) (b) MLCC via 29
34 30
35 4.4 IC 0.8±0.1 (1) (2) min. (2) 1.6± (3) ± ±0.1 : Electrode (in mm) 0.2 min. 0.2 min. (2) (1) (3) 0.25±0.1 (2) 0.4± ± ± ±0.1 : Electrode (in mm) 0.8± ± ± ± ±0.2 (2) (1) (3) 0.85± ±0.1 (2) 0.25±0.2 : Electrode (in mm) 1.1± ± ±0.2 (2) (1) 0.25±0.2 (2) (3) 0.3± ±0.2 : Electrode (in mm) 31
36 32 LC LC LC LC (a) (b) (a) IC (b) IC IC (2-2)
37 Z EPR Z = 2π f L Z = 1 2 π f EPC 0 2 π L EPC f = L) EPC) EPR) f 0 EPR EPC EPC EPC ESR
38 3dB ) 34
39 Z R X 10MHz 10MHz MHz 5-4 EPC Q 35
40 dB/dec EPC 100MHz EPC 100MHz 5-10 EPC 5.4 LC LC 5-11 L C 20dB/dec. 36
41 9) LC (db) dB/dec. (db) L L dB/dec (db) dB/dec. T L C IC 5-1 L L C LC L C 5-13 MLCC L LC
42 5-14 4MHz IC 1F L 10F time (ns) level (mv) level (mv) level (mv) -100 time (ns) -100 time (ns) 38
43 5.5 LC 10MHz LC 11) 5-15 LC A 5-16 (a) 5-16 (b) LC 1GHz LC 5-17 LC MHz IC 39
44 1FMLCC 2200pF 6mm 2200pF MLCC 2200pF LC 10FMLCC LC level (mv) level (mv) time (ns) time (ns) -100 time (ns) level (mv) (a) LC 5-17(b) LC 40
45 5.6 EPC IC (2-2) V = R I (5-1) ripple dc ripple V ripple R dc I ripple R dc 100m 1A 100mV 41
46
47 BLM03P 1005 BLM15P 0.6-± ± ± ± ± ± ± ±0.05 : Electrode (in mm) : Electrode (in mm) 1005 BLM15E 1005 BLM15G 0.25± ± ± ± ± ± ± ±0.05 : Electrode : Electrode (in mm) (in mm) 1608 BLM18P A 600 BLM18K 0.4± ± ± ±0.15 T 1.6± ± ±0.2 : Electrode (in mm) : Electrode (in mm) A BLM18S 1608 BLM18E 1.6± ± ± ± ±0.15 T 0.4± ±0.2 : Electrode (in mm) : Electrode (in mm) 1608 BLM18G 2012 BLM21P 0.35± ± ± ± ± ± ± ±0.2 : Electrode (in mm) EIA CODE : 0805 : Electrode (in mm) 3216 BLM31P 4516 BLM41P 0.7± ± ± ± ± ± ± ±0.2 : Electrode (in mm) : Electrode (in mm) 43
48 LQH31C 3225 LQ32C 2.3± ± ± ± ± ± ± ± ± ± min. 0.7min. 0.7min. (in mm) 0.9± ± ±0.3 (in mm) 3225 LQH32C_ ± ±0.2 A 1.55±0.15 A 3.2± ±0.2 A : 2.8 max. 0.9± ± ±0.3 (in mm) 4532 LQH C 5750 LQH55D 3.6± ± ± ± ± ± ± ± ± min. 1.0min. 1.0min. (in mm) min. min. min. (in mm) 6363 LQH66S 6.3± ± ± ± min. 1.7 min. 1.3 min. (in mm) 44
49 5.8 LC NFE BNX BNX 3216 NFE31P 6816 NFE61P 0.7± ± ±0.2 (1) (2) (3) BNX 1.6± ± ±0.15 : Electrode (in mm) 12.1±0.2 (1) (2) 9.1±0.2 (3) BNX022 (4) 4.2±0.3 (2.45) 3.1± ± ± ± ±0.3 (1) (3) (4) (4) (2) 7.0± ± ±0.2 (3) (4) (1) (2) : Electrode 1.0± ± ±0.2 (4) (in mm) L1 L3 C2 (1) B CB (2) L2 C1 (3) PSG CG (4) (1)-(4): Terminal Number PSG: Power Supply Ground CG: Circuit Ground CB: Circuit+B 0.7± ± ±0.2 (1) (2) (3) 6.8± ± ±0.3 : Electrode (in mm) 45
50 IC 6-1 IC IC IC IC (PDN) IC IC V = I (6-1) Z P V (V) I (A) ZPPDN V IC ZP 46
51 (a) 6-3(b) 6.2 PDN 6-4
52 6-5 PDN IC 6-3 (a) 3V 0.5 1A 10ns 1s 6-6 2F 5F 10F ESL 10nH ESLPCB ESR 50m
53 time (µs) F 6-7 ESR ESL ESR ESL ESL ESL time (µs) ESL di/dt 10ns di/dt = A/s) F 1F MLCC ESL ESLPCB 2nH 49
54 ESR 10m time (µs) 6-9 1F 0.1F 1F 0.2s time (µs) 50
55 6.4 ESL ESL 6-10 ESL 10F ESL 0.2nHESR 50m ESL time (µs) LPowerDelay
56 time (µs) F 6-11 RLC 13) 4LPowerDelay C (6-2) 2 R C R ESR ESL C 6-12 (6-2) 40F 6-12 F IC LPowerDelay TPowerDelay(s) LPowerDelay RL L = R (6-3) PowerDelay T PowerDelay 52
57 IC IC ESL IC 7.1 IC 7-1 PDN 10F 2.2F 0.47F 7-1 IC IC BC A PDN PDN MHz ESL A PDN A PDN 53
58 7.2 IC IC MSL 7-3 Z PowerTerminal Z nal = Z cap + Z line PowerTermi (7-1) Z cap Z line Z cap via 54
59 Z line 7-3 L line Z cap ESL ESL cap IC Z PowerTerminal Z = Z + Z j 2π f ( ESL + L ) (7-2) PowerTerminal cap line Lline MSL l MSL 14) Lline L line 0.6 h 6 = 0.4l 10 (H) (7-3) w h MSL w l m (7-2) Lline ESL cap IC ESL cap via ESLPCB cap line 7.3 IC 7-3 IC Z T f TPCB l max 55
60 (7-2) Z PowerTerminal Z T f f T L line_max L Z ESL T line_max cap 2π f (7-4) T (7-3) Lline L line_max l max l = L line _ max 6 T PCB cap 6 max h w Z 2πf f PCB h w ESL (m) (7-5) 7-4 IC l max l max l max l max Z T 7-5 l max IC IC Z T (7-5) ESL cap l max 7-5 IC IC Z T IC IC IC IC IC 56
61 (7-5) 2f T ESL cap Z T l max ESL Z T ESL ESL cap ESL cap l max l max h w 7-6 l max LW ESL MLCC f TPCB IC 100MHz f T@PCB IC l max ESL ESL l max ESL l max PDN @100MHz 1 MLCC 2f T ESL cap Z T ESL cap ESL ESL cap MSL MSL 57
62 58
63 59
64 60
65 PDN IC PDN 1) PDN IC PDN PDN Power Integrity PI IC IC ) PDN IC 61
66 IC PDN IC (ZT) 8-3 PDN IC BGA PCB 62
67 PDN 8-4 1) Z T V ZT 8-6 f min C cap f max ESL total ESL total 63
68 ESL cap L line ESL cap ESL via log Z 1 Z = 2f C cap Z =2f ESL total Z T ESR total f min 1 = 2 π Z T C cap f max Z T = 2π ESL total log f 8-6 ZT ZT ESR total Z T ESR Z T 8-7 ESL total
69 log Z f min 2 1 = 2 π Z T C Cap 2 f max 1 = Z T 2 π ESL total 1 Z T 2 log f IC ESL 8-8 log Z Z T log f log Z log f Z T 65
70 8.4PCB 8-2 IC PCB PCB f T@PCB IC 10MHz100MHz PCB f T@PCB IC IC PCB ESR ESL ESR ESL 8-9 MLCC 2.2F ESR 10MHz MLCC MLCC ESL 8.6 IC PCB MLCC IC IC 66
71 8-10 2) 8-10 (a) 8-11 F 10000pF 1000pF 100pF F 8-10 (b) 8-12 via via 67
72 -10 ESL 8-13 MLCC ESL ESL MLCC IC MSL 68
73 ZT IC V Z T = (8-1) I VIC I IC 16) 17) Z T f T@PCB IC 100MHz LPower C bulk L C bulk (8-2) Z Power 2 T LPower L line 0.6 h 6 = 0.4l 10 (H) (7-3) w h MSL w l (8-3)L power L powerresponce L Powe Responce = Z t (8-3) T Power Responce t powerresponce 69
74 C bulk L Power 2 Z T 0.6 h 6 L line = 0.4l 10 w l Cboad Lbulk (8-2) L C boad (8-4) Z bulk 2 T Lbulk ESL IC
75 C boad L Z bulk 2 T 0.6 h 6 L bulk = 0.4l 10 w l IC l max f T@PCB Z T Z 2 T πf PCBESLcap 6 l max (m) (7-5) 0.6 h PCB w ESLcap ESL ESL via ESLPCB) 71
76 l l max Z 2 f T 6 max 0.4 T PCB cap f PCB ESL h w l max 8-19 ESLcap l max ESL l max
77 0.6 Z h 6 V T = L line = 0.4l 10 w I l L Power L bulk C bulk C 2 boad Z 2 T ESL 2 6 Z Z lmax 0.4 T PCB cap T T h f PCB w 8.8 PDN CPU m ESL
78 PDN DC-50MHz 5m 2m L PowerDelay 10nH L Power 36 LW ESL 330F MLCC 10F MLCC 100F LW 100F 100F 74
79 IC IC PI IC MLCC ESL GHz 75
80 1), ",", vol.12 No.3, May, ), "," pp ,, EMC, No.233 3) Mark Montrose,, " EMC - -,", ) Brian Young, "Digital Signal Integrity Modeling and Simulation with Interconnects and Packages," Prentice Hall PTR, ) Clayton R. Paul,, "EMC,", ), "," CQ, ) " DC,", TE13JT, ), " EMC,", ) ",", ) Larry D. Smith, "Frequency Domain Target Impedance Method for Bypass Capacitor Selection for Power Distribution Systems", pp , Power Distribution Network Design Methodologies, IEC, ), " EMC,", ), "," pp.52-57, EMC, 2007 No ), "," ) Stephan H. Hall, Garret W. Hall, James A. McCall, "High-speed Digital System Design; A Handbook of Interconnect Theory and Design Practices," Wiley-Inter Science ) Mikhail Popovich, Andrey V. Mezhiba, Eby G. Friedman, "Power Distribution Networks with On-chip Decoupling Capacitors," Springer, ) Madhavan Swaminathan, A. Ege Engin, "Power Integrity Modeling and Design for Semiconductor and Systems," Prentice Hall PTR, ),", vol.12 No.3, May,
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