MAX1420 DS rev1.J

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1 ; Rev 1; 5/4 EALUATION KIT AAILABLE Functional diagram appears at end of data sheet. µ PART TEMP RANGE PIN-PACKAGE CCM C to +7 C 48 TQFP ECM -4 C to +85 C 48 TQFP INP INN ADD ADD CML REFN REFP REFIN ADD PD OE D11 D ADD ADD DDD DGND D D1 48-TQFP D9 D8 D7 D6 D DD D DD DGND DGND D5 D4 D3 D2 Maxim Integrated Products 1

2 ABSOLUTE MAXIMUM RATINGS, D DD to to +4 D DD, to DGND to +4 DGND to to +.3 INP, INN, REFP, REFN, REFIN, CML,,...( -.3) to ( +.3) D D11, OE, PD...(DGND -.3) to (D DD +.3) Continuous Power Dissipation (T A = +7 C) 48-Pin TQFP (derate 21.7mW/ C above +7 C) mW Operating Temperature Ranges CCM... C to +7 C ECM...-4 C to +85 C Maximum Junction Temperature C Storage Temperature Range C to +15 C Lead Temperature (soldering, 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input voltage at -.5dBFS, internal reference, f = 62.5MHz (5% duty cycle); digital output load C L = 1pF, +25 C guaranteed by production test, <+25 C guaranteed by design and characterization. Typical values are at T A = +25 C.) DC ACCURACY PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution RES 12 Bits Differential Nonlinearity DNL TA = +25 C, no missing codes -1 1 TA = T MIN to T MAX ±.5 Integral Nonlinearity INL TA = T MIN to T MAX ±2 LSB Mid-scale Offset MSO %FSR Mid-scale Offset Temperature Coefficient Gain Error Gain Error Temperature Coefficient MSOTC 3 x 1-4 %/ C GE GETC DYNAMIC PERFORMANCE (f = 6MHz, 496-point FFT) Signal-to-Noise Ratio Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-Noise and Distortion Effective Number of Bits Two-Tone Intermodulation Distortion SNR SFDR THD SINAD ENOB IMD Internal reference (Note 1) -5 ±.1 5 %FSR E xter nal r efer ence ap p l i ed to RE FIN ( N ote 2) E xter nal r efer ence ap p li ed to RE FP, CML, and REFN (Note 3) External reference applied to REFP, CML, and REFN (Note 3) -5 ± f IN = 5MHz 67 f IN = 15MHz, T A =+25 C f IN = 5MHz 72 f IN = 15MHz, T A =+25 C f IN = 5MHz -7 LSB 1 x 16 %/ C f IN = 15MHz, T A =+25 C f IN = 5MHz 64.5 f IN = 15MHz, T A =+25 C f IN = 5MHz 1.4 f IN = 15MHz 1.2 f IN1 = MHz, f IN2 = MHz (Note 4) db dbc dbc db Bits -74 dbc 2

3 ELECTRICAL CHARACTERISTICS (continued) ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input voltage at -.5dBFS, internal reference, f = 62.5MHz (5% duty cycle); digital output load C L = 1pF, +25 C guaranteed by production test, <+25 C guaranteed by design and characterization. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Gain DG ±1 % Differential Phase DP ±.25 Degrees ANALOG INPUTS (INP, INN, CML) Input Resistance R IN Either input to ground 22 kω Input Capacitance C IN Either input to ground 4 pf Common-Mode Input Level (Note 5) Common-Mode Input oltage Range (Note 5) CML CMR ADD x.5 Differential Input Range IN INP - INN (Note 6) ± DIFF Small-Signal Bandwidth BW -3dB (Note 7) 4 MHz Large-Signal Bandwidth FPBW -3dB (Note 7) 15 MHz Overvoltage Recovery OR 1.5 x FS input 1 INTERNAL REFERENCE (REFIN bypassed with.22µf in parallel with 1nF) Common-Mode Reference oltage CML At CML CML ± 5% ADD _.5 Clock cycles Positive Reference oltage REFP At REFP CML Negative Reference oltage REFN At REFN CML Differential Reference oltage DIFF (Note 6) 1.24 ±5% Differential Reference Temperature Coefficient EXTERNAL REFERENCE ( REFIN = 2.48) REFTC ±1 ppm/ C REFIN Input Resistance R IN (Note 8) 5 kω REFIN Input Capacitance C IN 1 pf REFIN Reference Input oltage REFIN 2.48 ±1% Differential Reference oltage DIFF (Note 6) EXTERNAL REFERENCE ( REFIN =, reference voltage applied to REFP, REFN, and CML).92 x REFIN /2 REFIN/2 1.8 x REFIN /2 REFP, REFN, CML Input Current I IN -2 2 µa REFP, REFN, CML Input Capacitance C IN 15 pf 3

4 ELECTRICAL CHARACTERISTICS (continued) ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input voltage at -.5dBFS, internal reference, f = 62.5MHz (5% duty cycle); digital output load C L = 1pF, +25 C guaranteed by production test, <+25 C guaranteed by design and characterization. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Differential Reference oltage Range DIFF (Note 6) 1.24 ±1% CML Input oltage Range CML 1.65 ±1% REFP Input oltage Range REFP CML + DIFF /2 REFN Input oltage Range REFN CML - DIFF /2 DIGITAL INPUTS (,, PD, OE) Input Logic High IH.7 x DDD Input Logic Low IL.3 x DDD Input Current, ±33 PD -2 2 OE -2 2 Input Capacitance 1 pf DIGITAL OUTPUTS (D D11) Output Logic High OH IOH = 2µA DDD -.5 DDD Output Logic Low OL IOL = -2µA.5 Three-State Leakage -1 1 µa Three-State Capacitance 2 pf POWER REQUIREMENTS Analog Supply oltage ADD Digital Supply oltage DDD Analog Supply Current I ADD ma Analog Supply Current with Internal Reference in Shutdown REFIN = ma Analog Shutdown Current PD = D DD 1 2 µa Digital Supply Current I DDD 8 ma Digital Shutdown Current PD = DDD 2 µa Power Dissipation P DISS Analog power dissipation mw µa 4

5 ELECTRICAL CHARACTERISTICS (continued) ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input voltage at -.5dBFS, internal reference, f = 62.5MHz (5% duty cycle); digital output load C L = 1pF, +25 C guaranteed by production test, <+25 C guaranteed by design and characterization. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Power Dissipation In Shutdown PDISS PD = DDD 1 µw Power-Supply Rejection Ratio PSRR (Note 9) ±1 m/ TIMING CHARACTERISTICS Maximum Clock Frequency f 6 MHz Clock High tch Figure 6, clock period ns 8.33 ns Clock Low tcl Figure 6, clock period ns 8.33 ns Pipeline Delay (Latency) Figure 6 7 Clock cycles Aperture Delay tad Figure 1 2 ns Aperture Jitter taj Figure 1 2 ps Data Output Delay tod Figure ns Bus Enable Time tbe Figure 5 5 ns Bus Disable Time tbd Figure 5 5 ns Note 1: Internal reference, REFIN bypassed to with a combination of.22µf in parallel with 1nF capacitor. Note 2: External 2.48 reference applied to REFIN. Note 3: Internal reference disabled. REFIN =, REFP = 2.162, CML = 1.65, and REFN = Note 4: IMD is measured with respect to either of the fundamental tones. Note 5: Specifies the common-mode range of the differential input signal supplied to the. Note 6: DIFF = REFP - REFN. Note 7: Input bandwidth is measured at a -3dB level. Note 8: REFIN is internally biased to 2.48 through a 1kΩ resistor. Note 9: Measured as the ratio of the change in mid-scale offset voltage for a ±5% change in ADD, using the internal reference. ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input drive, A IN = -.5dBFS, f = 6.6MHz (5% duty cycle), digital output load C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) -2 FFT PLOT (8192-POINT DATA RECORD) f IN = MHz toc1-2 FFT PLOT (8192-POINT DATA RECORD) f IN = MHz toc2-2 FFT PLOT (8192-POINT DATA RECORD) f IN = MHz toc3 AMPLITUDE (db) HD2 HD3 AMPLITUDE (db) HD2 HD3 AMPLITUDE (db) HD3 HD ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) 5

6 ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input drive, A IN = -.5dBFS, f = 6.6MHz (5% duty cycle), digital output load C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) -2 TWO-TONE IMD PLOT (8192-POINT DATA RECORD) f IN1 = MHz f IN2 = MHz A IN1 = A IN2 = -6.5dB FS toc SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY toc SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY toc6 AMPLITUDE (db) IMD3 f IN1 IMD2 f IN2 IMD2 IMD3 SNR (db) SINAD (db) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY toc SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY toc SIGNAL-TO-NOISE RATIO vs. INPUT POWER (f IN = 15MHz) toc9 THD (dbc) SFDR (dbc) SNR (db) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT POWER (db FS) SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (f IN = 15MHz) toc TOTAL HARMONIC DISTORTION vs. INPUT POWER (f IN = 15MHz) toc SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (f IN = 15MHz) toc SINAD (db) 4 3 THD (dbc) -5 SFDR (dbc) ANALOG INPUT POWER (db FS) ANALOG INPUT POWER (db FS) ANALOG INPUT POWER (db FS) 6

7 ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input drive, A IN = -.5dBFS, f = 6.6MHz (5% duty cycle), digital output load C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) 7 68 SIGNAL-TO-NOISE RATIO vs. TEMPERATURE f IN = 15MHz toc SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE f IN = 15MHz toc TOTAL HARMONIC DISTORTION vs. TEMPERATURE f IN = 15MHz toc15 SNR (db) SINAD (db) THD (dbc) SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE f IN = 15MHz toc16 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE toc DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE toc18 SFDR (dbc) INL (LSB) INL (LSB) DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE REFIN = 2.48 toc OFFSET ERROR vs. TEMPERATURE toc ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY OLTAGE toc21 GAIN ERROR (%FSR) OFFSET ERROR (%FSR) IADD (ma) () 7

8 ( ADD = DDD = 3.3, = DGND =, IN = ±1.24, differential input drive, A IN = -.5dBFS, f = 6.6MHz (5% duty cycle), digital output load C L = 1pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) IADD (ma) ANALOG SUPPLY CURRENT vs. TEMPERATURE toc22 IDDD (ma) DIGITAL SUPPLY CURRENT vs. DIGITAL SUPPLY OLTAGE toc23 IDDD (ma) DIGITAL SUPPLY CURRENT vs. TEMPERATURE toc D DD () IADD (µa) REFIN () ANALOG POWER-DOWN CURRENT vs. ANALOG SUPPLY OLTAGE () INTERNAL REFERENCE OLTAGE vs. ANALOG SUPPLY OLTAGE () toc25 toc28 IDDD (µa) REFIN () DIGITAL POWER-DOWN CURRENT vs. DIGITAL SUPPLY OLTAGE D DD () INTERNAL REFERENCE OLTAGE vs. TEMPERATURE toc26 toc29 COUNTS SNR/SINAD, THD/SFDR (db, dbc) , 5, 4, 3, 2, 1, SNR/SINAD, THD/SFDR vs. CLOCK FREQUENCY SNR THD SINAD SFDR 45 f IN = 15MHz CLOCK FREQUENCY (MHz) OUTPUT NOISE HISTOGRAM (DC INPUT) N-6 N-5 N-4 N-3 N-2 N-1 N N+1 N+2N+3 N+4 N+5 N+6 DIGITAL OUTPUT NOISE toc27 toc3 8

9 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 2, 3, 1, 11, 14, 15, 2, 42, 47 µ µ µ 6 INP 7 INN , 31, 32 D DD 22, 29, 3 DGND D D D6 D11 39 OE 4 PD 43 REFIN 44 REFP 45 REFN 46 CML µ µ µ µ OE µ µ µ µ 9

10 IN FLASH ADC MDAC T/H DAC 2 BITS Σ x2 OUT TO NEXT STAGE S4a S4c C2a INTERNAL BIAS S2a S1 C1a OTA CML S5a S3a OUT IN STAGE 1 STAGE 2 STAGE 12 S4b C2b C1b OUT DIGITAL CORRECTION LOGIC S3b 12 S2b S5b D11 D INTERNAL BIAS CML 1

11 R R 2 R 4 MAX4284 5Ω 2.22µF 5Ω.22µF R R 5Ω 1nF 1nF CML REFP R MAX µF 1nF REFN 4 R REFIN R.5 µ µ 1 SNRdB = 2 log 1 2π fin taj 11

12 INP INN A DD 1kΩ 1kΩ 1kΩ 1kΩ D11 D OE OE OE ADC DIFFERENTIAL INPUT OLTAGE* REF 247/248 REF 246/248 DIFFERENTIAL INPUT +FULL SCALE - 1LSB +FULL SCALE - 2LSB OFFSET BINARY REF 1/ LSB 1 1 Bipolar Zero 1 - REF 1/248-1 LSB REF 246/248 -FULL SCALE + 1 LSB 1 - REF 247/248 -FULL SCALE * REF = REFP - REFN OE OUTPUT DATA D11 D HIGH-Z tbe ALID DATA HIGH-Z t BD 12

13 ANALOG INPUT N N + 1 N CLOCK-CYCLE LATENCY N + 3 N + 4 N + 5 N + 6 t OD t CH tcl DATA OUTPUT N - 7 N - 6 N - 5 N - 4 N - 3 N - 2 N - 1 N 5.1µF LOWPASS FILTER 3Ω.1µF MAX418 R ISO 5Ω *C IN 22pF INP -5.1µF 3Ω 6Ω 6Ω.1µF 44pF* CML 5.1µF.22µF 1nF 5 INPUT MAX µF.1µF 3Ω 3Ω 6Ω MAX418.1µF LOWPASS FILTER R ISO 5Ω *C IN 22pF INN -5.1µF 3Ω 3Ω 6Ω *TWO C IN (22pF) CAPS MAY BE REPLACED BY ONE 44pF CAP, TO IMPROE PERFORMANCE. 13

14 .1µF 1 T1 6 IN N.C MINICIRCUITS T1 1T KK81.22µF 4 25Ω 25Ω 22pF 1nF 22pF * * 44pF * INP CML INN *REPLACE BOTH 22pF CAPS WITH 44pF BETWEEN INP AND INN TO IMPROE DYNAMIC PERFORMANCE. µ µ µ 14

15 IN MAX418 1Ω 1Ω.1µF 1kΩ.22µF R ISO 5Ω C IN 22pF 1nF R ISO 5Ω C IN 22pF INP CML INN ANALOG INPUT SAMPLED DATA (T/H) T/H t AD TRACK HOLD t AJ TRACK SNR MAX = (6.2 x N )dB SINAD ENOB =

16 THDdB = 2 log INP INN T/H INTERFACE PIPELINE ADC OUTPUT DRIERS D11 D PD BANDGAP REFERENCE REF SYSTEM + BIAS D DD DGND REFIN REFP CML REFN OE 16

17 japan.maxim-ic.com/packages 32L/48L,TQFP.EPS PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm E 1 2 PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm E Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products, Inc. All rights reserved. is a registered trademark of Maxim Integrated Products.

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