LTC ビット、100ksps、サンプリングADC

Transcription

1 BUSY ±V INPUT Ω.k V IN CAP REF V k BUFFER k AGND 8 7 V DIG V ANA k k REFERENCE AGND 6-BIT SAMPLING ADC DGND CONTROL LOGIC AND TIMING D TO D BUSY CS R/C BYTE 6 TA 6 TO TO 6 µf.µf DIGITAL CONTROL SIGNALS 6-BIT OR BYTE PARALLEL BUS INL (LSBs) CODE 6 TA

2 V IN AGND REF CAP AGND D (MSB) 6 D 7 D 8 D 9 D D D9 D8 DGND N PACKAGE 8-LEAD PDIP TOP VIEW G PACKAGE 8-LEAD PLASTIC SSOP 8 V DIG 7 V ANA 6 BUSY CS R/C BYTE D D D 9 D 8 D 7 D 6 D6 D7 SW PACKAGE 8-LEAD PLASTIC SO WIDE T JMAX = C, θ JA = 9 C/W (G) T JMAX = C, θ JA = C/W (N) T JMAX = C, θ JA = C/W (SW) ORDER PART NUMBER ACG ACN ACSW AIG AIN AISW CG CN CSW IG IN ISW A PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS Resolution 6 6 Bits No Missing Codes 6 Bits Transition Noise.. LSB Integral Linearity Error (Note 7) ± ± LSB Bipolar Zero Error Ext. Reference =.V (Note 8) ± ± mv Bipolar Zero Error Drift ± ± ppm/ C Full-Scale Error Drift ±7 ± ppm/ C Full-Scale Error Ext. Reference =.V (Notes, ) ±. ±. % Full-Scale Error Drift Ext. Reference =.V ± ± ppm/ C Power Supply Sensitivity V ANA = V DIG = V DD V DD = V ±% (Note 9) ±8 ±8 LSB

3 /A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (Note 9).7V V ANA.V,.7V V DIG.V ± V I IN Analog Input Leakage Current CS = High ± µa C IN Analog Input Capacitance pf R IN Analog Input Impedance kω /A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS S/(N D) Signal-to-(Noise Distortion) Ratio khz Input Signal (Note ) 87. db khz Input Signal 87 db khz, 6dB Input Signal db THD Total Harmonic Distortion khz Input Signal, First Harmonics db khz Input Signal, First Harmonics 9 db Peak Harmonic or Spurious Noise khz Input Signal db khz Input Signal 9 db Full-Power Bandwidth (Note ) 7 khz Aperture Delay ns Aperture Jitter Sufficient to Meet AC Specs Transient Response Full-Scale Step (Note 9) µs Overvoltage Recovery (Note 6) ns /A PARAMETER CONDITIONS MIN TYP MAX UNITS V REF Output Voltage I OUT =.7.. V V REF Output Tempco I OUT = ± ppm/ C Internal Reference Source Current µa External Reference Voltage for Specified Linearity (Notes 9, )...7 V External Reference Current Drain Ext. Reference =.V (Note 9) µa CAP Output Voltage I OUT =. V /A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Level Input Voltage V DD =.V. V V IL Low Level Input Voltage V DD =.7V.8 V I IN Digital Input Current V IN = V to V DD ± µa C IN Digital Input Capacitance pf V OH High Level Output Voltage V DD =.7V I O = µa. V I O = µa. V V OL Low Level Output Voltage V DD =.7V I O = 6µA. V I O =.6mA.. V

4 /A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I OZ Hi-Z Output Leakage D to D V OUT = V to V DD, CS High ± µa C OZ Hi-Z Output Capacitance D to D CS High (Note 9) pf I SOURCE Output Source Current V OUT = V ma I SINK Output Sink Current V OUT = V DD ma /A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SAMPLE(MAX) Maximum Sampling Frequency khz t CONV Conversion Time 8 µs t ACQ Acquisition Time µs t Convert Pulse Width (Note ) ns t Data Valid Delay After R/C (Note 9) 8 µs t BUSY Delay from R/C C L = pf 6 ns t BUSY Low 8 µs t BUSY Delay After End of Conversion ns t 6 Aperture Delay ns t 7 Bus Relinquish Time 8 ns t 8 BUSY Delay After Data Valid ns t 9 Previous Data Valid After R/C 7. µs t R/C to CS Setup Time (Notes 9, ) ns t Time Between Conversions µs t Bus Access and Byte Delay (Notes 9, ) 8 ns /A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DD Positive Supply Voltage (Notes 9, ).7. V I DD Positive Supply Current 6 ma P DIS Power Dissipation 8 mw

5 CS C C µ C SUPPLY CURRENT (ma) f SAMPLE = khz.7... SUPPLY VOLTAGE (V) 6 TPC POSITIVE SUPPLY CURRENT (ma)..... f SAMPLE = khz TEMPERATURE ( C) 7 6 TPC CHANGE IN CAP VOLTAGE (V) LOAD CURRENT (ma) 6 TPC.. INL (LSBs) DNL (LSBs) POWER SUPPLY FEEDTHROUGH (db) CODE CODE 6 7 k k k RIPPLE FREQUENCY (Hz) M 6 TPC 6 TPC 6 TPC6

6 MAGNITUDE (db) f SAMPLE = khz f IN = khz SINAD = 87.dB THD =.7dB FREQUENCY (khz) 6 TPC7 9 7 SINAD (db) TOTAL HARMONIC DISTORTION (db) INPUT FREQUENCY (khz) INPUT FREQUENCY (khz) 6 TPC8 6 TPC9 µ µ 6 CS C CS C

7 C CS C CS C CSC C CS C CS BUSY BUSY BUSY CS C µ µ V V k k DBN DBN DBN DBN k C L C L k pf pf TC TC A. HI-Z TO V OH AND V OL TO V OH B. HI-Z TO V OL AND V OH TO V OL A. V OH TO HI-Z B. V OL TO HI-Z V IN k C SAMPLE k k C SAMPLE V ANA REF k.v REF ZEROING SWITCHES V DIG REF BUF 6-BIT CAPACITIVE DAC COMP CAP (.V) AGND AGND DGND INTERNAL CLOCK SUCCESSIVE APPROXIMATION REGISTER CONTROL LOGIC 6 OUTPUT LATCHES D D CS R/C BYTE BUSY BD 7

8 CS C µ V IN R IN R IN SAMPLE HOLD C SAMPLE C DAC V DAC DAC SAMPLE SI COMPARATOR S A R 6-BIT LATCH 6 F A IN Ω pf.k V IN CAP 6 F µ 8

9 ±V INPUT Ω %.k % V IN AGND REF CAP AGND 6 F REF (.V) CAP (.V) S S k V ANA BANDGAP REFERENCE INTERNAL CAPACITOR DAC ±V INPUT Ω %.k % V R k R k 76k V IN AGND REF CAP AGND 6 F 6 F µ OUTPUT CODE FS/ BIPOLAR ZERO V LSB LSB INPUT VOLTAGE (V) FS = V LSB = FS/66 FS/ LSB 6 F6 9

10 COUNT CODE 6 F7 µ µ CS C CS C BUSY C CSC BUSY C C C µ CS CS C CS CS BUSY BUSY CS R/C t t t t BUSY t t 6 t MODE ACQUIRE CONVERT ACQUIRE CONVERT t CONV t ACQ t 9 DATA MODE PREVIOUS DATA VALID PREVIOUS HI-Z NOT VALID DATA HI-Z DATA VALID VALID DATA VALID t 7 t 8 6 F8 CS

11 t t t t R/C t t CS t t BUSY t 6 MODE ACQUIRE CONVERT ACQUIRE t CONV DATA BUS HI-Z DATA VALID HI-Z t t 7 6 F9 CS t t R/C CS BYTE PINS 6 TO HI-Z HIGH BYTE LOW BYTE HI-Z t t t 7 PINS TO HI-Z LOW BYTE HIGH BYTE HI-Z 6 F CS MAGNITUDE (db) f SAMPLE = khz f IN = khz SINAD = 87.dB THD =.7dB FREQUENCY (khz) 6 F

12 µ C CS THD log V V V... V = V N

13 ANALOG GROUND PLANE DIGITAL GROUND PLANE ANALOG GROUND PLANE

14 VIN 7V TO V E GND E VIN VIN U LT D6 GND MBR V KK V CC V DD C6 µf V DIGITAL I.C. BYPASSING R6 C9.µF C.µF C.µF V CC C.µF C.µF C.µF C µf J AIN VKK NC NC INPUT HEATER TEMP OUT GND TRIM U9 LT JP EXT VREF INT C7 µf R8 Ω % C C6 pf C.µF C R9.k % C.µF U U 7HC7 6 D D 9 VIN D D Q D 7 D D Q 8 AGND D D D Q 7 8 D D D Q 6 REF D D 6 D Q 9 D D 7 CAP D D Q D9 8 D D6 Q6 AGND D D8 9 D7 Q7 D DGND D OC CLK D9 BYTE D9 EXT_CLK J NA R7 U8 MHz, OSC GND 9 OUT VCC UD 7HC CLR LOAD CLK ENT R, k A B U6A 7HC CLK CEXT RCEXT Q Q U7 7HC6 ENP D C B A 8 UE 7HC RCO QD QC QB QA EXT CLK INT JP VCC REVERSE BYTE NORNAL VCC JP V CC CS VCC JP VKK C7 µf C8.µF R/C CS BUSY V ANA VDIG D8 D7 D6 D D D D D D D8 D7 D6 D D D D D D UB 7HC R K D D D D D D D6 D7 C PF D D D D D D D6 D7 OC U 7HC7 CLK UC 7HC 6 9 Q Q 8 Q 7 Q 6 Q Q Q6 Q7 GND UA 7HC R,.k D R,.k D R,.k D R,.k D R,.k D R,.k D R9,.k D9 R8,.k D R7,.k D7 R6,.k D6 R,.k D R,.k D R,.k D R,.k D R,.k D R,.k D D D D D D D D9 D8 D7 D6 D D D D D D D CLK GND GND JP LED ENABLE 6_7d.eps

15 .97.7* (.7.) ( ) ** (..8) (.7.99) 8..9 (..)..7 (..9) * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.mm) PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.6 (.6) BSC.. (..8)..8 (..) G8 SSOP 69.7* (.789) MAX ±.* (6.77 ±.8) (7.6 8.). ±. (. ±.7)..6 (..6).9. (.9.8) ( ). (.8) MIN. (.7) MIN *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED. INCH (.mm). (.7) MIN. ±. (. ±.).8 ±. (.7 ±.76).6 (.6) TYP N8 97

16 .697.7* ( ) NOTE.9.9 (.7.6).9.99** ( ) (..77).9. (.6.6).7. (.9.) 8 TYP.9. (.9.) NOTE.6. (.6.7). (.7) TYP..9 (.6.8) TYP NOTE:. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED.6" (.mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED." (.mm) PER SIDE.. (..) S8 (WIDE) K PRINTED IN JAPAN LINEAR TECHNOLOGY CORPORATION 997