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1 Studies on Interpolated Timing Recovery and External Clock Synchronization for Magnetic Recording Channels

2

3 PRML PR(1,0,-1) PRML Viterbi PRML Viterbi Viterbi PR(1,0,-1) PRML Zoned Bit Recording I

4 PRML ITR ITR PRML PRML PLL PLL II

5 Pre-Embossed Rigid Magnetic Disk PERM MR/Inductive DC

6 Viterbi PLL SSML AV

7 5 9.3 HDD Head-Disk Assembly

8 6 2.1 Fundamental process of the binary saturation magnetic recording Frequency spectrum of the di-pulse and PR(1,0,-1) target spectrum A channel model of the binary saturation magnetic recording Principles of classic data channels Block diagram of the PR(1,-1) channel Readback process of the PR(1,0,-1) channel Schematic block diagram of the PR(1,0,-1) channel Block diagram of the entire PRML channel electronics Generation of isolated PR(1,0,-1) response Frequency transfer characteristics of the equalizer for PR(1,0,- 1) channel. Simulation results Noise Figure of the equalizer as a function of the normalized linear density Eye pattern of the PR(1,0,-1) channel signal equalized by the 8-pole 4-zero analogfilter and cosine equalizer Trellis diagram and state transition diagram of the PR(1,-1) channel Example of the path selection error in the Viterbi decoding for PR(1,-1) channel All error patterns in the Viterbi decoder for the PR(1,-1) channel Bit error rate of the Viterbi decoder for the PR(1,-1) channel Timingoffset dependency of the bit error rate in a PR(1,0,-1) channel with a 3-level threshold detector. SNR of an input isolated pulse: S 0 p /N rms =20 db, Equalizer: 1st order LPF with f c = 1.0[1/T b ] and 5-tap FIR whose coefficients are determined by least squared error minimization method

9 Timingoffset dependency of the bit error rate in a PR(1,0,- 1) channel with a Viterbi decoder. SNR of an input isolated pulse: S 0 p /N rms =20 db, Equalizer: 1st order LPF with f c =1.0[1/T b ] and 5-tap FIR whose coefficients are determined by least squared error minimization method Disk storage system and OSI (Open System Interconnection) reference model Flame structure of a data sector Example of the bit synchronization loop and the signal level control loop Principle of Zoned Bit Recording Block diagram of the new PRML read channel which operates with a unique fixed clock Eye-pattern of the equalized PR(1,0,-1) channel signal Data points and signal samples in the PR(1,0,-1) channel output waveform Signal flow diagram of the Decision-directed digital phaselocked loop (D3PLL) Principle of the instantaneous phase detection based on linear interpolation Input-output characteristics θk d(θ k) of the phase detector and the deterministic phase detection error θ e = θ k θk d Maximum deterministic phase detection error as a function of the normalized linear density NLD Correlation coefficient r 01 between two adjacent noise samples S k and S k Noise to jitter conversion gain G of the phase detector Bit-by-bit ternary data detection in the D3PLL Closed loop transfer gain characteristics of the 1st order DPLL with the coefficient α. The loop samplingfrequency is mt s Signal flow graph of the 1st order DPLL with the truncation error at the coefficient multiplier Principle of the data point signal interpolation Signal flow diagram of the interpolator Simulation results on rms interpolation error vs. filter cut-off frequency Quantization of tap coefficients vs. rms interpolation error Configuration of the experimental PRML recording system with the new bit-synchronizer

10 Distribution of data-asynchronous signal samples. Experimental results Distribution of synchronized data samples Ŝ0 k. Experimental results Phase data ˆθ k of the D3PLL. Experimental results Experimental bit error rate for 6T preamble pattern as a function of channel bit rate deviation Experimental bit error rate for random data pattern as a function of channel bit rate deviation Experimental bit error rate performance as a function of C/N Principle of external clock generation and channel synchronization Schematic illustration of the servo pattern on a disk Block diagram of a recording channel with the servo-derived clockingscheme Readback signal from a servo area and the mode switching signal Definition of phase An example of measured clock mark intervals. The distribution of the interval has a standard deviation of about 1.5 ns, when the eccentricity component is removed by a high-pass filter with a cut-off frequency of 180 Hz Comparison of a measured clock mark pulse and a Lorentzian pulse based on the least squared error criterion. The RMS fittingerror is Schematic block diagram of a phase detector based on peak detection Block diagram of a PLL for servo-derived clock generation Simulation results of the bit clock jitter as a function of the PLL loop noise bandwidth Bit clock jitter as a function of the clock mark frequency (samplingfrequency). One-sided loop noise bandwidth is optimized for each f L Noise jitter dependency of the bit clock jitter components with optimized PLL one-sided loop noise bandwidth Simulation results of the bit clock jitter as a function of an input thermal noise jitter Bit clock jitter caused by eccentricity as a function of PLL gain variation

11 Measured bit clock jitter at a writingmoment alonga track Bit clock jitter measured on a spinstand with an air-bearing Schematic illustration of pattern on the PERM disk Electron microscope picture of the servo pattern on the PERM disk Cross sectional view of the MR/Inductive head Off-track profile Block diagram of the experimental recording system Saturation and overwrite characteristics Readback signal waveform Roll-off characteristics Transition density vs. noise at the head amplifier output Isolated pulse waveform of the readback signal Eye pattern Bit error rate as a function of the linear recordingdensity Model of phase estimation on an isolated readback pulse Model of phase estimation on a di-pulse readback pulse Schematic block diagram of the discrete time ML phase estimator (DMLPE) Schematic block diagram of the continuous time ML phase estimtor (CMLPE) Input-output operation curve f Ch (ˆθ) of CMLPE on an isolated pulse PW 50 dependency of the one-shot phase estimation error of CMLPE on an isolated pulse Input-output operation curve f Cd (ˆθ) of CMLPE on a dipulse. The mark length T m is PW 50. Input-output curve on a di-pulse is steeper than that on an isolated pulse Clock mark length dependency of the one-shot phase estimation error of CMLPE on a di-pulse. The error is minimum at T m = PW One-shot phase estimation error of DMLPE on an isolated pulse as a function of the samplinginterval. A short interval T s is required for a small PW 50 of the observed Lorentzian pulse One-shot phase estimation error of DMLPE as a function of the order. Calculation results

12 One-shot phase estimation error of DMLPE as a function of PW 50. Calculation results. For a di-pulse, the mark length is T m = PW S/N dependency of the clock jitter of the DPLL usingdmlpe on a di-pulse. Experimental results and calculation results Waveform of a reproduced servo signal in the data reading mode Waveform of a reproduced servo signal in the data writing mode Proposed DC-free coefficients compared with the original DMLPE coefficients. The order of DMLPE is Proposed DC-free coefficients compared with the original DMLPE coefficients. The order of DMLPE is Synthesized readback signal from a clock mark used in the performance simulation Performance of the DC-free coefficients to remove the effect of DC offset Performance of the DC-free coefficients to remove the base line variation of the exponentially decayingreadback signals Definition of the linear phase detection range in the phase comparator based on least-squared error method (DLSPC) Phase comparison curve obtained by DLSPC Examples of the wide linear phase detection range in a DLSPC Linear range and phase detection error as a function of the order of DLSPC Principle of the ML head position estimator ML position estimation gain G as a function of the order of estimation ML position estimation gain as a function of the PW 50 of coefficient vector. Simulation results Dependency of the position estimation gain on the timing offset of servo clock. Simulation results Block diagram of the coherent ML position estimator using time sharingtechnique Digital position and phase estimation by time-sharing a multiplier and accumulator Measurement results of the position S/N as a function of the input signal S/N

13 Schematic diagram of the sector servo and the synchronous servo formats Block diagram of the synchronous servo with ML detectors Example of the conventional track address recordingmethods Track address recordingmethod in the SSML scheme combining the Gray-coded magnetization and Viterbi decoding Clock jitter dependence of the Viterbi track address decoder Track address error rate as a function of the head position Track address discrimination characteristics. Comparison between the modified Gray code with level detection and the Gray-coded magnetization with Viterbi decoding Schematic block diagram of the ML head position detector Reduction of the head position detection gain due to the servo clock offset Maximum allowable clock jitter as a function of the S/N of the Lorentzian pulse that forms the di-pulse. Simulation results Schematic block diagram of the servo PLL with the digital ML phase estimator Plot of the jitter as a function of the natural frequency and dampingfactor of the PLL Servo clock jitter simulation results as a function of the servo loop samplingrate Relationship between major design parameters and performance of SSML scheme Data recordingcapacity as a function of the write-to-read switchingtime. Simulation results A comparison of capacity between the sector servo format and the synchronous servo format. Simulation results Open loop transfer characteristics of the trackingservo system Velocity profile, measured velocity and the lower 8 bit of track address in the experimental drive. Digital data are converted to analogsignals for measurements Concept of the 2 spin-speed AV/IT HDD Average continuous user data rate as a function of the disk rotational frequency Synchronous servo format Trackingservo system Block diagram of the prototype drive

14 Bode diagram of the open-loop tracking servo systems in the slow spin-speed and fast spin-speed drives Power spectrum of the position error signal Sensitivity functions of the closed-loop trackingservo systems Distribution of the track jump time in the slow spin-speed drive Error rate of the fast drive when readingthe disk cartridge written by the slow drive

15 Various applications of the external clockingscheme Characteristics of jitter sources Head and Disk Parameters Parameters of the head and medium Spin-speed related design issues Specification of the prototype drives Performance of the servo system

16

17 1 1.1 Hard Disk Drive, HDD PRML Partial-Response Maximum-Likelihood 1 15

18 16 1 LSI Large Scale Integrated circuit Interpolated TimingRecovery, ITR LSI ITR ITR ITR

19 I II 2 I 3 PRML HDD II PERM (Pre-Embossed Rigid Magnetic) HDD 10 I II

20

21 2 1 PRML Partial-Response Maximum-Likelihood 2.1 HDD VTR II PRML Partial-Response Maximum-Likelihood 1960 PR [2] [3] [5] ML Viterbi [4] 1971 [6] IC , 10, ( ), White Series No. 161 pp , May 31,

22 20 2 [7] PRML Viterbi HDD [7] [8] 2.2 B-H T b 2 b k 1.0 w(t) +1 if b k =1 w(t) = (2.1) 1 if b k =0 w(t) Π(t) b k w(t) = + k= (2b k 1)Π(t kt b ) (2.2) 1 if 0 t<t b Π(t) = 0 if t<0ort b t (2.3) 2.1 2Π(t) 1 d(t)

23 2 21 {b k } s(t) d(t) s(t) = k= 2b k 1 d(t kt b ) (2.4) 2 2 v x = vt vt b 2 [1] d δ a g a + d δ 1 h x (x) { } 1 x + g/2 x g/2 h x (x) A tan tan 1 (2.5) a + d a + d A PW % ( g ) 2 PW 50 2 (a + d) 2 + (2.6) 2 (2.5) a + d δ g Lorentz h(0) = 1.0 Lorentz h(t) h(t) = ( 1+ 1 t PW 50/2 ) 2 (2.7) Lorentz HDD Magneto-Resistive head, MR head d(t) =h(t) h(t T b ) d(t) D(f) = πpw 50 {1 exp( j2πft b )} exp( πpw 50 f ) (2.8) DC 2

24 22 2 Rec. data { b k } Rec. current w(t) t Magnetization +1 Di-pulse d(t) 0 Lorentzian pulse h(t) 0 d(t) T b t -1 Lorentzian pulse h(t-t b) 2.1: Fundamental process of the binary saturation magnetic recording. Power Spectrum Density, PSD N 0 n(t) {b k } z(t) z(t) =s(t)+n(t) = k= 2b k 1 d(t kt b )+n(t) (2.9) 2 MR [9][10] Lorentz {b k } (2.2)

25 Amplitude Spectrum Di-pulse spectrum D( f) of NLD = 2.5 Equalization target for PRS(1,0,-1) D eq ( f) Normalized frequency: [1/ bt ] : Frequency spectrum of the di-pulse and PR(1,0,-1) target spectrum. Linear filter Readback signal D ( f ) Binary write data s ( t ) z ( t ) = s ( t ) + n ( t) b k 0 + f n ( t ) Additive White Gaussian Noise 2.3: A channel model of the binary saturation magnetic recording. Inter-Symbol Interference, ISI {â k } 2 a k NRZI Non-Returned-to-Zero-Inverse 2 b k NRZI a k =1 a k =0 k 1 z(t) Viterbi 3 {a k } NRZI {b k }

26 24 2 Integration detection Differentiation detection Amplitude level detection Information data { a k } Write data { b k } Write current w ( t ) Readback signal z ( t ) Processed signal Detected data { ^ } a k : Principles of classic data channels. Source mod2 Pre-coder Recording PR(1,-1) channel Ternary Detected Data Data + Data Data mod 2 [ ] a k b k - c a^ D D k k NRZI Encoding 2.5: Block diagram of the PR(1,-1) channel. +1/2 1/2 2 3 ĉ k { 1, 0, +1} ĉ k 2 â k 3 S/N PRML PR

27 PRML PR 2.5 PR(1,-1) {a k } {b k } NRZI b k =[a k + b k 1 ] mod2 mod2 2 {b k } c k = b k b k 1 PR(1,-1) 3 {c k } 3 ĉ k 0, 0, 0, +1, 1, 0, 0, 0 â k =[ĉ k ] mod2 â k PR D N {a k } D A(D) = N 1 k=0 a k D k (2.10) B(D)/A(D) =1/[1 + D] mod2 PR(1,-1) C(D) =(1 D)B(D) PR(1-D) [1 D] mod2 =[1+D] mod2 (2.11) 1 Â(D) = [(1 D) A(D)] mod2 = A(D) (2.11) (1 + D) mod2 2 mod2 PR PR PR(1,0,-1) PR(1,0,-1) 3 0, 0, 0, +1, 0, 1, 0, 0, PR(1,0,-1)

28 26 2 { ak } { b k } w(t) t s(t) t 10 { c^k } { a^ k } : Readback process of the PR(1,0,-1) channel. 2.7(a) 2 {b k } 3 3 {ĉ k } mod2 {â k } PR(1,0,-1) C(D) =(1 D 2 )B(D) Â(D) = [(1 D 2 1 ) (1 + D 2 A(D)] mod2 = A(D) (2.12) ) mod2 (1 D 2 ) (b) {b k } PR(1,-1) PR(1,0,-1) Interleaved-NRZI PR(1,0,-1) 2.2 PR(1,0,-1)

29 2 27 Source Recording mod2 Pre coder PR(1,0, 1) channel Data Data + Ternary Data mod 2 [ ] a b k k c k a^ D D D D k Detected Data Clock rate = 1/T b (a) Straight forward expression of the PR(1,0, 1) channel model. even k PR(1, 1) channel + mod 2 [ ] Source Data a k mod2 Pre coder D D b k D PR(1, 1) channel + mod 2 [ ] Detected Data a^ k Clock rate = 1/T b odd k D Clock rate = 1/2T b (b) Parallel expression of the PR(1,0, 1) channel model. 2.7: Schematic block diagram of the PR(1,0,-1) channel. 1/2T b Null 2 3 S/N PRML PR(1,0,-1) Viterbi PRML 30 % [11] PRML 2.8 {a k } {b k } Write Precompensation AGC Automatic Gain Control A/D Viterbi A/D Viterbi

30 28 2 Head Magnetic disk Read amp. Write amp. z(t) Analog equalizer A/D Write Precoder pre comp. { b k } { a k } Digital equalizer Viterbi decoder { } a^k Channel decoder Channel encoder User data 2.8: Block diagram of the entire PRML channel electronics. Phase-Locked Loop, PLL PR(1,0,-1) PR(1,0,-1) PR(1,0,-1) nt b d eq (t) d eq (0) = 1 d eq (T b ) = 0 d eq (2T b ) = 1 d eq (nt b ) = 0 if n =, 2, 1, 3, 4, 5, (2.13) 2 1 1T b (1 + D) 2 (1 + D) 1T b (1 D) X(f) (2.14) G nyq (f) = T b + m= X(2π(f m T b )) (2.14)

31 2 29 Signal amplitude [a.u.] Raised cosine pulse (1+D) equalized pulse 2 (1-D ) equalized pulse Roll-off = Normalized time [ T b ] : Generation of isolated PR(1,0,-1) response. 1 D PR(1,0,-1) 1+D (2.7) Lorentz h(t) (2.14) (2.15) PR(1,0,-1) G eq (f) = G nyq (f)(1 + D) D=e j2πft b = πpw T b cos(πft b )e jπft b + m= exp ( πpw 50 f m T b ) (2.15) 2.10 PR(1,0,-1) (2.15) PR(1,0,-1) Noise Figure NLD = PW 50 /T b 2.11 Noise Figure PW 50 1/2T b PR(1,0,-1) (1 + D) Null NLD 2 PR(1,-1) 2dB PR(1,0,-1) G eq (f)

32 Transfer gain [a. u.] Ideal EQ 7pole 2zero LPF + Cos EQ 8pole 4zero LPF + Cos EQ Normalized frequency [1/ T b ] 2.10: Frequency transfer characteristics of the equalizer for PR(1,0,-1) channel. Simulation results. z =[z(kt b ),,z((k i)t b ),,z((k N +1)T b )] T v =[v 0,,v i,,v N 1 ] T z eq (kt b ) z eq (kt b )=v T z = N 1 i=0 v i z((k i)t b ) (2.16) N Lorentz PRML LMS Least Mean Squared 7

33 Noise Figure: NF [db] PR(1,-1) (Nyquist EQ only) PR(1,0,-1) (Nyquist EQ & (1+D)) Normalized Linear Density : NLD : Noise Figure of the equalizer as a function of the normalized linear density. 3 G lpf (s) = K 1q 1 s 2 + q2 2 (2.17) 7 p m s m m=0 7 2 LPF Low-Pass Filter 2 f =1/4T b K 1 G cos (f) G cos (f) =1+2K 2 cos(2πft b ) (2.18) K 2 1/2T b

34 : Eye pattern of the PR(1,0,-1) channel signal equalized by the 8-pole 4-zero analogfilter and cosine equalizer. 2.6 PRML Viterbi PRML Viterbi PR(1,0,-1) PRML Viterbi PR(1,0,-1) 2 PR(1,-1) PR(1,-1) Viterbi 1/2 PR(1,0,-1) 2 Viterbi [6] PR(1,-1) Viterbi b k { 1, +1} b k b k PR(1,-1) c k c k = c k =+2 c k = 2 {z k }

35 2 33 {b k } {c k } z =[z 1,z 2,,z N ] 2 3 c =[c 1,c 2,,c N ] N ĉ = Argmin c z c 2 = Argmin c (z k c k ) 2 (2.19) Argmin x f(x) f(x) x 3 c k = b k b k 1 (2.19) 1 z(t) (2.19) (2.20) 2 b { N } N ˆb = Argmin b zk 2 4 B(b k 1,b k ) (2.20) k=1 k=1 B(b k 1,b k ) k 1 k B(b k 1,b k ) 1 2 z k(b k b k 1 ) 1 4 (b k b k 1 ) 2 (2.21) N ˆb = Argmax b N k=1 k=1 B(b k 1,b k ) (2.22) Viterbi k L k L k = L k 1 + B(b k 1,b k ) (2.23) +1 1 k 1 L k 1 k 1 2 b k 1 =+1, 1 k 2 4 (2.21) 4 B(+1, +1) = 0 B( 1, 1) = 0 B(+1, 1) = z k 1 B( 1, +1) = z k 1 (2.24)

36 /0 b k = L k 2 L k 1 L k L k+1 B (+1,+1) B (+1,+1) B (+1,+1) +1/+2 1/ 2 b k = 1 L k 2 (+1, 1) ( 1,+1) B ( 1, 1) L k 1 (+1, 1) ( 1,+1) B ( 1, 1) L k (+1, 1) ( 1,+1) B ( 1, 1) L k+1 b k /c k 1/0 2.13: Trellis diagram and state transition diagram of the PR(1,-1) channel. k L + k L k 2 L + k = max[l + k 1 + B(+1, +1),L k 1 + B( 1, +1)] = max[l + k 1,L k 1 + z k 1] (2.25) L k = max[l + k 1 + B(+1, 1),L k 1 + B( 1, 1)] = max[l + k 1 z k 1,L k 1 ] (2.26) Viterbi Viterbi 2.14 k = B( 1, 1) + B( 1, 1) + B( 1, +1) <B( 1, +1) + B(+1, +1) + B(+1, +1) (2.27) (2.24) n 2 n 4 > 2 a k 2

37 2 35 a k =0 0 l Viterbi l 2 l 2.15(a) (b) 8 l P err =8/2 l (a) 4 n l n 2 > (b) 4 n 2 n l > 2 0 σ n 2 n l n l n 2 0 2σ P [ n l n 2 > 2] = Q( 2/σ) Q(x) Viterbi P vtb 2 l 2Q( σ )=4Q( σ ) (2.28) l=3 P lev =(3/2)Q(1/σ) [6] Viterbi 3dB Viterbi 2 (2.28) PR(1,0,-1) 2 [14] R(l 2) 2 P vtb = 2 4 l Q( σ 1 R(l 2) ) (2.29) l= PR(1,0,-1) Viterbi Viterbi

38 36 2 k= 1 k= 2 k= 3 k= 4 B B b 3 (+1,+1) = 0 4(+1,+1) = 0 k =+1 b k = 1 2 ( 1,+1) = z 1 B 2 Errorneous path B 2 ( 1, 1) = 0 B 3 ( 1, 1) = 0 B ( 1,+1) = z 1 44 Correct path 2.14: Example of the path selection error in the Viterbi decodingfor PR(1,-1) channel. k =1, 2,..., l 1, l +1 k =1, 2,..., l 1, l +1 k=1, 2,..., l 1, l +1 k =1, 2,..., l 1, l (a) 4 error patterns in which a condition n n l 2 >2 is satisfied. k =1, 2,..., l 1, l +1 k =1, 2,..., l 1, l +1 k =1, 2,..., l 1, l +1 k =1, 2,..., l 1, l (b) 4 error patterns in which a condition n n 2 l >2 is satisfied. 2.15: All error patterns in the Viterbi decoder for the PR(1,-1) channel PR(1,0,-1) PR(1,0,-1) PR(1,0,-1) f c =1.0[1/T b ] 1 LPF 2 5 S/N S 0 p /N rms =20dB

39 2 37 Bit error rate Level det., Colored R(1)= 0.36 Level det., White R(1)= 0.00 Viterbi det, Colored R(1)= 0.36 Viterbi det, White R(1)= S/N [db] : Bit error rate of the Viterbi decoder for the PR(1,-1) channel. NLD Viterbi 0.05T b Viterbi 1 NLD = T b 2.7 PRML [16] (d, k, m, n, r) d NRZI k m n m/n r =1 r >1 (1) (d, k) 2

40 38 2 Bit error rate NLD= Bit by bit threshold detection Timing offset between data point and bit clock [ T b ] 2.17: Timingoffset dependency of the bit error rate in a PR(1,0,-1) channel with a 3-level threshold detector. SNR of an input isolated pulse: S 0 p /N rms =20 db, Equalizer: 1st order LPF with f c =1.0[1/T b ] and 5-tap FIR whose coefficients are determined by least squared error minimization method. (2) k PRML Viterbi PR(1,0,-1) 2 Viterbi k 1 (d, k, k 1,m,n,r) PRML 8/9 [17] 1 9 (0, 4, 4, 8, 9, 1) k =4 3 {ĉ k } 4 k 1 =4 Viterbi 4

41 2 39 Bit error rate NLD= Viterbi detection Timing offset between data point and bit clock [ T b ] 2.18: Timingoffset dependency of the bit error rate in a PR(1,0,-1) channel with a Viterbi decoder. SNR of an input isolated pulse: S 0 p /N rms =20 db, Equalizer: 1st order LPF with f c =1.0[1/T b ] and 5-tap FIR whose coefficients are determined by least squared error minimization method. 2.8 PR(1,0,-1) 8/9 PRML 4 PRML PR PRML (1 D)(1+D) n [18] n =2 EPR4 n =3 EEPR4 (1 D) (1 + D) n n NLD = PW 50 /T b 4 PR(1,0,-1) EPR4 8 3dB PRML [15] PRML EPR4 HDD PRML EEPR4 1-7 RLL Partial Erasure [19] PRML

42 PR Ungerboek [20] 8/10 MSN PR(1,0,-1) PRML 3dB [21] LSI [22] 9 HDD 8/10 8/ /9 16/18 EPR4 [23][24] 3 Decision Feedback Equalizer, DFE RAM [25] Noise-Predictive Maximum-Likelihood NPML [26][27] PRML Viterbi HDD 4 Low Density Parity Check Code, LDPC PLL

43 Network layer Host (Computer) Host interface bus 2. Data link layer ECC encode Buffer memory Corrected data or Retry control ECC decode Disk controller Formatter Adding flame sync. symbols Adding preamble pattern Channel encoding 1. Physical layer Write head Deformatter Flame Flame synchronization Channel decode Data read Data detection channel Equalization Channel synchronization Read head Recording medium 2.19: Disk storage system and OSI (Open System Interconnection) reference model OSI Open System Interconnection [28] OSI 2.19

44 42 2 User data symbol sequence User data Flame Sync User data #1 (Ex. 512 Byte) ECC User data #2 Sync Data sector Preamble Sync User data (channel encoded) ECC (channel encoded) 2.20: Flame structure of a data sector HDD Retry ( ) 1 Retry Retry Preamble PLL Preamble OSI

45 HDD HDD Zoned Bit Recording PLL Preamble PLL Preamble Preamble

46 44 2 PRML Viterbi 2.12 PR(1,0,-1) AGC Viterbi 3 {ĉ k } [8][15] 2.21 Variable Gain Amplifier, VGA MSE (Mean Squared Error) E[(z eq (kt b ) ĉ k ) 2 ] γ k =ĉ k {z eq (kt b ) ĉ k } +ĉ k 1 {z eq ((k 1)T b ) ĉ k 1 } (2.30) τ k τ k =ĉ k z eq ((k 1)T b ) ĉ k 1 z eq (kt b ) (2.31) 3 D/A VCO Voltage-Controlled Oscillator (a) (b) Zoned Bit Recording HDD Zoned Bit Recording

47 2 45 Readback signal VGA z ( t ) Analog equalizer A/D Digital equalizer z eq ( kt b ) Viterbi decoder Channel data Level control loop Loop filter Bit synchronization loop VCO Loop filter z z -1 - Tentative ternary data deetctor + D/A D/A z -1 + Level error: γ k Phase error: τ k 2.21: Example of the bit synchronization loop and the signal level control loop. HDD Constand Angular Velocity, CAV 2.22 Zoned Bit Recording Zoned Bit Recording N zone CAV Constand Linear Velocity, CLV Zoned Bit Recording

48 Disk surface Channel data rate 0 #3 #2 #1 Zone #N zone Radius 2.22: Principle of Zoned Bit Recording. 10 Zoned Bit Recording PLL f M f d = f M M d /N d HDD

49 Zoned Bit Recording HDD 1 (2) (1) (2)

50 (1) (2) I II

51 [1], (2),, MR , [2] E. R. Kretzmer, An efficient binary data communication system, IEEE Trans. Comm. Sys., Vol. CS-12, No. 2, pp. 250, June [3] E. R. Kretzmer, Generalization of a technique for binary data transmission, IEEE Trans. Comm. Tech., Vol. COM-14, pp , Feb [4] A. J. Viterbi, Error bounds for convolutional codes and an asymptotically optimum decodingalgorithm, IEEE Trans. Information Theory, Vol. IT-13, pp , Apr [5] H. Kobayashi and D. T. Tang, Application of partial-response channel codingto magnetic recordingsystems, IBM J. Res. Develop., Vol. 14, pp , July [6] H. Kobayashi, Application of probabilistic decoding to digital magnetic recordingsystems, IBM J. Res. Develop., No. 15, pp , [7] J. D. Coker, R. L. Galbraith, G. J. Kerwin, J. W. Rae and P.A. Ziperovich, Implementation of PRML in a rigid disk drive, IEEE Trans. Magn., Vol. 27, No. 6, pp , [8] R. D. Cideciyan, F. Dolivo, R. Hermann, W. Hirt and W. Schott, A PRML system for digital magnetic recording, IEEE J. Selected Areas in Communications, Vol. 10, No. 1, pp , [9],,, MR PRML, Vol. 48, No. 11, pp , Nov

52 50 2 [10] T. Yamakoshi, Y. Shimano and H. Yada, The effect of MR head nonlinearity on the PRML recordingchannel, IEEE Translation Journal of Magnetism in Japan Vol. 9, No. 3, May/June [11] H. K. Thaper and T. D. Howell, On the performance of Partial- Response Maximum-Likelihood and peak detection methods in digital magnetic recording, Digests of The Magnetic Recording Conference 1991 (TMRC 91), D1, IEEE, [12] M. J. Ferguson, Optimal reception for binary partial response channels, Bell System Technical Journal, Vol. 51, No. 2, pp , [13] R. W. Wood and D. A. Petersen, Viterbi detection of class IV partial response on a magnetic recording channel, IEEE Trans. Comm., Vol. COM34, No. 5, pp , [14],,, NRZL,, Vol. 35, No. 7, pp , [15] F. Dolivo, Signal processing for high-density digital magnetic recording, Proc. VLSI and Computer Peripherals, 1-91/1-96, IEEE, [16] P. Siegel, Recording codes for digital magnetic storage, IEEE Trans. Magn. Vol. MAG21, No. 5, pp , [17] J. S. Eggenberger and A.M. Patel, Method and apparatus for implementingoptimum PRML codes, U.S. Patent 4,707,681, [18] H.K. Thaper and A.M. Patel, A class of partial response systems for increasing storage density in magnetic recording, IEEE Trans. on Magn. Vol. 23, No. 5, pp , [19] R. T. Behrens and A. J. Armstrong, An advanced read/write channel for magnetic disk storage, Proc. 26th Asilomar Conf. on Signals, Systems & Computers, pp , [20] J. K. Wolf and G. Ungerboeck, Trellis coding for partial-response channels, IEEE Trans. Commum., Vol. COM34, No. 8, pp , [21] H. K. Thaper, J. Rae, C. Shung, R. Karabed and P. Siegel, On the performance of a rate 8/10 matched spectral null code for Class-4 Partial Response, IEEE Trans. Magn., Vol. 28, No. 5, pp , 1992.

53 2 51 [22],,,,,,,,,,,, HDD 100Mbps8/10 PRML LSI,, ICD97-113, pp , [23],,,, 16/18 EPR4,, MR97-67, [24] M. Uchida, N. Hayashi and H. Yada, A 16/18 Trellis Code for EPR4 Magnetic Recording Channel, Conference record of GLOBECOM 98, S118.5, Sydney, Australia, Nov (Refereed). [25] K. Fisher, J. Cioffi and C. M. Melas, An adaptive DFE for storage channels sufferingfrom nonlinear ISI, Proc. of IEEE ICC 89, pp , [26] P. R. Chevillat, E. Eleftheriou and D. Maiwald, Noise predeictive partial-response equalizers and applications, IEEE Conf. Records ICC 92, pp , June 14-18, [27] J. D. Coker, E. Eleftheriou, R. L. Galbraith and W. Hirt, Noise- Predeictive Maximum Likelihood (NPML) Detection, IEEE Trans. Magn., Vol. 34, No. 1, pp , Jan [28] A. S. Tanenbaum, Computer networks, Prentice-Hall software series, pp , 1981.

54

55 I

56

57 3 PRML 1 PRML Partial-Response Maximum-Likelihood Phase-Locked Loop, PLL PLL 2 sample/bit PLL Viterbi Viterbi PRML PRML 10 Mbit/s PRML Partial-Response Maximum-Likelihood [1] [2] PRML Viterbi PRML ,, PRML,, Vol. J75-C-II, No. 11, pp , c 1992 IEICE. H. Yada, et al., A Novel Digital Signal Processing Bit Synchronizer for a PRML Recording Channel, Electronics and Communications in Japan, Part 2: Electronics, Vol. 76, No. 4, pp , Scripta Technica, Inc., Apr

58 56 3 PR(1,0,-1) 4, PR4 1/2 [3] Viterbi PRML [4][5] PLL Phase- Locked Loop Voltage-Controlled Oscillator, VCO Viterbi PRML LSI 2 sample/bit PRML PLL Decision-directed digital PLL, D3PLL PRML Viterbi Interpolated TimingRecovery, ITR PRML ITR ITR F. M. Gardner [13]

59 [12] F. M. Gardner MODEM (a) (b) (1) (2) (3) (4) (5) (6) (4)(5)(6) [16] Sinc F. M. Gardner Aachen RWTH G. Ascheid 1989 [11] QASK Quadrature Amplitude Shift Keying PSK Phase Shift Keying 1988 F. M. Gardner European Space Agency ITR [14][15] 1989 S. Nakamura Lagrange QPSK Quadrature PSK 128 kbit/s [7] VCO ITR NTT QPSK VCO ITR [8] 30 Mbit/s [9] ITR ITR [17][18][19][20] [21] Stanford D. Kim 2 Minimum Mean Square Error, MMSE

60 58 3 [22] [23][24] ITR ITR PRML G. Ascheid F. M. Gardner Stationary head type Digital Audio Tape recorder, SDAT [25][26] 1 20 SDAT Non-Tracking NT-1 [27] PRML SDAT 1990 Viterbi [28] FIR Finite Impulse Response PR DPLL Digital PLL Sony Research Forum Proceedins of Sony Research Forum 1991[29] [30][31] [32][33] 1994 IBM C. M. Melas P. Sutardja [34][35] ITR

61 3 59 ITR 1997 Stanford Z. Wu J. M. Cioffi [36] MMSE PR(1,0,-1) PR4ML Nyquist 1.05 sample/bit HDD Digital Zero Phase Start Cirrus Logic M. Spurbeck R. T. Behren PR4ML ITR FIR 1.1 sample/bit [37] 1995 ITR [38] LSI [39][40] STMicroelectronics ITR LSI [41] ITR Minnesota T. Oenning J. Moon ITR Amplitude Error Predictor, AEP [42] ITR Data Storage Institute G. Mathew MDFE (Multilevel Decision Feedback Equalization) [43] Carnegie Mellon Y. Yuan Turbo VCO PLL ITR AFTR (Adaptive Filter TimingRecovery 3 [44] IBM D. Berman ITR Enhanced Linear Interpolation (ELI) [45] 4 FIR 2 ITR ITR ELI 1/2 University of California at San Diego J. S. Goldberg J. K. Wolf [46]

62 M. Sawada ITR Zero Frequency Start [47] ITR ITR II HDD [48] [49] ITR 2 sample/bit 1 sample/bit PRML PRML 3.1 PRML A/D 2 f s EQ FIR PR(1,0,-1) PLL D3PLL (Interpolator) Bit synchronizer Viterbi Viterbi Viterbi Mbit/s Viterbi NLD= S/N S 0 p /N rms 20 db

63 3 61 Input signal A/D EQ (FIR) Bit synchronizer Inter 5 polator Phase data Viterbi decoder Data 1 Fixed clock L D3PLL Level tracking loop 5 3.1: Block diagram of the new PRML read channel which operates with a unique fixed clock. PW 50 T b NLD = PW 50 /T b Reed-Solomon 1/2 ±0.1% PR(1,0,-1) PR(1,0,- 1) 3-1, 0, +1 0 radian π radian 3.3 PR(1,0,-1) S k T s (= 1/f s ) kt s S(t) k (Data point) Sk 0 S0 k S k 2 sample/bit Sk T s

64 : Eye-pattern of the equalized PR(1,0,-1) channel signal. kt s kt s θ k kt s Sk 0 0 radian θ k S k 3.3 [(k 2)T s, (k 1)T s ] (k 1)T s Sk 2 0 θ k 1 L bit T b 2π radian 2 L (quantized phase slot) 3.3 L = 4 bit T b 16 θ k 2 =4 HEX,θ k 1 = C HEX,θ k =4 HEX HEX 16

65 S k+1 S k +2 Signal amplitude 0 0 Signal sample S k- 2 S k- 1 Sk 0 S k 0 t Data point -1-1 a tme slot 0 (Data) ( k -3) T s ( k -2) Ts ( k -1) T s 0 S k -1 (Data) S 0 k- 2 S k- 1 θ k S a quantized phase slot k t S k- 3 θ k- 2 θ k- 1 Phase [radian] 0 π 0 Phase [Hex] C D E F A B C D E F Example: L = 4 [bits], 2-1 = 15 L D = F HEX 3.3: Data points and signal samples in the PR(1,0,-1) channel output waveform. θ k {S k } (1) θ k ˆθ k (2) ˆθ k Ŝ0 k (1) PLL (2)

66 64 3 ^ θk- 1 (Previous output phase) S k+1 Data detector Control logic (Loop control signal) modify_θ k z -3 S k (Current signal sample) (Instantaneous phase) Phase detector + - α (Loop gain) 1st-order DPLL π (Output phase) + -1 z ^ θk- 1 ^ θk 3.4: Signal flow diagram of the Decision-directed digital phase-locked loop (D3PLL). 3.4 PLL PLL D3PLL 3.4 Phase Detector DPLL Data Detector Control Logic S k θk d DPLL DPLL 1 θk d ˆθ k θk d 2 modify θ k DPLL S(t) 3.5 θk d θ k S k 1 (θ k ) S k (θ k )

67 3 65 Signal amplitude S k S(t) 0 t =( k -1) Ts t=kt s t S k- 1 L- 1 d θ k θ k 2 π [radian] s θk θ k :Detected phase. :Data point phase. 3.5: Principle of the instantaneous phase detection based on linear interpolation. [25] θ d k = π S k (θ k ) S k (θ k ) S k 1 (θ k ) (3.1) L bit DPLL 2 L T s π radian θ k θk d S(t) NLD =1.5 Lorentz 1/T b 1 Low-Pass Filter, LPF 5 FIR 6T b 3, 0, +1, +1, 0, 1, 1, 0, (3.1)

68 Detected phase θ [ x π radian] d k Ideal case Detected phase Phase θ [ x π radian] k 2.0 Phase detection error θ e [ x π radian] Phase θ k [ x π radian] 3.6: Input-output characteristics θk d(θ k) of the phase detector and the deterministic phase detection error θ e = θ k θk d. 3.6 θ k θk d θ e θ k θk d θ k 3.7 NLD = π radian NLD = π radian NLD = π radian NLD

69 3 67 Max. phase detection error [ x π radian] Normalized linear density NLD [ PW 50 /Tb ] 3.7: Maximum deterministic phase detection error as a function of the normalized linear density NLD. (3.1) 2 S k,s k 1 f(s k 1,S k ) πs k /(S k S k 1 ) f(s k 1,S k ) S k, S k 1 Taylor 2 f(s k 1,S k )=f( S k 1 + S k 1, S k + S k ) = f( S k 1, S f(s k 1,S k ) f(s k 1,S k ) k )+ S k 1 Sk, S S k 1 + S k k 1 S k Sk, S k 1 +O(( S) 2 ) (3.2) S/N 20 db S 1/10 2 (3.2) 1 c k 1,c k

70 68 3 c k 1 f(s k 1,S k ) S = π Sk k 1 Sk, S k 1 ( S k S (3.3) k 1 ) 2 = π Sk, S k 1 c k f(s k 1,S k ) S k S k 1 ( S k S k 1 ) 2 (3.4) S k 1, S k c k 1,c k θ k S k [ S k 1, S k ] T (3.5) c k (θ k ) [c k 1 (θ k ),c k (θ k )] T (3.6) θk d (3.2) 1 θ d k(θ k ) S T k c k (θ k ) (3.7) 2 1 S k 2 2 θ k 1 2 S k 0 1 θ d k (θ k) 0 θ d k (θ k) = E θk, S[ θk d (θ k)] = E θk [E S [ θk d (θ k) θ k ]] = E θk [E S [ S T k ]c k (θ k ) θ k ] = 0 (3.8) 2 θ k σ θ 2 (θ k) = E θk, S[( θk d θd k )2 ]=E θk [E S [( θk d (θ k)) 2 θ k ]] = E θk [c T k (θ k )R S c k (θ k ) θ k ] (3.9) R S 0 ( ) E S [ Sk 1 2 R S = ] E S[ S k S k 1 ] E S [ S k 1 S k ] E S [ Sk 2] (3.10) σ S 2 r 01 ( ) R S = σ S 2 1 r 01 (3.11) r 01 1

71 3 69 Correlation r 01 between S k and S k LPF with f c = 0.9 LPF with f c = 1.0 Lorentz isolated pulse. PR(1,0, 1) channel with 1st order LPF ( f c = 1/T b ) and 5 tap FIR EQ Normalized linear density NLD [ PW 50 /Tb ] 3.8: Correlation coefficient r 01 between two adjacent noise samples S k and S k 1. LPF S k 1,S k θ k σ S σ θ G(θ k ) σ θ /σ S (3.9) (3.11) G(θ k ) = = { ( c T k (θ k ) 1 r 01 r 01 1 ) c k (θ k ) } 1/2 c 2 k 1 (θ k)+2r 01 c k 1 (θ k )c k (θ k )+c 2 k (θ k) (3.12) c k (θ k ) θ k

72 70 3 σ θ /σ s G= Noise to jitter conversion gain Maximum gain max [ G( θk)] θ k Average gain Eθ [ G(θ k) θ k] k 6 Tb preamble based on Lorentz isolated pulse. PR(1,0, 1) channel with 1st order LPF ( f c = 1/T b ) and 5 tap FIR EQ. L 1 2 = Normalized linear density NLD [ PW 50 /Tb ] 3.9: Noise to jitter conversion gain G of the phase detector. NLD G(θ k ) θ k, 0 k 15 E θk [G(θ k ) θ k ] max θk G(θ k ) Lorentz 6T b PR(1,0,-1) 3.9 NLD NLD 1/2T b Roll-off S 0 1 /N rms 1/σ S σ θ = G(θ k )σ S σ θ radian σ θ (θ k )= G(θ k ) S 0 1 /N rms (3.13) L π radian T s 2 L 1 σ L radian σ L = π 2 (L 1) 2 3 (3.14)

73 DPLL 1 θk d θ k ˆθ k modulo(2π) radian α, 0 <α<1 if(modify θ k = 0) then (free run) ˆθ k = ˆθ k 1 + π elseif(modify θ k = 1) then (phase modification) ˆθ k = ˆθ k 1 + π + α(θk d (ˆθ k 1 + π)) (3.15) D3PLL PR(1,0,-1) modify θ k π radian 2 1 π radian PR(1,0,-1) 3, +1, 0, 1,, 1, 0, +1,,, +1, 1,, 1, +1, π radian D3PLL D3PLL 1 3 d k+3 DPLL

74 72 3 Viterbi -1, 0, bit-by-bit ternary threshold detection 3.10 S k+2 S k+3 +A th (k +3)T s θ + k+3 θ + k+3 = π S k+3 A th S k+3 S k+2 (3.16) ˆθ k+3 Sk+3 0 A th Sk+3 0-1, 0, +1 ˆθ k+3 D3PLL ˆθ k 1 D3PLL D3PLL PR(1,0,-1) S/N 6T b D3PLL D3PLL α D3PLL PLL D3PLL D3PLL

75 3 73 Signal amplitude Threshold Level +A th S k+2 Data point 0 S k+3 θ ^ k+3 + k+3 S k+3 θ 0 t t=( k+2) T s t=( k+3) T s -A th 2 π L-1 [radian] 3.10: Bit-by-bit ternary data detection in the D3PLL. D3PLL 1 (3.15) D3PLL 3 ( ) (+1 0 1) 3 T s mt s 6T b 3T b m =6 T b =2T s m mt s 3.6 8/9 m 28 m m PLL m PLL PLL mt s m m PLL 2 D3PLL mt s D3PLL θ k 1 mt s (m 1)T s (m +1)T s

76 74 3 PLL αt s, 0 <α<1 1 mt s 3 D3PLL θ, 0 θ<2π modulo(2π) D3PLL θ, < θ <+ 1 mt s m π (3.15) mt s k = lm t = lmt s l l θ k = θ k m + α(θk d θ k m ) for k = ml (3.17) l θ l = θ l 1 + α(θ d l θ l 1 ) (3.18) PLL mt s D3PLL z 1 mt s (3.18) z Θ(z) Θ d (z) = α 1 (1 α)z 1 (3.19) Θ d (z) θ d k z Z[θd k ] 0 <α<1 z p =1 α PLL u(k) α(1 α) l u(k) if k = lm h k = h k 1 u(k) if k lm (3.20) k = lm l h l = α(1 α) l u(l) j

77 Transfer gain α= α = 0.3 α= Normalized frequency [1/ mts ] 3.11: Closed loop transfer gain characteristics of the 1st order DPLL with the coefficient α. The loop samplingfrequency is mt s. Θ(ω) Θ d = (ω) = = Θ(z) Θ d (z) z=e jωmts α 1 (1 α)e jωmts α 1+(1 α)2 2(1 α) cos(ωmt s ) (3.21) 3.11 [0, 1/4mT s ] mt s m α m 1/4mT s khz m =28, 1/T s = 20 MHz 1/4mT s = 178 khz

78 76 3 D3PLL (3.18) θl d 1 θ l +(α 1) θ l 1 = αθ d l (3.22) D3PLL l <0 k = lm < 0 θ k =0 θl d θd step θ l =(1 (1 α) l+1 )θstep d u(l) (3.23) 0 < 1 α<1 lim θl = θstep d l θ res = lim (θstep d θ l ) 0 θ res α l 1/2 D3PLL ω radian/s mt s mt s ω radian z θ res radian θ res = lim l (θ d l θ l ) = lim z 1 (1 z 1 ) = lim z 1 (1 z 1 ) ( Z[θl d ] Θ(z) ) Θ d (z) Z[θd l ] { } 1 α 1 (1 α)z 1 z (z 1) 2 mt s ω = 1 α α mt s ω (3.24) f 0 =1/2T s f/f 0 θ res radian θ res = 1 α α f f 0 mπ (3.25) α mt s D3PLL PLL PLL

79 D3PLL 1 [50] ±0.1% ±0.1% D3PLL 2T s 1 1 αt s [ ] = T<αT s (3.26) 2mT s f 0 =1/T 0 = 1/(2mT s ) f f f 0 f 0 + f = 1 T 0 T 1 (1 + T ) (3.27) T 0 T 0 f f 0 T T 0 (3.28) T <αt s,t 0 =2mT s f/f 0 f f 0 < α 2m (3.29) α m D3PLL θk d θk d = E[θd k ]+ θd k θ k ˆθ k E[ ] θk d θk d E[ θd k ]=0 σ2 θ (3.7) LPF

80 78 3 5T s mt s,m 6 l D3PLL E[θl d] ˆθ l E[ˆθ l ]=E[θl d] Unbiassed m ˆθ 0 l ˆθ l ˆθ l = (1 α)ˆθ l 1 + αθl d = (1 α) 2 ˆθl 2 + αθl d + α(1 α)θd l 1 = = l 1 (1 α) l ˆθ0 + α (1 α) j θl j d (3.30) j=0 l 1 E[ˆθ l ]=(1 α) l E[ˆθ 0 ]+α (1 α) j E[θl j d ] (3.31) θ E[θl j d ]=θ 2 closed form j=0 E[ˆθ l ]=(1 α) l E[ˆθ 0 ]+(1 (1 α) l )θ (3.32) 0 < 1 α<1 lim E[ˆθ l ]=θ (3.33) l (Asymptotically unbiased) σ 2 E[(ˆθ ˆθ l E[ˆθ l ]) 2 ] l h l lim l σ2 = σ 2 ˆθ l θ h l 2 = σ θ 2 α(1 α) l 2 = l=0 l=0 α 2 α σ2 θ (3.34)

81 3 79 PLL σ ˆθ α σ ˆθ = σ θ (3.35) 2 α α 0 <α<1 0 < σ ˆθ <σ θ α D3PLL 1 D3PLL 1 IIR Infinite Impulse Response DC B mpy modulo(2 L ) L B mpy (Dead Band) DC DC θ limit radian [51] 2 Bmpy θ limit π 1 1 α (3.36) B mpy 2 [51] e mpy 3.12 ˆθ l (1 α) l u(l) e mpy 2 2(Bmpy 1) /12 { 2 2(B mpy 1) σ Bmpy = π 12 = π 2 (Bmpy 1) 2 3α(2 α) } 1/2 (1 α) l 2 l=0 (3.37) B mpy

82 80 3 e mpy θ d l α θ ^ l 1 z : Signal flow graph of the 1st order DPLL with the truncation error at the coefficient multiplier. D3PLL D3PLL 2 D3PLL D3PLL 3.7 (3.13) σ S (3.14) σ L L (3.36) θ limit (3.37) σ Bmpy α B mpy (3.25) θ res α (3.29) α α D3PLL σ S σ L α D3PLL PLL 1

83 3 81 α α 2 0 D3PLL NLD =2.0 S 0 1 /N rms =20dB m = 6 m =28 1/T b 1/2 0.1 % α =0.3 PLL 3.9 σ θ /σ S =1.486 (3.35) D3PLL σ ˆθ π radian π T b /2 T b 3.12 % θ res (3.25) 0.014π radian T b 0.7 % T b 3.27 % ±2.5% m =28 ±0.54 % α PLL 2 m Viterbi 3 i, j, k k i, j k 2 L 1 [Step-1]

84 82 3 Signal amplitude 0 Sample Data point 0 S k +1 S k+2 S 1 k+ S k+3 t Sk- 1 θ ^ k Sk- 3 Sk- 2-1 L-1 2 Quantized phase slots... i, j k T s :a time slot 3.13: Principle of the data point signal interpolation. 1 2 L 1 {x i } S k S k if i =2 L 1 k x i = 0 if i 2 L 1 k (3.38) [Step-2] 3.13 f s /2 FIR LPF j {x i } {h i } N y j y j = N/2 1 i= N/2 h i x j i (3.39) [Step-3] PLL D3PLL 1

85 3 83 Input signal vector S. Inner product Interpolated sample S ^ 0k Phase data ^ θ k h ^θk Switch..... h 0 h h..... h 1 2 Coefficient vectors L 1 (2 1) 3.14: Signal flow diagram of the interpolator. S k kt s Sk 0 θ k D3PLL ˆθ k ˆθ k Ŝ0 k Ŝk 0 = y j, j =2 L 1 k ˆθ k (3.40) (3.38) x i =0 (3.39) N FIR h =[h N/2,,h 1,h 0,h 1,,h N/2 1 ] 2 L 1 ˆθ k h 0,, h (2 L 1 1) D3PLL ˆθ k 3.14 N/2 L 1 FIR

86 84 3 rms interpolation error (Signal amplitude = 1.0) N=128, 2 = 32 L- 1 N=256, 2 = 64 Cut-off frequency (unit [1/ T ] ) ch L : Simulation results on rms interpolation error vs. filter cut-off frequency N FIR rms PR(1,0,-1) h i Hamming N K norm w(i) sin( 2πifc 2 h i = L 1 f s )/i if i 0 K norm w(i) if i =0 (3.41) N/2 i N/2 K norm w(i) ( w(i) = cos 2π i + N ) 2 N (3.42) 3.15 rms % rms S/N 20 db bit

87 3 85 rms interpolation error (Signal amplitude = 1.0) L- 1 N=128, 2 = 32 L- 1 N=256, 2 = Coefficients word length [bits] 3.16: Quantization of tap coefficients vs. rms interpolation error. Hard Disk Drive R/W amp. Digital Signal Generator Read Signal Write data PRML Demodulator Error Analyzer VME Bus GP-IB Interface Host Computer 3.17: Configuration of the experimental PRML recording system with the new bit-synchronizer. 3.6 PRML PRML PRML

88 86 3 AGC Automatic Gain Control -3 db f c = 7 MHz 1 LPF 8 bit A/D 12 FIR PR(1,0,-1) 10 bit L = 6 bit 1 T s FIR LPF 8 RAM Random Access Memory RAM 8 bit Viterbi PRML Viterbi inch 8.3 µm MIG (Metal In Gap 10 Mbit/s 9.58 m/s µm/bit 115 ns Byte 512 Byte D3PLL 6T b D3PLL (1) (2) 1+x 4 + x 9 M 8/9 2 8/9 D3PLL RLL (d, k, m, n, r) = (0, 10, 8, 9, 1) 8/9 3, 1, 0, +1,, +1, 0, 1, 14 bit

89 S k Signal amplitude of Time [ µ s] 3.18: Distribution of data-asynchronous signal samples. Experimental results S ^k0 60 Signal amplitude of Time [ µ s] : Distribution of synchronized data samples Ŝ0 k. Experimental results , 0, -1 3 D3PLL ˆθ k 3.20 PRML 0.3% ˆθ k PRML

90 88 3 Phase data θ (32= π [radian]) ^ k Time [ µ s] 3.20: Phase data ˆθ k of the D3PLL. Experimental results. Viterbi T b (3.29) (3.25) 3.22 α (3.35) D3PLL 3.23 C/N 3 Viterbi C/N (1.66 MHz) 2.66 MHz 30 KHz PRML Viterbi Viterbi 3 1dB [28]

91 3 89 Loop gain α = 0.5 Loop gain α = 0.3 Loop gain α = Bit error rate Channel bit rate deviation [%] (Preamble pattern, Threshold detection.) 3.21: Experimental bit error rate for 6T preamble pattern as a function of channel bit rate deviation Loop gain α = 0.5 Loop gain α = 0.3 Loop gain α = 0.1 Bit error rate Channel bit rate deviation [%] (Random pattern, Threshold detection.) 3.22: Experimental bit error rate for random data pattern as a function of channel bit rate deviation.

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