SEIKO EPSON CORPORATION 2011, All rights.
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1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17554/564 Rev.1.3
2 SEIKO EPSON CORPORATION 2011, All rights.
3 S1 C 17xxx F 00E : & 0A : TCP BL 2 0B : & BACK 0C : TCP BR 2 0D : TCP BT 2 0E : TCP BD 2 0F : & FRONT 0G : TCP BT 4 0H : TCP BD 4 0J : TCP SL 2 0K : TCP SR 2 0L : & LEFT 0M : TCP ST 2 0N : TCP SD 2 0P : TCP ST 4 0Q : TCP SD 4 0R : & RIGHT 99 : D: F: QFP B: BGA C: S1: S5U1 C H : 1: Version 1 Hx : ICE Dx : Ex : ROM Mx : ROM Tx : Cx : Sx : Yx : 17xxx: S1C17xxx C: S5U1:
4 S1C S1C CPU S1C CPU PSR , Flash Flash Flash Flash FLASHC Read Wait Control (FLASHC_WAIT) RAM RAM IRAM Size (MISC_IRAMSZ) x4000~ x5000~ S1C17 I/O LVDD I/OHVDD AVDD Flash VPP S1C S1C VD1 Control (VD1_CTL) #RESET P S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation i
5 6 ITC ITC Vector Table Address Low/High s (MISC_TTBRL, MISC_TTBRH) ITC S1C NMI HALT, SLEEP Interrupt Level Setup x (ITC_LVx) CLG CLG CLG OSC OSC IOSCS1C CPU CCLK PCLK FOUTA, FOUTB Clock Source Select (CLG_SRC) Oscillation Control (CLG_CTL) Noise Filter Enable (CLG_NFEN) FOUTA Control (CLG_FOUTA) FOUTB Control (CLG_FOUTB) IOSC Control (CLG_IOSC) PCLK Control (CLG_PCLK) CCLK Control (CLG_CCLK) P P MUX P Px Port Input Data s (Px_IN) Px Port Output Data s (Px_OUT) Px Port Output Enable s (Px_OEN) Px Port Pull-up Control s (Px_PU) Px Port Interrupt Mask s (Px_IMSK) Px Port Interrupt Edge Select s (Px_EDGE) Px Port Interrupt Flag s (Px_IFLG) Px Port Chattering Filter Control s (Px_CHAT) P0 Port Key-Entry Reset Configuration (P0_KRST) ii Seiko Epson Corporation S1C17554/564 TECHNICAL MANUAL
6 Px Port Input Enable s (Px_IEN) P0[3:0] Port Function Select (P00_03PMUX) P1[3:0] Port Function Select (P10_13PMUX) P1[7:4] Port Function Select (P14_17PMUX) P2[3:0] Port Function Select (P20_23PMUX) P2[7:4] Port Function Select (P24_27PMUX) P3[3:0] Port Function Select (P30_33PMUX) P3[7:4] Port Function Select (P34_37PMUX) P4[3:0] Port Function Select (P40_43PMUX) P4[5:4] Port Function Select (P44_45PMUX) P5[3:0] Port Function Select (P50_53PMUX) P5[5:4] Port Function Select (P54_55PMUX) T T RUN/STOP T T T16 Ch.x Count Clock Select s (T16_CLKx) T16 Ch.x Reload Data s (T16_TRx) T16 Ch.x Counter Data s (T16_TCx) T16 Ch.x Control s (T16_CTLx) T16 Ch.x Interrupt Control s (T16_INTx) T16F T16F RUN/STOP T16F T16F T16F Ch.x Count Clock Select s (T16F_CLKx) T16F Ch.x Reload Data s (T16F_TRx) T16F Ch.x Counter Data s (T16F_TCx) T16F Ch.x Control s (T16F_CTLx) T16F Ch.x Interrupt Control s (T16F_INTx) PWMT16A T16A T16A T16A / S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation iii
![.. 8-18 P4[3:0] Port Function Select (P40_43PMUX)... 8-19 P4[5:4] Port Function Select (P44_45PMUX)... 8-19 P5[3:0] Port Function Select (P50_53PMUX)... 8-20 P5[5:4] Port Function Select (P54_55PMUX).](/docs-images/57/20072722/images/page_6.jpg ".. 8-21 9 16 T16...9-1 9.1 T16...9-1 9.2...9-2 9.3...9-2 9.4...9-2 9.5...9-3 9.6 RUN/STOP...9-3 9.7 T16...9-4 9.8 T16...9-4 9.9...9-5 T16 Ch.x Count Clock Select s (T16_CLKx)... 9-5 T16 Ch.")
7 RUN/STOP T16A T16A Clock Control Ch.x (T16A_CLKx) T16A Counter Ch.x Control s (T16A_CTLx) T16A Counter Ch.x Data s (T16A_TCx) T16A Comparator/Capture Ch.x Control s (T16A_CCCTLx) T16A Comparator/Capture Ch.x A Data s (T16A_CCAx) T16A Comparator/Capture Ch.x B Data s (T16A_CCBx) T16A Comparator/Capture Ch.x Interrupt Enable s (T16A_IENx) T16A Comparator/Capture Ch.x Interrupt Flag s (T16A_IFLGx) CT CT RUN/STOP CT Clock Timer Control (CT_CTL) Clock Timer Counter (CT_CNT) Clock Timer Interrupt Mask (CT_IMSK) Clock Timer Interrupt Flag (CT_IFLG) SWT SWT BCD RUN/STOP SWT Stopwatch Timer Control (SWT_CTL) Stopwatch Timer BCD Counter (SWT_BCNT) Stopwatch Timer Interrupt Mask (SWT_IMSK) Stopwatch Timer Interrupt Flag (SWT_IFLG) WDT WDT WDT NMI/ WDT RUN/STOP WDT HALT, SLEEP Watchdog Timer Control (WDT_CTL) Watchdog Timer Status (WDT_ST) iv Seiko Epson Corporation S1C17554/564 TECHNICAL MANUAL
8 15 UART UART UART UART IrDA UART Ch.x Status s (UART_STx) UART Ch.x Transmit Data s (UART_TXDx) UART Ch.x Receive Data s (UART_RXDx) UART Ch.x Mode s (UART_MODx) UART Ch.x Control s (UART_CTLx) UART Ch.x Expansion s (UART_EXPx) UART Ch.x Baud Rate s (UART_BRx) UART Ch.x Fine Mode s (UART_FMDx) UART Ch.x Clock Control s (UART_CLKx) SPI SPI SPI SPI SPI SPI Ch.x Status s (SPI_STx) SPI Ch.x Transmit Data s (SPI_TXDx) SPI Ch.x Receive Data s (SPI_RXDx) SPI Ch.x Control s (SPI_CTLx) I 2 CI2CM I2CM I2CM I2CM I 2 C Master Enable (I2CM_EN) I 2 C Master Control (I2CM_CTL) I 2 C Master Data (I2CM_DAT) I 2 C Master Interrupt Control (I2CM_ICTL) I 2 CI2CS I2CS I2CS I2CS S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation v
9 I2CS I 2 C Slave Transmit Data (I2CS_TRNS) I 2 C Slave Receive Data (I2CS_RECV) I 2 C Slave Address Setup (I2CS_SADRS) I 2 C Slave Control (I2CS_CTL) I 2 C Slave Status (I2CS_STAT) I 2 C Slave Access Status (I2CS_ASTAT) I 2 C Slave Interrupt Control (I2CS_ICTL) USI [S1C17564] USI USI USI USI USI UART SPI I 2 C UART SPI I 2 C USI UART SPI I 2 C I 2 C USI Ch.x Global Configuration s (USI_GCFGx) USI Ch.x Transmit Data Buffer s (USI_TDx) USI Ch.x Receive Data Buffer s (USI_RDx) USI Ch.x UART Mode Configuration s (USI_UCFGx) USI Ch.x UART Mode Interrupt Enable s (USI_UIEx) USI Ch.x UART Mode Interrupt Flag s (USI_UIFx) USI Ch.x SPI Master Mode Configuration s (USI_SCFGx) USI Ch.x SPI Master Mode Interrupt Enable s (USI_SIEx) USI Ch.x SPI Master Mode Interrupt Flag s (USI_SIFx) USI Ch.x I 2 C Master Mode Trigger s (USI_IMTGx) USI Ch.x I 2 C Master Mode Interrupt Enable s (USI_IMIEx) USI Ch.x I 2 C Master Mode Interrupt Flag s (USI_IMIFx) USI Ch.x I 2 C Slave Mode Trigger s (USI_ISTGx) USI Ch.x I 2 C Slave Mode Interrupt Enable s (USI_ISIEx) USI Ch.x I 2 C Slave Mode Interrupt Flag s (USI_ISIFx) IR REMC REMC REMC vi Seiko Epson Corporation S1C17554/564 TECHNICAL MANUAL
![.. 18-16 19 USI [S1C17564]...19-1 19.1 USI...19-1 19.2 USI...19-2 19.3 USI...19-2 19.4 USI...19-3 19.4.1 USI...19-4 19.4.2...19-4 19.4.3...19-4 19.4.4 UART...19-4 19.4.5 SPI...19-5 19.4.6 I 2 C.](/docs-images/57/20072722/images/page_9.jpg "..19-6 19.5...19-6 19.5.1 UART...19-6 19.5.2 SPI...19-7 19.5.3 I 2 C...19-9 19.6...19-19 19.7 USI...19-20 19.7.1 UART...19-20 19.7.2 SPI...19-21 19.7.3 I 2 C...19-22 19.7.4 I 2 C...19-22 19.8.")
10 REMC REMC Configuration (REMC_CFG) REMC Carrier Length Setup (REMC_CAR) REMC Length Counter (REMC_LCNT) REMC Interrupt Control (REMC_INT) A/DADC ADC ADC A/D A/D A/D / A/D A/D A/D A/D A/D A/D A/D A/D Conversion Result (ADC10_ADD) A/D Trigger/Channel Select (ADC10_TRG) A/D Control/Status (ADC10_CTL) A/D Clock Control (ADC10_CLK) A/D Comparator Setting (ADC10_COM) DBG Debug Mode Control 1 (MISC_DMODE1) Debug Mode Control 2 (MISC_DMODE2) IRAM Size Select (MISC_IRAMSZ) Debug RAM Base (DBRAM) Debug Control (DCR) Instruction Break Address 2 (IBAR2) Instruction Break Address 3 (IBAR3) Instruction Break Address 4 (IBAR4) COPRO S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation vii
11 DC SPI I 2 C USI S1C A/D Flash Appendix A I/O... AP-A-1 0x4100 0x4107, 0x506c UART (with IrDA) Ch.0... AP-A-5 0x4120 0x4127, 0x506d UART (with IrDA) Ch.1... AP-A-6 0x4200 0x4208 Fine Mode 16-bit Timer Ch.0... AP-A-7 0x4220 0x bit Timer Ch.0... AP-A-7 0x4240 0x bit Timer Ch.1... AP-A-8 0x4260 0x bit Timer Ch.2... AP-A-8 0x4280 0x4288 Fine Mode 16-bit Timer Ch.1... AP-A-9 0x4306 0x431c Interrupt Controller... AP-A-9 0x4320 0x4326 SPI Ch.0... AP-A-10 0x4340 0x4346 I 2 C Master... AP-A-11 0x4360 0x436c I 2 C Slave... AP-A-11 0x4380 0x4386 SPI Ch.1... AP-A-12 0x43a0 0x43a6 SPI Ch.2... AP-A-12 0x5000 0x5003 Clock Timer... AP-A-12 0x5020 0x5023 Stopwatch Timer... AP-A-13 0x5040 0x5041 Watchdog Timer... AP-A-13 0x5060 0x5081 Clock Generator... AP-A-13 0x50c0 0x50cf USI Ch.0... AP-A-15 0x50e0 0x50ef USI Ch.1... AP-A-17 0x5121 Power Generator... AP-A-18 0x5200 0x52ab P Port & Port MUX... AP-A-18 0x4020, 0x5322 0x532c MISC s... AP-A-26 0x5340 0x5346 IR Remote Controller... AP-A-27 0x5380 0x5388 A/D Converter... AP-A-27 0x5068, 0x5400 0x540c 16-bit PWM Timer Ch.0... AP-A-28 0x5069, 0x5420 0x542c 16-bit PWM Timer Ch.1... AP-A-30 0x506a, 0x5440 0x544c 16-bit PWM Timer Ch.2... AP-A-31 0x506b, 0x5460 0x546c 16-bit PWM Timer Ch.3... AP-A-33 0x54b0 Flash Controller... AP-A-34 0xffff84 0xffffd0 S1C17 Core I/O... AP-A-34 Appendix B... AP-B-1 B.1... AP-B-1 B.2... AP-B-2 viii Seiko Epson Corporation S1C17554/564 TECHNICAL MANUAL
12 Appendix C... AP-C-1 Appendix D... AP-D-1 Appendix E... AP-E-1 S1C17554/564 TECHNICAL MANUAL Seiko Epson Corporation ix
13 S1C17554/ S1C17554 S1C17564 CPU CPU EPSON16 RISC CPU S1C17 COPRO Flash 128K / 10 min. FLS V1.0 / / VPP ICDmini RAM 16K 2 OSC3/OSC1 3 IOSC/OSC3/OSC1 IOSC 2/4/8/12 MHz typ. OSC3 24MHz max. / OSC kHz typ. 40TQFP13-64pin 40 34WCSP-48 SPI 3 I 2 CI2CM 1 I 2 CI2CS 1 UART 2IrDA1.0 IR REMC 1 USI 2UART/SPI/I 2 C 16 T T16F 2 16 PWMT16A 4 CT 1 SWT 1 WDT 1 A/D 4max. 10 #RESET NMI 23 8 LVDD 1.65V 1.95V 1.65V 1.95V I/O HVDD 1.65V 5.5V 2.0V 5.5V 1.65V 5.5V AVDD 2.7V 5.5V Flash /VPP 7V/7.5V S1C17554/564 Technical Manual Seiko Epson Corporation 1-1
14 1 S1C17554 S1C V 5.5V 1.8V 3.3V 5.0V -40 C 85 C Typ LVDD = HVDD = 1.8V SLEEP HALT 0.8µA OSC1 = Off, OSC3 = Off 2.7µA OSC1 = 32kHz, OSC3 = Off 16µA OSC1 = 32kHz, OSC3 = Off 3000µA OSC1 = Off, OSC3 = 8MHz 1.2µA OSC1 = Off, IOSC = Off, OSC3 = Off 3.1µA OSC1 = 32kHz, IOSC = Off, OSC3 = Off 16µA OSC1 = 32kHz, IOSC = Off, OSC3 = Off 3000µA OSC1 = Off, IOSC = Off, OSC3 = 8MHz 4500µA OSC1 = Off, IOSC = 12MHz, OSC3 = Off A/D 380µA AVDD = 3.6V, 100kHz, FSEL[1:0] =, XPD[1:0] = 1 TQFP13-64pin 10mm 10mm 1.0mm, : 0.5mm mm 3.137mm, : 140µm 3 WCSP mm 3.137mm 0.72mm, : 0.4mm 1-2 Seiko Epson Corporation S1C17554/564 Technical Manual
15 1 1.2 S1C17554 CPU Core S1C17 DCLK, DST2, DSIO 32 bits Internal RAM (16K bytes) 8/16 bits I/O 2 (0x5000 ) Flash memory (128K bytes) 16 bits TEST Test circuit A/D converter AVDD AINx, #ADTRG #RESET Reset circuit I/O 1 (0x4000 ) 8/16 bits Interrupt system MISC register Clock generator (with oscillators) OSC1 2, OSC3 4 FOUTA, FOUTB Interrupt controller Clock timer 16-bit timer (3 ch.) Stopwatch timer Fine mode 16-bit timer (2 ch.) Watchdog timer SINx, SOUTx, SCLKx UART (2 ch.) 16-bit PWM timer (4 ch.) EXCLx, CAPx, TOUTx SDIx, SDOx, SPICLKx, #SPISSx SPI (3 ch.) IR remote controller REMI, REMO SDA0, SCL0 I 2 C master SDA1, SCL1, #BFR I 2 C slave I/O port/ port MUX Pxx S1C17554 S1C17554/564 Technical Manual Seiko Epson Corporation 1-3
16 1 S1C17564 CPU Core S1C17 DCLK, DST2, DSIO 32 bits Internal RAM (16K bytes) 8/16 bits I/O 2 (0x5000 ) TEST Flash memory (128K bytes) Test circuit 16 bits Regulator A/D converter VIN, VOUT, REGEN AVDD AINx, #ADTRG #RESET Reset circuit I/O 1 (0x4000 ) 8/16 bits Interrupt system MISC register Clock generator (with oscillators) OSC1 2, OSC3 4 FOUTA, FOUTB Interrupt controller Clock timer 16-bit timer (3 ch.) Stopwatch timer Fine mode 16-bit timer (2 ch.) Watchdog timer SINx, SOUTx, SCLKx UART (2 ch.) 16-bit PWM timer (4 ch.) EXCLx, CAPx, TOUTx SDIx, SDOx, SPICLKx, #SPISSx SPI (3 ch.) IR remote controller REMI, REMO SDA0, SCL0 I 2 C master USI (2 ch.) US_SDIx, US_SDOx, US_SCKx, US_SSIx SDA1, SCL1, #BFR I 2 C slave I/O port/ port MUX Pxx S1C Seiko Epson Corporation S1C17554/564 Technical Manual
17 S1C17554 WCSP-48 S1C17554 A1 Corner Top View Bottom View A1 Corner A A B Index B C C D D E E F F G G Top View A B P10 SDI0 P01 AIN1 1 P11 SDO0 P00 AIN P13 #SPISS0 TOUT5 CAP5 P12 SPICLK0 P14 SIN1 SDI1 P15 SOUT1 SDO1 P43 SDA1 REMI P44 SCL1 REMO P24 (EXCL3) SDO2 P25 #BFR #SPISS2 P26 SDA1 P27 SCL1 C P03 AIN3 P02 AIN2 HVDD P16 SCLK1 SPICLK1 VSS P30 TOUT0 CAP0 D E F G P17 SCL0 P45 (EXCL0) SDA0 P40 SIN0 TOUT6 CAP6 #RESET P32 TOUT4 CAP4 FOUTA P42 SCLK0 TOUT1 CAP1 LVDD P23 (EXCL2) SDI2 AVDD P41 SOUT0 TOUT7 CAP7 P22 (EXCL1) FOUTB P21 TOUT3 CAP3 VSS HVDD P20 TOUT2 CAP2 OSC4 LVDD DCLK P35 VPP OSC3 P31 #BFR #ADTRG TEST P34 REMO #SPISS1 OSC2 DST2 P37 DSIO P36 P33 REMI SPICLK2 OSC S1C17554 WCSP-48 S1C17554/564 Technical Manual Seiko Epson Corporation 1-5
18 1 1-6 Seiko Epson Corporation S1C17554/564 Technical Manual TQFP13-64pin S1C P50 SDI0/P10 VSS SDO0/P11 SPICLK0/P12 #SPISS0/TOUT5/CAP5/P13 LVDD HVDD SIN1/SDI1/P14 P51 SOUT1/SDO1/P15 SCLK1/SPICLK1/P16 SDA1/REMI/P43 SCL1/REMO/P44 SDO2/P24(EXCL3) #BFR/#SPISS2/P25 VSS VSS HVDD LVDD P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P20/TOUT2/CAP2 HVDD OSC4 OSC3 VPP OSC2 OSC1 VSS P P54 P34/REMO/#SPISS1 P33/REMI/SPICLK2 DCLK/P35 TEST DSIO/P36 DST2/P37 P31/#BFR/#ADTRG P53 LVDD P30/TOUT0/CAP0 HVDD VSS P27/SCL1 P26/SDA1 P52 #RESET LVDD SIN0/TOUT6/CAP6/P40 SOUT0/TOUT7/CAP7/P41 SCLK0/TOUT1/CAP1/P42 SDA0/P45(EXCL0) HVDD VSS SCL0/P17 TOUT4/CAP4/FOUTA/P32 N.C. AVDD AIN3/P03 AIN2/P02 AIN1/P01 AIN0/P S1C17554 TQFP13-64pin
19 1 S1C17554 Y X (0, 0) P50 SDI0/P10 VSS SDO0/P11 SPICLK0/P12 #SPISS0/TOUT5/CAP5/P13 LVDD HVDD SIN1/SDI1/P14 P51 SOUT1/SDO1/P15 SCLK1/SPICLK1/P16 SDA1/REMI/P43 SCL1/REMO/P mm HVDD SDO2/P24(EXCL3) #BFR/#SPISS2/P25 VSS N.C. VSS N.C. N.C. LVDD P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P20/TOUT2/CAP2 HVDD OSC4 VSS OSC3 VPP OSC2 OSC1 VSS P55 #RESET LVDD SIN0/TOUT6/CAP6/P40 SOUT0/TOUT7/CAP7/P41 SCLK0/TOUT1/CAP1/P42 SDA0/P45(EXCL0) P54 P34/REMO/#SPISS1 P33/REMI/SPICLK2 DCLK/P35 TEST DSIO/P36 HVDD VSS SCL0/P17 TOUT4/CAP4/FOUTA/P32 N.C. AVDD LVDD DST2/P37 P31/#BFR/#ADTRG P53 LVDD P30/TOUT0/CAP0 AVDD AIN3/P03 AIN2/P02 AIN1/P01 AIN0/P00 N.C Die No. CJ554D0B HVDD VSS VSS P27/SCL1 P26/SDA1 P X = 3.137mm, Y = 3.137mm No. 1 18, 37 54: X = 122µm, Y = 85µm No , 55 72: X = 85µm, Y = 122µm 400µm 3.137mm S1C17554 S1C17554/564 Technical Manual Seiko Epson Corporation 1-7
20 S1C17554 No. X (mm) Y (mm) No. X (mm) Y (mm) 1 P P P10/SDI VSS VSS OSC P11/SDO OSC P12/SPICLK VPP P13/#SPISS0/TOUT5/CAP OSC LVDD VSS HVDD OSC P14/SIN1/SDI HVDD P P20/TOUT2/CAP P15/SOUT1/SDO P21/TOUT3/CAP P16/SCLK1/SPICLK P22(EXCL1)/FOUTB P43/SDA1/REMI P23(EXCL2)/SDI P44/SCL1/REMO LVDD HVDD N.C P24(EXCL3)/SDO N.C P25/#BFR/SPISS VSS VSS N.C P #RESET P26/SDA LVDD P27/SCL P40/SIN0/TOUT6/CAP VSS P41/SOUT0/TOUT7/CAP VSS P42/SCLK0/TOUT1/CAP HVDD P45(EXCL0)/SDA P30/TOUT0/CAP HVDD LVDD VSS P P17/SCL P31/#BFR/ADTRG P32/TOUT4/CAP4/FOUTA DST2/P N.C LVDD AVDD DSIO/P AVDD TEST P03/AIN DCLK/P P02/AIN P33/REMI/SPICLK P01/AIN P34/REMO/#SPISS P00/AIN P N.C Seiko Epson Corporation S1C17554/564 Technical Manual
21 1 S1C17554/564 Technical Manual Seiko Epson Corporation 1-9 S1C TQFP13-64pin S1C US_SDI0/P50 SDI0/P10 VSS SDO0/P11 SPICLK0/P12 #SPISS0/TOUT5/CAP5/P13 LVDD HVDD SIN1/SDI1/P14 US_SDO0/P51 SOUT1/SDO1/P15 SCLK1/SPICLK1/P16 SDA1/REMI/P43 SCL1/REMO/P44 SDO2/P24(EXCL3) #BFR/#SPISS2/P25 REGEN VSS VIN VOUT P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P20/TOUT2/CAP2 HVDD OSC4 OSC3 VPP OSC2 OSC1 VSS P55/US_SCK P54/US_SDO1 P34/REMO/#SPISS1 P33/REMI/SPICLK2 DCLK/P35 TEST DSIO/P36 DST2/P37 P31/#BFR/#ADTRG P53/US_SDI1 LVDD P30/TOUT0/CAP0 HVDD VSS P27/SCL1 P26/SDA1 P52/US_SCK0 #RESET LVDD SIN0/TOUT6/CAP6/P40 SOUT0/TOUT7/CAP7/P41 SCLK0/TOUT1/CAP1/P42 SDA0/P45(EXCL0) HVDD VSS SCL0/P17 TOUT4/CAP4/FOUTA/P32 N.C. AVDD AIN3/US_SSI1/P03 AIN2/US_SSI0/P02 AIN1/P01 AIN0/P S1C17564 TQFP13-64pin
22 1 S1C17564 Y X (0, 0) US_SDI0/P50 SDI0/P10 VSS SDO0/P11 SPICLK0/P12 #SPISS0/TOUT5/CAP5/P13 LVDD 3.137mm HVDD SIN1/SDI1/P14 US_SDO0/P51 SOUT1/SDO1/P15 SCLK1/SPICLK1/P16 SDA1/REMI/P43 SCL1/REMO/P44 HVDD SDO2/P24(EXCL3) #BFR/#SPISS2/P25 VSS REGEN VSS VIN VOUT LVDD P23(EXCL2)/SDI2 P22(EXCL1)/FOUTB P21/TOUT3/CAP3 P20/TOUT2/CAP2 HVDD OSC4 VSS OSC3 VPP OSC2 OSC1 VSS P55/US_SCK1 #RESET LVDD SIN0/TOUT6/CAP6/P40 SOUT0/TOUT7/CAP7/P41 SCLK0/TOUT1/CAP1/P42 SDA0/P45(EXCL0) P54/US_SDO1 P34/REMO/#SPISS1 P33/REMI/SPICLK2 DCLK/P35 TEST DSIO/P36 HVDD VSS SCL0/P17 TOUT4/CAP4/FOUTA/P32 N.C. AVDD LVDD DST2/P37 P31/#BFR/#ADTRG P53/US_SDI1 LVDD P30/TOUT0/CAP0 AVDD AIN3/US_SSI1/P03 AIN2/US_SSI0/P02 AIN1/P01 AIN0/P00 N.C Die No. CJ554D0B HVDD HVDD VSS P27/SCL1 P26/SDA1 P52/US_SCK X = 3.137mm, Y = 3.137mm No. 1 18, 37 54: X = 122µm, Y = 85µm No , 55 72: X = 85µm, Y = 122µm 400µm 3.137mm S1C Seiko Epson Corporation S1C17554/564 Technical Manual
23 S1C17564 No. X (mm) Y (mm) No. X (mm) Y (mm) 1 P50/US_SDI P55/US_SCK P10/SDI VSS VSS OSC P11/SDO OSC P12/SPICLK VPP P13/#SPISS0/TOUT5/CAP OSC LVDD VSS HVDD OSC P14/SIN1/SDI HVDD P51/US_SDO P20/TOUT2/CAP P15/SOUT1/SDO P21/TOUT3/CAP P16/SCLK1/SPICLK P22(EXCL1)/FOUTB P43/SDA1/REMI P23(EXCL2)/SDI P44/SCL1/REMO LVDD HVDD VOUT P24(EXCL3)/SDO VIN P25/#BFR/SPISS VSS VSS REGEN P52/US_SCK #RESET P26/SDA LVDD P27/SCL P40/SIN0/TOUT6/CAP VSS P41/SOUT0/TOUT7/CAP HVDD P42/SCLK0/TOUT1/CAP HVDD P45(EXCL0)/SDA P30/TOUT0/CAP HVDD LVDD VSS P53/US_SDI P17/SCL P31/#BFR/ADTRG P32/TOUT4/CAP4/FOUTA DST2/P N.C LVDD AVDD DSIO/P AVDD TEST P03/AIN3/US_SSI DCLK/P P02/AIN2/US_SSI P33/REMI/SPICLK P01/AIN P34/REMO/#SPISS P00/AIN P54/US_SDO N.C S1C17554/564 Technical Manual Seiko Epson Corporation 1-11
24 : I/O HVDD I/O V LVDD V VSS GND / S1C17554 S1C17564 WCSP TQFP/ TQFP/ VPP Flash / 7/7.5V AVDD V VIN V VOUT 1.8V REGEN I I OSC3 I I OSC3 / LVDD OSC4 O O OSC3 OSC1 I I OSC1 / LVDD OSC2 O O OSC1 #RESET I I Pull-up TEST I I Pull-down VSS P00 I/O I Pull-up AIN0 I A/D Ch.0 P01 I/O I Pull-up AIN1 I A/D Ch.1 P02 I/O I Pull-up AIN2 I A/D Ch.2 US_SSI0 I/O USI Ch.0S1C17564 P03 I/O I Pull-up AIN3 I A/D Ch.3 US_SSI1 I/O USI Ch.1S1C17564 P10 I/O I Pull-up SDI0 I SPI Ch.0 P11 I/O I Pull-up SDO0 O SPI Ch.0 P12 I/O I Pull-up SPICLK0 I/O SPI Ch.0 P13 I/O I Pull-up #SPISS0 I SPI Ch.0 TOUT5 O T16A Ch.2 TOUT B CAP5 I T16A Ch.2 B P14 I/O I Pull-up SIN1 I UART Ch.1 SDI1 I SPI Ch.1 P15 I/O I Pull-up SOUT1 O UART Ch.1 SDO1 O SPI Ch.1 P16 I/O I Pull-up SCLK1 I UART Ch.1 SPICLK1 I/O SPI Ch.1 P17 I/O I Pull-up SCL0 I/O I 2 C SCL P20 I/O I Pull-up TOUT2 O T16A Ch.1 TOUT A CAP2 I T16A Ch.1 A P21 I/O I Pull-up TOUT3 O T16A Ch.1 TOUT B CAP3 I T16A Ch.1 B P22 (EXCL1) I/O I Pull-up T16A Ch.1 FOUTB O P23 (EXCL2) I/O I Pull-up T16A Ch.2 SDI2 I SPI Ch.2 P24 (EXCL3) I/O I Pull-up T16A Ch.3 SDO2 O SPI Ch Seiko Epson Corporation S1C17554/564 Technical Manual
25 1 / S1C17554 S1C17564 I/O TQFP/ TQFP/ WCSP P25 I/O I Pull-up #BFR I I 2 C #SPISS2 I SPI Ch.2 P26 I/O I Pull-up SDA1 I/O I 2 C P27 I/O I Pull-up SCL1 I/O I 2 CSCL P30 I/O I Pull-up TOUT0 O T16A Ch.0 TOUT A CAP0 I T16A Ch.0 A P31 I/O I Pull-up #BFR I I 2 C #ADTRG I A/D P32 I/O I Pull-up TOUT4 O T16A Ch.2 TOUT A CAP4 I T16A Ch.2 A FOUTA O P33 I/O I Pull-up REMI I REMC SPICLK2 I/O SPI Ch.2 P34 I/O I Pull-up REMO O REMC #SPISS1 I SPI Ch.1 DCLK O O H P35 I/O DSIO I/O I Pull-up P36 I/O DST2 O O L P37 I/O P40 I/O I Pull-up SIN0 I UART Ch.0 TOUT6 O T16A Ch.3 TOUT A CAP6 I T16A Ch.3 A P41 I/O I Pull-up SOUT0 O UART Ch.0 TOUT7 O T16A Ch.3 TOUT B CAP7 I T16A Ch.3 B P42 I/O I Pull-up SCLK0 I UART Ch.0 TOUT1 O T16A Ch.0 TOUT B CAP1 I T16A Ch.0 B P43 I/O I Pull-up SDA1 I/O I 2 C REMI I REMC P44 I/O I Pull-up SCL1 I/O I 2 CSCL REMO O REMC P45 (EXCL0) I/O I Pull-up T16A Ch.0 SDA0 I/O I 2 C P50 I/O I Pull-up US_SDI0 I/O USI Ch.0S1C17564 P51 I/O I Pull-up US_SDO0 O USI Ch.0 S1C17564 P52 I/O I Pull-up US_SCK0 I/O USI Ch.0S1C17564 P53 I/O I Pull-up US_SDI1 I/O USI Ch.1S1C17564 P54 I/O I Pull-up US_SDO1 O USI Ch.1 S1C17564 P55 I/O I Pull-up US_SCK1 I/O USI Ch.1S1C17564 S1C17554/564 Technical Manual Seiko Epson Corporation 1-13
26 2 CPU 2 CPU S1C17554/564 S1C17 S1C17 16 RISC 18 CPU S1C17 S1C17 Family S1C S1C17 16 RISC µm CMOS C , 16M NMI 32 HALT halt SLEEP slp S1C17554/564 Technical Manual Seiko Epson Corporation 2-1
27 2 CPU 2.2 CPU S1C PC 7 SP 6 PSR IL[2:0] IE C V Z N R7 R6 R5 R4 R3 R2 R1 R S1C S1C17 Family S1C S1C17 ld.b %rd,%rs ( ) () %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs ( ) () ( ) () ( ) () ( ) ( ) [imm7],%rs ( ) ld.ub %rd,%rs ( ) () %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] ( ) () ( ) () %rd,[imm7] ( ) () ld %rd,%rs (16 ) %rd,sign7 () %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs (16 ) (16 ) (16 ) (16 ) (16 ) [imm7],%rs (16 ) ld.a %rd,%rs (24 ) %rd,imm7 () 2-2 Seiko Epson Corporation S1C17554/564 Technical Manual
28 2 CPU ld.a %rd,[%rb] (32 ) (*1) %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] (32 ) (*1) %rd,[imm7] (32 ) (*1) [%rb],%rs (32 ) (*1) [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs (32 ) (*1) [imm7],%rs (32 ) (*1) %rd,%sp SP %rd,%pc PC %rd,[%sp] (32 ) (*1) %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp] [%sp],%rs (32 ) (*1) [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs (24 ) SP %sp,imm7 SP add %rd,%rs 16 add/c add/nc add %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 add.a %rd,%rs 24 add.a/c add.a/nc add.a %sp,%rs (/c: C = 1, /nc: C = 0 ) SP 24 %rd,imm7 24 %sp,imm7 SP24 adc %rd,%rs 16 adc/c adc/nc adc %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 sub %rd,%rs 16 sub/c sub/nc sub %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 sub.a %rd,%rs 24 sub.a/c sub.a/nc sub.a %sp,%rs (/c: C = 1, /nc: C = 0 ) SP 24 %rd,imm7 24 %sp,imm7 SP24 sbc %rd,%rs 16 sbc/c sbc/nc sbc %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 cmp %rd,%rs 16 cmp/c cmp/nc cmp %rd,sign7 (/c: C = 1, /nc: C = 0 ) 16 cmp.a %rd,%rs 24 cmp.a/c cmp.a/nc cmp.a %rd,imm7 (/c: C = 1, /nc: C = 0 ) 24 cmc %rd,%rs 16 cmc/c cmc/nc cmc %rd,sign7 (/c: C = 1, /nc: C = 0 ) 16 S1C17554/564 Technical Manual Seiko Epson Corporation 2-3
29 2 CPU and %rd,%rs and/c and/nc and %rd,sign7 (/c: C = 1, /nc: C = 0 ) or %rd,%rs or/c or/nc or %rd,sign7 (/c: C = 1, /nc: C = 0 ) xor %rd,%rs xor/c xor/nc xor %rd,sign7 (/c: C = 1, /nc: C = 0 ) not %rd,%rs (1 ) not/c not/nc not %rd,sign7 (/c: C = 1, /nc: C = 0 ) (1 ) & sr %rd,%rs ( ) %rd,imm7 () sa %rd,%rs ( ) %rd,imm7 () sl %rd,%rs ( ) %rd,imm7 () swap %rd,%rs 16 ext imm13 cv.ab %rd,%rs 8 24 cv.as %rd,%rs cv.al %rd,%rs cv.la %rd,%rs cv.ls %rd,%rs jpr sign10 PC jpr.d %rb jpa imm7 jpa.d %rb jrgt jrgt.d sign7 PC :!Z &!(N ^ V) jrge jrge.d sign7 PC :!(N ^ V) jrlt jrlt.d sign7 PC : N ^ V jrle jrle.d sign7 PC : Z N ^ V jrugt jrugt.d sign7 PC :!Z &!C jruge jruge.d sign7 PC :!C jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d sign7 PC : C sign7 PC : Z C sign7 PC : Z sign7 PC :!Z sign10 PC %rb imm7 %rb int imm5 intl imm5,imm3 reti reti.d brk 2-4 Seiko Epson Corporation S1C17554/564 Technical Manual
30 2 CPU retd nop halt HALT slp SLEEP ei di ld.cw %rd,%rs %rd,imm7 ld.ca %rd,%rs %rd,imm7 ld.cf %rd,%rs %rd,imm7 *1 ld.a %rs %rd [%rb] [%rb]+ [%rb]- -[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]- -[%sp] imm3,imm5,imm7,imm13 sign7,sign PSR ( ) () () ( ) () () ( ) ( ) S1C17554/564 S1C17 PSR Processor Status MISC_PSR PSR PSR PSR (MISC_PSR) name Address Bit Name Function Setting Init. R/W Remarks PSR (MISC_PSR) 0x532c (16 bits) D when being read. D7 5 PSRIL[2:0] PSR interrupt level (IL) bits to 0x7 R D4 PSRIE PSR interrupt enable (IE) bit 1 1 (enable) 0 0 (disable) 0 R D3 PSRC PSR carry (C) flag 1 1 (set) 0 0 (cleared) 0 R D2 PSRV PSR overflow (V) flag 1 1 (set) 0 0 (cleared) 0 R D1 PSRZ PSR zero (Z) flag 1 1 (set) 0 0 (cleared) 0 R D0 PSRN PSR negative (N) flag 1 1 (set) 0 0 (cleared) 0 R D[15:8] D[7:5] D4 Reserved PSRIL[2:0]: PSR Interrupt Level (IL) Bits PSR IL : PSRIE: PSR Interrupt Enable (IE) Bit PSR IE 1 R : 1 0 R : 0 S1C17554/564 Technical Manual Seiko Epson Corporation 2-5
31 2 CPU D3 D2 D1 D0 PSRC: PSR Carry (C) Flag Bit PSR C 1 R : 1 0 R : 0 PSRV: PSR Overflow (V) Flag Bit PSR V 1 R : 1 0 R : 0 PSRZ: PSR Zero (Z) Flag Bit PSR Z 1 R : 1 0 R : 0 PSRN: PSR Negative (N) Flag Bit PSR N 1 R : 1 0 R : S1C17554/564 IDIR CPU Processor ID (IDIR) name Address Bit Name Function Setting Init. R/W Remarks Processor ID (IDIR) 0xffff84 D7 0 IDIR[7:0] Processor ID 0: S1C17 Core 0 0 R ID S1C17 ID Seiko Epson Corporation S1C17554/564 Technical Manual
32 3, 3, 3.1 S1C17554/564 0xff ffff 0xff fc00 0xff fbff fff fff fff fff ff fff 0 3fc I/O (1K ) Flash (128K ) ( : 16 ) 2 (4K ) 1 (1K ) RAM (64 ) RAM (16K ) ( : 32 ) 0x5500 0x5fff 0x5480 0x54ff Flash 0x5400 0x547f 16 PWM Ch.0 3 0x53a0 0x53ff 0x5380 0x539f A/D 0x5360 0x537f 0x5340 0x535f IR 0x5320 0x533f MISC 0x52c0 0x531f 0x52a0 0x52bf MUX 0x5280 0x529f 0x5200 0x527f P 0x5140 0x51ff 0x5120 0x513f (S1C17564) 0x5100 0x511f 0x50c0 0x50ff USI Ch.0 1(S1C17564) 0x50a0 0x50bf 0x5060 0x509f 0x5040 0x505f 0x5020 0x503f 0x5000 0x501f 0x43c0 0x43ff 0x4380 0x43bf 0x4360 0x437f 0x4340 0x435f 0x4320 0x433f 0x42e0 0x431f 0x4280 0x42df 0x4220 0x427f 0x4200 0x421f 0x4140 0x41ff 0x4100 0x413f 0x4040 0x40ff 0x4020 0x403f 0x4000 0x401f 3.1 S1C17554/564 SPI Ch.1 2 I 2 C I 2 C SPI Ch.0 16 Ch.1 16 Ch Ch.0 UART Ch.0 1 MISC ( ) (16 ) (16 ) (16 ) (16 ) (16 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (8 ) (8 ) 3.1 CPU CLG Flash1 Flash/ : 1 = 1 Flash : 1 = 1 3 Flash : 1 = 2 4 CPU S1C17554/564 Technical Manual Seiko Epson Corporation 3-1
33 3, CPU * * * 1 * 32 8 S1C PSR / S1C Flash Flash RAM RAM Flash Flash 0x80007fff128K Flash4K 32 0x8000 ITC MISC_TTBRL/MISC_TTBRH Flash S1C17554/564 FlashICDmini / Flash2 16K 000 CPU Seiko Epson Corporation S1C17554/564 Technical Manual
34 3, Flash Protect Bits Address Bit Function Setting Init. R/W Remarks 7ffc (16 bits) 7ffe (16 bits) D15 8 D7 1 1 R/W Always set to 1. D6 Flash write-protect bit for fff 1 Writable 0 Protected 1 R/W D5 Flash write-protect bit for c000 ffff 1 Writable 0 Protected 1 R/W D4 Flash write-protect bit for 8000 bfff 1 Writable 0 Protected 1 R/W D3 Flash write-protect bit for fff 1 Writable 0 Protected 1 R/W D2 Flash write-protect bit for fff 1 Writable 0 Protected 1 R/W D1 Flash write-protect bit for 0xc000 0xffff 1 Writable 0 Protected 1 R/W D0 Flash write-protect bit for 0x8000 0xbfff 1 Writable 0 Protected 1 R/W D15 8 D7 Flash data-read-protect bit for fff 1 Readable 0 Protected 1 R/W D6 Flash data-read-protect bit for fff 1 Readable 0 Protected 1 R/W D5 Flash data-read-protect bit for c000 ffff 1 Readable 0 Protected 1 R/W D4 Flash data-read-protect bit for 8000 bfff 1 Readable 0 Protected 1 R/W D3 Flash data-read-protect bit for fff 1 Readable 0 Protected 1 R/W D2 Flash data-read-protect bit for fff 1 Readable 0 Protected 1 R/W D1 Flash data-read-protect bit for 0xc000 0xffff 1 Readable 0 Protected 1 R/W D0 1 1 R/W Always set to 1. : data.rodata 7ffe D0 10 Flash Flash RDWAIT[1:0]/FLASHC_WAIT FLASHC Read Wait Control (FLASHC_WAIT) name Address Bit Name Function Setting Init. R/W Remarks FLASHC Read 0x54b0 D when being read. Wait Control (FLASHC_ WAIT) (16 bits) D1 0 RDWAIT [1:0] Flash read wait cycle RDWAIT[1:0] Wait R/W 2 wait 1 wait No wait D[1:0] RDWAIT[1:0]: Flash Read Wait Cycle Bits Flash 11 no wait : 1 = 1 : 1 = 2 : 3.3 RAM RAM fff16k RAM RAM S1C17554/564 Technical Manual Seiko Epson Corporation 3-3
35 3, : RAM64fc0 fff S1C17554/564 RAM16KB 12KB 8KB 4KB 2KB 1KB 512 S1C17554/564 ROMRAM RAM IRAMSZ[2:0]/MISC_IRAMSZ IRAM Size (MISC_IRAMSZ) name Address Bit Name Function Setting Init. R/W Remarks IRAM Size 0x5326 (16 bits) (MISC_IRAMSZ) D when being read. D8 DBADR Debug base address select 1 0 0xfffc00 0 R/W D7 0 when being read. D6 4 IRAMACTSZ IRAM actual size 0x6 (= 16KB) 0x6 R [2:0] D3 0 when being read. D2 0 IRAMSZ[2:0] IRAM size select IRAMSZ[2:0] Size 0x6 R/W 0x7 0x6 0x5 0x4 16KB 512B 1KB 2KB 4KB 8KB 12KB D[6:4] D[2:0] IRAMACTSZ[2:0]: IRAM Actual Size Bits RAM : 0x6 IRAMSZ[2:0]: IRAM Size Select Bits RAM RAM IRAMSZ[2:0] 0x7 0x6 0x5 0x4 RAM Reserved 16KB 512B 1KB 2KB 4KB 8KB 12KB : 0x6 : MISC_IRAMSZ MISC_PROT0x96 MISC_IRAMSZ MISC_PROT0x x4000 1K0x5000 4K I/O Appendix I/O 3-4 Seiko Epson Corporation S1C17554/564 Technical Manual
36 3, x4000~ 0x I/O MISCMISC, 8 UART UART, 8 16 T16F, T16, 16 ITC, 16 SPI SPI, 16 I 2 CI2CM, 16 I 2 CI2CS, x5000~ 0x I/O CT, 8 SWT, 8 WDT, 8 CLG, 8 USI, 8 S1C17564 VD1, 8 S1C17564 & MUX P, 8 MISCMISC, 16 IR REMC, 16 A/DADC10, PWMT16A, 16 Flash FLASHC, S1C17 I/O 0xfffc00 0xffffff 1KCPU I/OI/O I/OS1C17 I/O S1C17 I/O 0xffff84 IDIR Processor ID ID 0xffff90 DBRAM Debug RAM Base RAM 0xffffa0 DCR Debug Control 0xffffb4 IBAR1 Instruction Break Address 1 #1 0xffffb8 IBAR2 Instruction Break Address 2 #2 0xffffbc IBAR3 Instruction Break Address 3 #3 0xffffd0 IBAR4 Instruction Break Address 4 #4 IDIR CPU DBG S1C17 S1C17 S1C17554/564 Technical Manual Seiko Epson Corporation 3-5
37 LV DD CPULVDD VSS VSS GND LVDD LVDD = 1.65V 1.95V VSS = GND LVDD VSS + GND S1C V 3.3V 5V 1.8VLVDD 4.2 I/OHVDD HVDD VSS GND HVDD HVDD = 1.65V 5.5V VSS = GND HVDD : OSC3 OSC1 LVDD P00 P03 AIN0 AIN3AVDD AVDD A/D HVDD AVDD VSS GND AVDD AVDD = 2.7V 5.5V VSS = GND AVDD = 1.65V 5.5V VSS = GND A/D A/D : A/D AVDD HVDD 1.65V AVDD HVDD P00 P03 AIN0 AIN3AVDDA/DP00 P03 A/D A/D 4.4 Flash VPP Flash /Flash /VSS GND VPP VPP = 7V VSS = GND VPP = 7.5V VSS = GND : VPP S1C17554/564 Technical Manual Seiko Epson Corporation 4-1
38 4 4.5 S1C17564 S1C V VIN : 2.0V 5.5V VOUT : 1.8V VIN HVDD AVDD REGEN1.8V Typ. VOUTLVDD 32kHz HALT SLEEP 4.6 S1C x5121 VD1_CTL VD1 Control S1C17564 : Reserved 0 1 VD1 Control (VD1_CTL) name Address Bit Name Function Setting Init. R/W Remarks VD1 Control 0x5121 D7 2 0 when being read. (VD1_CTL) D1 0 VD1ECO [1:0] Regulator operation mode select VD1ECO[1:0] Mode R/W S1C17564 Auto-control Economy Normal D[7:2] D[1:0] Reserved VD1ECO[1:0]: Regulator Operation Mode Select Bits VD1ECO[1:0] Reserved : OSC1VD1ECO[1:0] VD1ECO[1:0] slp VD1ECO[1:0] IOSC OSC3 SLEEP OSC1 OSC1 4-2 Seiko Epson Corporation S1C17554/564 Technical Manual
39 4 4.7 : LVDD HVDD I/O, AVDD A/D LVDD, HVDD I/O, AVDD A/D : HVDD : HVDD I/O, AVDD A/D LVDD HVDD I/O, AVDD A/D, LVDD : LVDDHVDDI/O LVDD 1 LVDD HVDD AVDD 1 HVDD AVDD CMOS CMOS IC PNPN HVDD VSS HVDD HVDD VSS 1 VSS 2 3 HVDD AVDD VSS 4 S1C17554/564 Technical Manual Seiko Epson Corporation 4-3
40 S1C17554/ #RESET 2 P0P00 P #RESET P00 P01 P02 P03 P0 ( ) WDT CPU CPU #RESET #RESET Low S1C17554/564 #RESETLow AC #RESET Low HighCPU #RESET P0 P00 P03Low P : P S1C17554/564 CPU 4 CPU NMI WDTMD/WDT_ST1 WDTMD 0 NMI WDT S1C17554/564 Technical Manual Seiko Epson Corporation 5-1
41 5 : #RESET * 8 Flash16 CPU CPUOSC3 IOSC S1C17564 * : SLEEP OSC3/IOSC(*) #RESET (*) (8) Flash (16) * S1C17554: OSC3 1,024OSC3 S1C17564: IOSC64IOSC 5.3 CPU R0 R7: PSR: = 0 SP: PC: RAM Appendix I/O 5-2 Seiko Epson Corporation S1C17554/564 Technical Manual
42 6 ITC 6 ITC 6.1 ITC ITC S1C17 ITC P00 P P10 P P20 P P30 P P40 P P50 P55 6 * S1C17554 WCSP PWM Ch PWM Ch PWM Ch PWM Ch Ch.0&Ch Ch Ch Ch USI Ch.0&Ch.16 * S1C UART Ch UART Ch IR3 21. SPI Ch SPI Ch SPI Ch I 2 C I 2 C3 26. A/D 2 8 ITC / S1C17554/564 Technical Manual Seiko Epson Corporation 6-1
43 6 ITC S1C17 1 n 1 n NMI S1C S1C17554/ No./ No. 0 (0) TTBR + 0 #RESETLow 1 *2 1 (1) TTBR (0xfffc00) brk 3 2 (2) TTBR + 8 NMI *2 4 3 (3) TTBR + c C 4 (4) TTBR + 0 P0 P00~P03 *1 5 (5) TTBR + 4 P1 P10~P17 6 (6) TTBR Hz 10Hz 1Hz 7 (7) TTBR + c 32Hz 8Hz 2Hz 1Hz 8 (8) TTBR PWM Ch.2 A/B A/B A/B 9 (9) TTBR + 4 P4 P40~P45 10 (a) TTBR + 8 SPI Ch.2 11 (b) TTBR + c 16 PWM Ch.0 A/B A/B A/B 12 (c) TTBR Ch.0&Ch.1 USI Ch.0&Ch.1 Ch.0 Ch.1 Ch.0 Ch.0 Ch.0 Ch.1 Ch.1 Ch.1 13 (d) TTBR Ch Seiko Epson Corporation S1C17554/564 Technical Manual
44 6 ITC No./ No. 14 (e) TTBR Ch.1 15 (f) TTBR + c 16 Ch.2 16 PWM Ch.3 A/B A/B A/B 16 (0) TTBR + 0x40 UART Ch.0 17 (1) TTBR + 0x44 UART Ch.1 18 (2) TTBR + 0x48 SPI Ch.0 19 (3) TTBR + 0x4c I 2 C 20 (4) TTBR + 0x50 IR SPI Ch.1 21 (5) TTBR + 0x54 16 PWM Ch.1 A/B A/B A/B 22 (6) TTBR + 0x58 A/D 23 (7) TTBR + 0x5c P5 P50~P55 24 (8) TTBR + 0x60 P2 P20~P27 25 (9) TTBR + 0x64 P3 P30~P37 26 (a) TTBR + 0x68 I 2 C 27 (b) TTBR + 0x6c : : : : 31 (f) TTBR + 0x7c *1 *1 *2 NMI 4 26 S1C17554/ : 16 Ch.0/Ch.1 USI Ch.0/Ch.1 15: 16 Ch.2 16 PWM Ch.3 20: IR SPI Ch.1 OR ITC MISC_TTBRL MISC_TTBRH TTBR MISC_TTBRL/MISC_TTBRH0x8000 MISC_TTBRL S1C17554/564 Technical Manual Seiko Epson Corporation 6-3
45 6 ITC Vector Table Address Low/High s (MISC_TTBRL, MISC_TTBRH) name Address Bit Name Function Setting Init. R/W Remarks Vector Table 0x5328 D15 8 TTBR[15:8] Vector table base address A[15:8] 0xff 0x80 R/W Address Low (MISC_TTBRL) (16 bits) D7 0 TTBR[7:0] Vector table base address A[7:0] (fixed at 0) R Vector Table Address High (MISC_TTBRH) 0x532a (16 bits) D when being read. D7 0 TTBR[23:16] Vector table base address A[23:16] 0xff R/W : MISC_TTBRL/MISC_TTBRH MISC_PROT0x96 MISC_TTBRL/MISC_TTBRH MISC_PROT0x ITCS1C17 0 1ITC : PSR reti ITC ITC S1C ITC S1C17 ILPSR S1C ITC 00S1C17 ITC 07 ITCITC S1C S1C17 ITCS1C17 S1C17 ITC 6-4 Seiko Epson Corporation S1C17554/564 Technical Manual
46 6 ITC P0 ILV0[2:0] D[2:0]/ITC_LV0 0x4306 P1 ILV1[2:0] D[10:8]/ITC_LV0 0x4306 ILV2[2:0] D[2:0]/ITC_LV1 0x4308 ILV3[2:0] D[10:8]/ITC_LV1 0x PWM Ch.2 ILV4[2:0] D[2:0]/ITC_LV2 0x430a P4 ILV5[2:0] D[10:8]/ITC_LV2 0x430a SPI Ch.2 ILV6[2:0] D[2:0]/ITC_LV3 0x430c 16 PWM Ch.0 ILV7[2:0] D[10:8]/ITC_LV3 0x430c 16 Ch.0 & Ch.1 / ILV8[2:0] D[2:0]/ITC_LV4 0x430e USI Ch.0 & Ch.1 16 Ch.0 ILV9[2:0] D[10:8]/ITC_LV4 0x430e 16 Ch.1 ILV10[2:0] D[2:0]/ITC_LV5 0x Ch.2 / ILV11[2:0] D[10:8]/ITC_LV5 0x PWM Ch.3 UART Ch.0 ILV12[2:0] D[2:0]/ITC_LV6 0x4312 UART Ch.1 ILV13[2:0] D[10:8]/ITC_LV6 0x4312 SPI Ch.0 ILV14[2:0] D[2:0]/ITC_LV7 0x4314 I 2 C ILV15[2:0] D[10:8]/ITC_LV7 0x4314 IR / SPI Ch.1 ILV16[2:0] D[2:0]/ITC_LV8 0x PWM Ch.1 ILV17[2:0] D[10:8]/ITC_LV8 0x4316 A/D ILV18[2:0] D[2:0]/ITC_LV9 0x4318 P5 ILV19[2:0] D[10:8]/ITC_LV9 0x4318 P2 ILV20[2:0] D[2:0]/ITC_LV10 0x431a P3 ILV21[2:0] D[10:8]/ITC_LV10 0x431a I 2 C ILV22[2:0] D[2:0]/ITC_LV11 0x431c S1C17 S1C17 PSR S1C17IE1 PSR IL NMI 1 S1C17 S1C17S1C17 1 PSR PC 2 PSR IE0 3 PSR ILNMI 4 PC 2 S1C17554/564 Technical Manual Seiko Epson Corporation 6-5
47 6 ITC IE1 3IL retipsr 6.4 NMI S1C17554/564NMI NMI S1C17 NMI WDT 6.5 S1C17 int imm5またはintl imm5,imm3 命 令 を 使 用 することによって imm50 31 intlimm3 PSR IL HALT, SLEEP HALT SLEEP CPU ITC CPU NMI : ITC CPU HALT SLEEP CPU halt slp ITC HALT SLEEP Appendix HALT SLEEP CLG ITC 0x4306 ITC_LV0 Interrupt Level Setup 0 P0 P1 0x4308 ITC_LV1 Interrupt Level Setup 1 SWT CT 0x430a ITC_LV2 Interrupt Level Setup 2 T16A Ch.2 P4 0x430c ITC_LV3 Interrupt Level Setup 3 SPI Ch.2 T16A Ch.0 0x430e ITC_LV4 Interrupt Level Setup 4 T16F Ch.0 & Ch.1/USI Ch.0 & Ch.1 T16 Ch.0 0x4310 ITC_LV5 Interrupt Level Setup 5 T16 Ch.1 T16 Ch.2/T16A Ch.3 0x4312 ITC_LV6 Interrupt Level Setup 6 UART Ch.0 Ch.1 0x4314 ITC_LV7 Interrupt Level Setup 7 SPI Ch.0 I2CM 0x4316 ITC_LV8 Interrupt Level Setup 8 REMC/SPI Ch.1 T16A Ch.1 0x4318 ITC_LV9 Interrupt Level Setup 9 ADC10 P5 0x431a ITC_LV10 Interrupt Level Setup 10 P2 P3 0x431c ITC_LV11 Interrupt Level Setup 11 I2CS ITC 16 : Reserved Seiko Epson Corporation S1C17554/564 Technical Manual
48 6 ITC Interrupt Level Setup x (ITC_LVx) name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4306 Setup x (ITC_LVx) 0x431c (16 bits) D[15:11], D[7:3] Reserved D when being read. D10 8 ILVn[2:0] INTn (1, 3,... 21) interrupt level 0 to 7 R/W D7 3 0 when being read. D2 0 ILVn[2:0] INTn (0, 2,... 22) interrupt level 0 to 7 R/W D[10:8], D[2:0] ILVn[2:0]: INTn Interrupt Level Bits (n = 0~22) 0 7: S1C17PSR IL ITC ITC ITC_LVx0x4306 0x431c S1C17 S1C17 ITCS1C17 S1C17 ITC ITC_LV0 0x4306 ILV0[2:0] D[2:0] P0 ILV1[2:0] D[10:8] P1 ITC_LV1 0x4308 ILV2[2:0] D[2:0] ILV3[2:0] D[10:8] ITC_LV2 0x430a ILV4[2:0] D[2:0] 16 PWM Ch.2 ILV5[2:0] D[10:8] P4 ITC_LV3 0x430c ILV6[2:0] D[2:0] SPI Ch.2 ILV7[2:0] D[10:8] 16 PWM Ch.0 ITC_LV4 0x430e ILV8[2:0] D[2:0] 16 Ch.0 & Ch.1 / USI Ch.0 & Ch.1 ILV9[2:0] D[10:8] 16 Ch.0 ITC_LV5 0x4310 ILV10[2:0] D[2:0] 16 Ch.1 ILV11[2:0] D[10:8] 16 Ch.2 / 16 PWM Ch.3 ITC_LV6 0x4312 ILV12[2:0] D[2:0] UART Ch.0 ILV13[2:0] D[10:8] UART Ch.1 ITC_LV7 0x4314 ILV14[2:0] D[2:0] SPI Ch.0 ILV15[2:0] D[10:8] I 2 C ITC_LV8 0x4316 ILV16[2:0] D[2:0] IR / SPI Ch.1 ILV17[2:0] D[10:8] 16 PWM Ch.1 ITC_LV9 0x4318 ILV18[2:0] D[2:0] A/D ILV19[2:0] D[10:8] P5 ITC_LV10 0x431a ILV20[2:0] D[2:0] P2 ILV21[2:0] D[10:8] P3 ITC_LV11 0x431c ILV22[2:0] D[2:0] I 2 C ILV23[2:0] D[10:8] Reserved S1C17554/564 Technical Manual Seiko Epson Corporation 6-7
49 7 CLG 7 CLG : IOSC S1C17564S1C17554 IOSC 7.1 CLG S1C17 CLG - IOSC: 2/4/8/12MHz typ. * - OSC3: 24MHz max. / - OSC1: kHz typ. IOSC* OSC3 OSC1 CPU CCLK CCLK 1/1 1/2 1/4 1/8 CPU RUN HALT SLEEP On/Off SLEEP SLEEP IOSC On IOSC* CLG * S1C17564 OSC3 OSC4 OSC1 OSC2 FOUTA FOUTB IOSC (2/4/8/12MHz) OSC3 (24MHz) OSC1 (32.768kHz) FOUTA FOUTB S1C17564 IOSC OSC3 IOSC OSC3 OSC1 OSC1 OSC SLEEP, wakeup (1/1~1/8) CLG HALT CCLK PCLK 256Hz S1C17,, CT/SWT/WDT ITC, T16, T16F, SPI, USI, I2CM, I2CS, UART, P, MISC, VD1, ADC, REMC CT, SWT, WDT T16A, UART CLG HALT SLEEP Appendix S1C17554/564 Technical Manual Seiko Epson Corporation 7-1
50 7 CLG 7.2 CLG CLG CLG I/O OSC1 I 1 OSC kHz OSC1 OSC2 O 1 OSC kHz OSC3 I 1 OSC3 max. 24MHz OSC3 OSC4 O 1 OSC3 max. 24MHz FOUTA O 1 FOUTA IOSC/OSC3OSC1 FOUTB O 1 FOUTB IOSC/OSC3OSC1 CLG FOUTA FOUTB CLG (P) 7.3 S1C17554 CLG 2 OSC3 OSC1 S1C17564 CLG 3 IOSC OSC3 OSC1OSC3IOSCS1C17 OSC1 S1C17554 OSC3 S1C17564 IOSC On/OffIOSC OSC3OSC IOSC OSC3 OSC1 S1C17554 S1C17564 OSC3 : On : Off : On : Off : Off OSC3 OSC OSC3 OSC3 OSC4X tal3 Ceramic Rf3 OSC3 OSC4 VSS 2 CG3 CD3 OSC4 LVDD 50% OSC3 IOSC 7-2 Seiko Epson Corporation S1C17554/564 Technical Manual
51 7 CLG VSS CG3 Rf3 CD3 OSC3 OSC4 X'tal3 or Ceramic (1) / OSC3EN SLEEP fosc3 OSC3WT[1:0] OSC3WCE LVDD VSS OSC3 N.C. OSC4 (2) OSC3 OSC3EN SLEEP fosc3 OSC3WT[1:0] OSC3WCE OSC3 On/Off OSC3OSC3EN/CLG_CTL1 0 SLEEPOSC3 OSC3EN OSC OSC3 OSC3EN OSC3 S1C On S1C Off OSC3On OSC3 OSC (OSC3EN/IOSCEN/OSC1EN) (fosc3/fiosc/fosc1) OSC3 OSC3WT[1:0]/CLG_CTL4 S1C17554/564 Technical Manual Seiko Epson Corporation 7-3
52 7 CLG OSC3 OSC3WT[1:0] : 1024OSC3 OSC3OnOSC3 OSC3 OSC3 OSC3 OSC3 max. + OSC3 : OSC3 OSC3 OSC3WCE/CLG_NFEN OSC3OSC3WCE = 1 OSC3 OSC3WCE OSC1 OSC kHz OSC1 16 PWM OSC3 IOSC OSC1 CG1 Rf1 OSC1 X'tal1 OSC1EN SLEEP OSC1WCE fosc1 VSS CD1 OSC2 (1) LVDD VSS OSC1 OSC1EN SLEEP OSC1WCE fosc1 N.C. OSC2 (2) OSC1 OSC1 OSC2X tal1, Typ kHz Rf1OSC1 OSC2 VSS 2 CG1 CD1 7-4 Seiko Epson Corporation S1C17554/564 Technical Manual
53 7 CLG OSC2 LVDD 50% OSC1 OSC1 On/Off OSC1OSC1EN/CLG_CTL0 1 SLEEPOSC1 OSC1EN 0 OSC1 OSC1 OSC1On OSC1 OSC1256 OSC1OnOSC1 OSC1 OSC1 OSC1 OSC1 max. + OSC1256 OSC1 OSC1WCE/CLG_NFEN OSC1OSC1WCE = 1 OSC1 OSC1WCE IOSCS1C17564 IOSC S1C17 IOSCEN IOSCWT[1:0] IOSC fiosc IOSC IOSC IOSCSEL[1:0]/CLG_IOSC IOSC IOSC On/Off IOSCSEL[1:0] IOSC typ. 2MHz 4MHz 12MHz 8MHz : IOSCIOSCEN/CLG_CTL0 1 SLEEPIOSC IOSCEN 1 IOSCOn IOSC S1C17 IOSC SLEEP SLEEP IOSCOn IOSC S1C17554/564 Technical Manual Seiko Epson Corporation 7-5
54 7 CLG IOSC 7.4 IOSCOn IOSC IOSC IOSC IOSCWT[1:0]/CLG_CTL IOSC IOSCWT[1:0] : 64IOSC CPU CPU CPU IOSC max. + IOSC64 IOSCOnIOSC IOSC IOSC LVDD IOSCWT[1:0] = IOSC IOSC max. + IOSC CLKSRC[1:0] S1C17564 fiosc fosc3 fosc S1C OSC3 OSC1 S1C IOSC OSC3 OSC1CLKSRC[1:0]/CLG_SRC S1C17554 OSC3 S1C17564 IOSC OSC CLKSRC[1:0] S1C17554 S1C17564 Reserved OSC3 OSC3 OSC1 OSC1 Reserved IOSC IOSC OSC1 OSC3 1. OSC3 OSC3WT[1:0] 2. OSC3 OSC3 OSC3WCE = 0 3. OSC3OffOn OSC3EN = 1 4. OSC3 CLKSRC[1:0] = 7-6 Seiko Epson Corporation S1C17554/564 Technical Manual
55 7 CLG 5. FOUTA/BIOSC OSC1 IOSC OSC1Off IOSC OSC3 OSC1 1. OSC1 OSC1 OSC1WCE = 0 2. OSC1On OSC1EN = 1 3. OSC1 CLKSRC[1:0] = 4. FOUTA/BIOSC OSC3 IOSC OSC3Off OSC3 OSC1 IOSC S1C IOSC IOSCWT[1:0] 2. IOSCOffOn IOSCEN = 1 3. IOSC CLKSRC[1:0] = 4. FOUTA/BOSC3 OSC1 OSC3 OSC1Off : CLKSRC[1:0] CLKSRC[1:0] S1C17554 OSC3EN OSC1EN 1 1 OSC3 OSC S1C17564 IOSCEN OSC3EN OSC1EN IOSC OSC3OSC IOSC OSC IOSC OSC OSC3 OSC1 Off CLKSRC[1:0] CLKSRC[1:0]1 S1C17564 SLEEP SLEEP IOSC On IOSCEN = 1 IOSC CLKSRC[1:0] = HALT HALT 7.5 CPU CCLK CLG S1C17 S1C17 haltclg S1C17 S1C17564 fiosc fosc3 fosc1 (1/1~1/8) HALT CCLK S1C CCLK S1C17554/564 Technical Manual Seiko Epson Corporation 7-7
56 7 CLG CCLKGR[1:0]/CLG_CCLK CCLK CCLKGR[1:0] 1/8 1/4 1/2 1/1 : CCLKhalt HALTNMI CCLK slpclg CCLK SLEEPCCLK PCLK CLG PCLK S1C17564 fiosc fosc3 fosc1 On/Off PCLK UART Ch Ch Ch.0 2 SPI Ch.0 2 USI Ch.0 1(S1C17564) I 2 C I 2 C (S1C17564) P & MUX MISC IR A/D PCLKPCKEN[1:0]/CLG_PCLK PCKEN[1:0] PCLK PCLK On Off : : PCKEN[1:0]/CLG_PCLK 7-8 Seiko Epson Corporation S1C17554/564 Technical Manual
57 7 CLG UART Ch.0 1 PCLK 1 16 Ch Ch.0 2 SPI Ch.0 2 USI Ch.0 1 S1C17564 I 2 C I 2 C S1C17564 P & MUX MISC IR A/D OSC1 PCLK PCLK 1 16 PWM OSC1 PCLK Ch.0 3 FOUTA/FOUTB IOSC/OSC3/OSC1 7.7 PCLK FOUTA, FOUTB IOSC/OSC3OSC1 OSC1 IOSC S1C17564 OSC3 FOUTA (1/1~1/4) (1/1~1/4) FOUTB FOUTA On/Off FOUTB On/Off (FOUTA ) (FOUTB ) CLG FOUTA FOUTB 2 FOUTA FOUTB FOUTA FOUTB FOUTA FOUTB P FOUTASRC[1:0]/CLG_FOUTA FOUTBSRC[1:0]/CLG_FOUTB IOSC S1C17564 OSC3 OSC FOUTASRC[1:0]/ FOUTBSRC[1:0] S1C17554 S1C17564 Reserved OSC3 OSC3 OSC1 OSC1 Reserved IOSC : S1C17554/564 Technical Manual Seiko Epson Corporation 7-9
58 7 CLG OSC3 IOSC3 FOUTAD[1:0]/CLG_FOUTA FOUTBD[1:0]/CLG_FOUTB IOSC/OSC3 FOUTAD[1:0]/FOUTBD[1:0] Reserved 1/4 1/2 1/1 : FOUTAE/CLG_FOUTA FOUTBE/CLG_FOUTB FOUTAE/FOUTBE 1 FOUTA/FOUTBFOUTA/FOUTB 0 FOUTAE (FOUTBE) FOUTA (FOUTB) FOUTA/FOUTB : FOUTA/FOUTB FOUTAE/FOUTBE On/Off CLG 0x5060 CLG_SRC Clock Source Select 0x5061 CLG_CTL Oscillation Control 0x5062 CLG_NFEN Noise Filter Enable / ON/OFF 0x5064 CLG_FOUTA FOUTA Control FOUTA 0x5065 CLG_FOUTB FOUTB Control FOUTB 0x506e CLG_IOSC IOSC Control IOSC 0x5080 CLG_PCLK PCLK Control PCLK 0x5081 CLG_CCLK CCLK Control CCLK CLG 8 : Reserved 0 1 Clock Source Select (CLG_SRC) name Address Bit Name Function Setting Init. R/W Remarks Clock Source 0x5060 D7 2 0 when being read. Select (CLG_SRC) D1 0 CLKSRC[1:0] System clock source select CLKSRC[1:0] Clock source R/W S1C17554 Clock Source Select (CLG_SRC) S1C x5060 OSC3 OSC1 D7 2 0 when being read. D1 0 CLKSRC[1:0] System clock source select CLKSRC[1:0] Clock source R/W OSC3 OSC1 IOSC D[7:2] Reserved 7-10 Seiko Epson Corporation S1C17554/564 Technical Manual
59 7 CLG D[1:0] CLKSRC[1:0]: System Clock Source Select Bits CLKSRC[1:0] S1C17554 S1C17564 Reserved OSC3 OSC3 OSC1 OSC1 Reserved IOSC IOSC OSC3 OSC1 IOSC OSC3 : CLKSRC[1:0] CLKSRC[1:0] S1C17554 OSC3EN OSC1EN 1 1 OSC3 OSC S1C17564 IOSCEN OSC3EN OSC1EN IOSC OSC3OSC IOSC OSC IOSC OSC OSC3 OSC1 Off CLKSRC[1:0] CLK- SRC[1:0]1 S1C17564 SLEEP SLEEPIOSCOn IOSCEN = 1 IOSC CLKSRC[1:0] = HALT HALT Oscillation Control (CLG_CTL) name Address Bit Name Function Setting Init. R/W Remarks Oscillation 0x5061 D7 6 0 when being read. Control (CLG_CTL) D5 4 OSC3WT[1:0] OSC3 wait cycle select OSC3WT[1:0] Wait cycle R/W S1C17554 Oscillation Control (CLG_CTL) S1C x cycles 256 cycles 512 cycles 1024 cycles D3 2 0 when being read. D1 OSC1EN OSC1 enable 1 Enable 0 Disable 0 R/W D0 OSC3EN OSC3 enable 1 Enable 0 Disable 1 R/W D7 6 IOSCWT[1:0] IOSC wait cycle select IOSCWT[1:0] Wait cycle R/W 8 cycles 16 cycles 32 cycles 64 cycles D5 4 OSC3WT[1:0] OSC3 wait cycle select OSC3WT[1:0] Wait cycle R/W 128 cycles 256 cycles 512 cycles 1024 cycles D3 0 when being read. D2 IOSCEN IOSC enable 1 Enable 0 Disable 1 R/W D1 OSC1EN OSC1 enable 1 Enable 0 Disable 0 R/W D0 OSC3EN OSC3 enable 1 Enable 0 Disable 0 R/W S1C17554/564 Technical Manual Seiko Epson Corporation 7-11
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お客様各位 カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し 両社の全ての事業が当社に承継されております 従いまして 本資料中には旧社名での表記が残っておりますが 当社の資料として有効ですので ご理解の程宜しくお願い申し上げます ルネサスエレクトロニクスホームページ (http://www.renesas.com)
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