Vol. 43 No. SIG 6(HPS 5) PNN 207 PNN / PNN PNN 2 PNN PNN 3 PNN Kernel Layer Summation Layer Decision Layer X =(x,x 2,..., x n ) S i j C i
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1 Vol. 43 No. SIG 6(HPS 5) Sep PNN: Probabilistic Neural Network PNN PNN 33.3 ms 0 An Architecture for Parallelized High-speed Probabilistic-Neural- Network Calculation and Its Application to Image Recognition Systems Noriyuki Aibe and Moritoshi Yasunaga Recently, probabilistic neural networks (PNN) are being applied to the practical pattern recognition applications such as face recognition and satellite-image recognition. In order to obtain high recognition accuracy, however, PNN requires a large number of sample patterns to be processed in it. Furthermore, the PNN calculation must be repeated so many times in its learning-stage to determine a network parameter precisely. Specialized hardware is thus indispensable for the high speed PNN calculation. In this paper, we propose a specialized processor and a parallel architecture using the processors for high speed PNN calculation. And we develop an image-recognition prototype system in a small single board. Measurements of the system show its high-speed recognition in a video-rate period of 33.3 ms and a high-speed learning less than 0 seconds is estimated using the measured result. Those results demonstrate effectiveness of the proposed hardware for the practical pattern recognition problems.. PNN: Probabilistic Neural Network Specht 3 ) 4) Mao 5), Tian 6),7) Graduate School, Doctoral Program of Systems and Information Engineering, University of Tsukuba Institute of Information Sciences and Electronics, University of Tsukuba PNN PNN PNN 33.3 ms PNN 206
2 Vol. 43 No. SIG 6(HPS 5) PNN 207 PNN / PNN PNN 2 PNN PNN 3 PNN Kernel Layer Summation Layer Decision Layer X =(x,x 2,..., x n ) S i j C i j K ( ) ( ) X S i j K X S i j K ( { ) X S i : xk (s i j) k σ j = 2 () 0 : otherwise (for all k, k =, 2,...,n) X =(x,x 2,...,x n ), S i j = ( (s i j), (s i j) 2,...,(s i j) n ) x k, (s i j) k k n () σ Fig. Network configuration of PNN. PNN Summation Layer X C i p (X C i ) ˆp (X C i )= N p N p j=0 K ( ) X S i j (2) N p /N p Decision Layer 2.2 spnn serial-pnn Processor PNN 8),9)
3 208 Sep Look-up Table 8),0) 2) spnn Processor 33.3 ms spnn Processor 4 3. PNN σ σ PNN PNN σ σ σ / PNN PNN 6) 7) GOES-8 / PNN 5 PNN PNN Sigma-Parallel Architecture SPA SPA PNN σ σ spnn Processor SPA VLSI VLSI spnn Processor Hybrid-SPA 3. Sigma-Parallel Architecture SPA C i j S i j S i j n, q bit qn bit N p N c qnn p N c bit q =8 n =256 N p =52 N c =8 MByte N c N p MByte MByte 2 (a) PNN 2 (a) Neuron in Kernel Layer X σ X
4 Vol. 43 No. SIG 6(HPS 5) PNN 209 Fig. 2 2 SPA Neuron Parallel Architecture vs. Sigma Parallel Architecture. σ σ m m =0 m = N σ N σ σ 2 (a) qn p N c q q (N p N c +) q =8 N p =52 N c = 8 q (N p N c +) = 32, 776 σ 2 (b) SPA Sigma-Parallel ArchitectureSPA spnn Processor σ spnn Processor PNN PNN spnn Processor σ Neuron-Parallel Architecture σ Sigma-Parallel Architecture σ log 2 N σ spnn Processor spnn Processor q bit, q bit 2q σ / VLSI 8),2) 6) SPA PNN 3.2 Hybrid-SPA 2 (b) SPA SPA spnn Processor 2 (b) VLSI Chip 3 SPA-Module 3
5 20 Sep SPA Fig. 3 Neuron parallelism based on the SPA. σ Hybrid-SPA Hybrid- SPA 4. PNN SPA spnn Processor Hybrid-SPA 4. spnn Processor spnn Processor 4 X S i j σ m PNN PNN 3 PNN X S i j ( q bit x,x 2,...,x n ) (s i j), (s i j) 2,...,(s i j) n () σ m m σ SPA () PNN ˆp (X C i ) 7) ˆp (X C i ) ˆp (X C i ) X Minchin PNN 8) % 94.2% % 94.0%.5 2.8% 9) 4 C i j ( ) s i Kernel Size Adjuster σ j m/2 Kernel Size Comparator ( ) ( s i j + σ m/2 ) s i j σ m/2 X x () xk ( ) s i j k σ/2 Kernel Size Comparator (( ) s i σ j m/2 ) x (( ) s i j + σ m/2 ) x 0 S i j
6 Vol. 43 No. SIG 6(HPS 5) PNN 2 Fig. 4 4 spnn Processor Circuit configuration of spnn Processor. () Summation Layer Decision Layer Register Max Detector spnn Processor Xilinx FPGA XCV000E-6HQ240C SLICE SLICE SLICE XCV000E 2,288 SLICE 20) FPGA 64 spnn Processor ASIC spnn Processor 4.2 SPA 5 5 Hybrid-SPA PNN 2 FPGA Xilinx XCV000E-6HQ240C XCV300E-6PQ240C 5 Hybrid-SPA Fig. 5 System configuration using the Hybrid-SPA. LSI 4M-bit SRAM HM62W85HJP FPGA XCV000E 3 Hybrid-SPA 64 spnn Processor 64 spnn Processor 4 SPA- Module 4
7 22 Sep Fig. 6 6 Configuration of image recognition system. SPA-Module 6 spnn Processor 6σ 64 spnn Processor Processor 5 Common Data Bus FPGA XCV300E FPGA σ Best σ Detector Best σ Detector spnn Processor spnn Processor 8 bit Best σ Detector spnn Processor Best σ Detector spnn Processor spnn Processor Hybrid- SPA Module 5 7 spnn Processor FPGA XCV000E XCS30XL-4PQ240C 30,000 XCS30XL 3 spnn Processor 6
8 Vol. 43 No. SIG 6(HPS 5) PNN 23 Table Fig. 7 Specification of prototype system. 27 MHz (spnn Processor:3.5 MHz) 3 spnn Processors (Max) 48 Mbit (4 Mbit 2)(Max) 96 bit (8 bit 2)(Max) mm (4 ) NTSC PS/2 ATA Analog-RGB RS-232C 7 Photograph of prototype system. NTSC OKI MSM7674 A/D FPGA Xilinx XCV800-4HQ240C 6 6 XCV800-4HQ240C NTSC AnalogDevices ADV776AKS 6 6 spnn Processors spnn Processors 4Mbit-SRAM HM62W85HJP-2 2 XCS30XL-4PQ240C 8 bit 2 96 bit Best σ Detector Xilinx XCV300-4PQ240C SPA 8 Main Board 6 8 Sub Board spnn Processor Hybrid-SPA Module Main Board Sub Board 8 Pre-Processed Unknown Pattern Input Hybrid-SPA Module Common Data Bus 2 Hybrid-SPA Module XCV000E 64 spnn Processor 2 XCV000E spnn Processor 28 Processor XCV000E spnn Processor Processor PNN NTSC 6 6 segment 8 bit n =256 q =8 spnn Processor 8.96 µs 33.3 ms, N p =256 spnn Processor 6 7 N c = spnn Processor XCV000E 6σ 4 Hybrid-SPA T learn
9 24 Sep Fig. 8 8 spnn Processor Configuration of the extened system using Sub Boards. T learn = (T recog. + βn sp NN N Mod. T CLK ) N tp N σ N sp NN (3) T recog. = ( + qnn pn c rn Mod. + αn c + βn Mod. ) T CLK (4) n : q : r : s : N c : N p : N tp : N σ : N sp NN : N Mod. : α : γ : T CLK : spnn Processor σ SPA-Module spnn Processor SPA-Module spnn Processor Best σ Detector T recog. β = log 2 N p + log 2 N c s + γ (5) 5 spnn Processor Best σ Detector 5 Common Data Bus SPA-Module 5 spnn Processor Hybrid-SPA Module SPA-Module T recog. 2 qnn p N c rn Mod. n =256 q = r = s = 8 bit N c = N p =256 N Mod. = α = γ =0 T CLK =/3.5MHz T recog. = 4.85ms
10 Vol. 43 No. SIG 6(HPS 5) PNN 25 (3) β spnn Processor Best σ Detector (3) N c =8 2.5sec N c = sec Intel PentiumIII- GHz PC gcc ANSI C N c =8 70 sec N c = sec SPA PC 5 Hybrid-SPA Module spnn Processor XCV000E,569,78 System Gates 20) XCV3200E 4,074,387 System Gates 20) spnn Processor (3) (4) β spnn Processor FPGA XCV000E XCV3200E PC XCV000E Sub Board 3 64 spnn Processors 7 Hybrid-SPA Modules spnn Processor 448 (3) (4) PC 480 FPGA Sub Board W 3 C C 2 C 3 FPGA Field Programmable Gate Array σ σ =0 256 N σ =256 σ = Unknown Pattern Field Video Camera Prototype Board SONY DCR-PC0 Video Monitors q =8 n =256 N p = N tp =256 N c =3 N sp NN = N Mod. = r = s =8 80% spnn Processor SPA
11 26 Sep Fig. 9 Recognition test system. 200 No Fig. 0 Sample patterns for recognition test. 80% 33.3 ms 256 /256 / ) Specht, D.: Probabilistic Neural Networks, J. Neural Networks, Vol.3, pp.09 8 (990). 2) Specht, D.: Probabilistic Neural Networks and the Polynomial Adaline as Complementary Techniques for Classification, IEEE Trans. Neural Networks, Vol., No., pp.0 (990). 3) Müller, Klaus-R., Mika, S., Rätsch, G., Tsuda, K. and Schölkopf, B.: An Introduction to Kernel-Based Learning Algorithms, IEEE Trans. Neural Networks, Vol.2, No.2, pp.8 20 (200). 4) Ruiz, A. and López-de Teruel, P.E.: Nonlinear Kernel-Based Statistical Pattern Analysis, IEEE Trans. Neural Networks, Vol.2, No., pp.6 32 (200). 5) Mao, K.Z., Tan, K.C. and Ser, W.: Probabilistic Neural-Network Structure Determination for Pattern Classification, IEEE Trans. Neural Networks, Vol., No.4, pp (2000). 6) Tian, B., Azimi-Sadjadi, M.R., Vonder Harr, T.H. and Reinke, D.: Temporal Updating Scheme for Probabilistic Neural Network with Application on Satellite Cloud Classification, IEEE Trans. Neural Networks, Vol., No.4, pp (2000). 7) Tian, B., Azimi-Sadjadi, M.R.: Comparison
12 Vol. 43 No. SIG 6(HPS 5) PNN 27 of Two Different PNN Training Approaches for Satellite Cloud Data Classification, IEEE Trans. Neural Networks, Vol.2, No., pp (200). 8) LSI (995). 9) Gotarredona, T.S., Barranco, B.L. and Andreou, A.G.: Programmable Kernel Analog VLSI Convolution Chip for Real Time Vision Processing, Proc. IEEE Int l Joint Conf. Neural Networks, CD-ROM (2000). 0) Szabo, T., Antoni, L., Horvath, G. and Feher, B.: A full-parallel digital implementation for pre-trained NNs, Proc. IEEE Int l Joint Conf. Neural Networks, CD-ROM (2000). ) Girau, B. and Lorraine, L.: Digital hardware implementation of 2D compatible neural networks, Proc. IEEE Int l Joint Conf. Neural Networks, CD-ROM (2000). 2) Yasunaga, M., Masuda, N., Yagyu, M., Asai, M., Yamada, M. and Masaki, A.: Design, Fabrication and Evaluation of A 5-inch Wafer Scale Neural Network LSI Composed of 576 Digital Neurons, IJCNN 90, II, pp (990). 3) J84-D-II, No.6, pp (200). 4) Sinencico, E.S. and Lau, C. (Eds.): Artificial Neural Networks: Paradigms, Applications, and Hardware Implementations, IEEE Press (992). 5) Kohonen, T.: Chapter 8 (Hardware for SOM) in Self-Organizing Maps, Vol., 2nd edition, chapter 2, pp.37 38, Springer (997). 6) Wawrzynek, J., Asanovic, K., Kingsbury, B., Johnson, D., Beck, J. and Morgan, N.: Spert-II: A Vector Micro Processor System, Special Issue of Neural Computing in IEEE COMPUTER, Vol.29, No.3, pp (996). 7) Bishop, C.: Neural Network for Pattern Recognition, Oxford Press (995). 8) Minchin, G. and Zaknich, A.: A Design for FPGA Implementation of the Probabilistic Neural Network. 9) PRMU2000-7, pp.7 78 (2000). 20) Xilinx, Inc.: Virtex-E.8V Field Programmable Gate Arrays, DS022- (v2.2) (200) c X X 2 (a) c~ 2 ~ ~ X X 2 (b) P(A) p(x A) P(B) p(x B) c~ c Fig. Experimental result of cross-points approximation between the probabilistic density distributions. 2 PC 2 p(x A) p(x B) (a) c c 2 X X =0.33 X 2 = S 20 S () (b) c c 2 X X =0.337 X 2 = () σ σ 20 σ =0.5, 0.05, ( 4 29 ) ( ) X
13 28 Sep IEEE INNS
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1 Table 1: Identification by color of voxel Voxel Mode of expression Nothing Other 1 Orange 2 Blue 3 Yellow 4 SSL Humanoid SSL-Vision 3 3 [, 21] 8 325
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17 Proposal of an Algorithm of Image Extraction and Research on Improvement of a Man-machine Interface of Food Intake Measuring System
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4. C i k = 2 k-means C 1 i, C 2 i 5. C i x i p [ f(θ i ; x) = (2π) p 2 Vi 1 2 exp (x µ ] i) t V 1 i (x µ i ) 2 BIC BIC = 2 log L( ˆθ i ; x i C i ) + q
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Kochi University of Technology Aca Title 省 電 力 セルフタイム 回 路 に 関 する 研 究 Author(s) 岩 田, 誠, 宮 城, 桂, 三 宮, 秀 次, 西 川, 博 昭 Citation 高 知 工 科 大 学 紀 要, 10(1): 95-102 Date of 2013-07-20 issue URL http://hdl.handle.net/10173/1082
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[2] OCR [3], [4] [5] [6] [4], [7] [8], [9] 1 [10] Fig. 1 Current arrangement and size of ruby. 2 Fig. 2 Typography combined with printing
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Vol.55 No.1 2 15 (Jan. 2014) 1,a) 2,3,b) 4,3,c) 3,d) 2013 3 18, 2013 10 9 saccess 1 1 saccess saccess Design and Implementation of an Online Tool for Database Education Hiroyuki Nagataki 1,a) Yoshiaki
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![(a) 1 (b) 3. Gilbert Pernicka[2] Treibitz Schechner[3] Narasimhan [4] Kim [5] Nayar [6] [7][8][9] 2. X X X [10] [11] L L t L s L = L t + L s](/thumbs/75/72066128.jpg "(a) 1 (b) 3. Gilbert Pernicka[2] Treibitz Schechner[3] Narasimhan [4] Kim [5] Nayar [6] [7][8][9] 2. X X X [10] [11] L L t L s L = L t + L s")
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