c t WC 1 2: SRAM 1.2 DRAM DRAM DRAM DRAM 3 4M 1 DRAM 22 1 A0 A10 11 DRAM 22 DIN DOUT 1 DRAM

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あまめみのしま
7 years ago
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1 2014/4/ SRAM SRAM 1 128K 1M 128K SRAM CS 1 OE 2 WE 3 CS OE WE V CC V SS 1: SRAM SRAM 2 2 (a) t ACC t RC 1 2 (b) t CSW CS 1 chip select 2 output enable 3 write enable 1

2 c t WC 1 2: SRAM 1.2 DRAM DRAM DRAM DRAM 3 4M 1 DRAM 22 1 A0 A10 11 DRAM 22 DIN DOUT 1 DRAM

3 c WE 4 RAS 5 CAS 6 WE RAS CAS 3: DRAM DRAM 4 1. RAS 2. RAS CAS 3. DOUT 4. CAS RAS DOUT t RACC 7 RAS t RC 1. RAS 2. RAS WE DIN 3. CAS WE 4. CAS 4 write enable 5 row address strobe 6 column address strobe 7 RAS

4 c : DRAM

5 c RAS WE WE t RW C RAS t W C DRAM RAS 3 16 ms 16, ms 2 11 = 7.8 µs (1) KB SRAM4 128KB SRAM 5: 5 1. CS 2 H H 07FFF 1 H H 0FFFF 2 H H 17FFF 3 H H 1FFFF 4

6 c : A B Y0 Y1 Y2 Y3 L L L H H H L H H L H H H L H H L H H H H H H L 1.4 FPM-DRAM 8 1 DRAM EDO-DRAM 9 FPM-DRAM RDRAM 10 DRAM DRAM SDRAM 11 DRAM 1 1 DDR SDRAM 12 SDRAM 2 DPRAM 13 2 DMA 6 CPU I/O PIO 14 CPU I/O CPU DMA 8 Fast Page Mode DRAM 9 Extended Data Out DRAM 10 Rambus DRAM 11 Synchronous DRAM 12 Double Data Rate SDRAM 13 Dual Port RAM 14 Programmed I/O

SDRAM 2 DPRAM 13 2 DMA 6 CPU I/O PIO 14 CPU I/O CPU DMA 8 Fast Page Mode DRAM 9 Extended

7 c : CPU DMA 15 7 DMA DMAC 16 I/O 17 DMA CPU CPU DMA CPU 7: DMA DMA Direct Memory Access 16 Dicect Memory Access Controller 17 H8/3062BF DMA

8 c DMA CPU DMA CPU CPU CPU DMAC 3 H8 H8 H8 3.1 ROM RAM I/O H8 8 CS n 2: H8/3062BF 5 0 H H 1FFFFF CS 0 1 H H 3FFFFF CS 1 2 H H 5FFFFF CS 2 3 H H 7FFFFF CS 3 4 H H 9FFFFF CS 4 5 H A00000 H BFFFFF CS 5 6 H C00000 H DFFFFF CS 6 7 H E00000 H FFFFFF CS 7

200000 H 3FFFFF CS 1 2 H 400000 H 5FFFFF CS 2 3 H 600000 H 7FFFFF CS 3 4

9 c H8 3 3: A 23 A 0 D 15 D 0 CS 7 CS 0 AS RD HWR LWR WAIT BREQ BACK H8/3062BF (ABWCR) 8 D 15 D 8 CS 7 CS 4 (CSCR) 4: H8/3062BF A 7 A 0 P17 P10 AS P63 A 15 A 8 P27 P20 RD P64 A 19 A 16 P53 P50 HWR P65 A 23 A 20 PA4 PA7 LWR P66 D 7 D 0 P47 P40 WAIT P60 D 15 D 8 P37 P30 BREQ P61 CS 3 CS 0 P81 P84 BACK P62 CS 7 CS 4 PB0 PB3 8

10 c : H8 9 2 n CS n AS RD CS n AS RD 9: H n CS n AS WR WR HWR LWR D 15 D 8 D 7 D 0 8 HWR CPU

11 c : H8 3 WAIT 9 3 T W 11 WCRH WCRL 11: BCR WAITE 1 WAIT T 2 T W WAIT WAIT

12 c T W : 1 4 MPU DMA H8/3062BF CPU 13 3 BREQ BACK 14 BREQ BREQ BACK AS RD HWR LWR BREQ BREQ 2 18 BACK ISA PCI PCI Express ATA 18 2 BREQ

13 c : 14: ]

14 c (MTR-300) MTR SRAM H 1F8000 H 1FFFFF 32KB SRAM H H 21FFF 128KB H H 27FFFF 512KB 15: MTR-300 MTR H 1F (ABWCR) 8 P84 DDR CS0 1: 1 ; S R A M ( 5 ) 2 ; SRAM H 1 F8000 H 1 FFFFF ( 0 3. CPU 300 HA 4 P1DDR. EQU H FEE000 5 P2DDR. EQU H FEE001 6 P3DDR. EQU H FEE002

15 c P4DDR. EQU H FEE003 8 P5DDR. EQU H FEE004 9 P6DDR. EQU H FEE P8DDR. EQU H FEE PBDDR. EQU H FEE00A 12 P1DR. EQU H FFFFD0 ;A0 -A7 13 P2DR. EQU H FFFFD1 ;A8 - A15 14 P3DR. EQU H FFFFD2 ;D8 - D15 15 P4DR. EQU H FFFFD3 ; VPD <- > I/ O board VP1 16 P5DR. EQU H FFFFD4 ;A16 - A18 (P50 - P52 ) 17 P6DR. EQU H FFFFD5 ;RD(P64 ), HWR ( P65 ) 18 P8DR. EQU H FFFFD7 ; CS0 ( P84 ) 19 PBDR. EQU H FFFFDA ; VPE <- > I/ O board VP2 20. SECTION PROG,CODE, LOCATE =H DATA.L RESET 22. SECTION P,CODE, LOCATE =H RESET : MOV.L #H FFF00, ER7 ; S P 24 MOV.B #H FF, R0L 25 MOV.B ; 1 (A0 -A7) 26 MOV.B ; 2 (A8 - A15 ) 27 MOV.B ; 5 (A16 - A18 ) 28 MOV.B ; 3 (D8 - D15 ) 29 MOV.B ; 4 30 MOV.B ; B 31 MOV.B #B , R0L 32 MOV.B ;P64, P 6 5 (RD, HWR ) 33 MOV.B #B , R0L 34 MOV.B ; P 8 4 ( CS0 ) 35 MOV.B #H 01, R0L ; 36 MOV.L #H 1 F8000, ER1 ; 37 MOV.B #H 0F,R0H ; 38 WLOOP : MOV.B ; 39 ROTL.B R0L ; 40 INC.L #1, ER1 ; 41 DEC.B R0H ; 42 BNE WLOOP ; 43 MOV.B #H 00, R0L 44 MOV.B ; 3 (D8 - D15 ) 45 RLOOP : MOV.L #H 1 F8000, ER1 ;

EQU H FFFFD7 ; CS0 ( P84 ) 19 PBDR. EQU H FFFFDA ; VPE <- > I/ O board VP2 20. SECTION PROG,CODE, LOCATE =H 000000 21. DATA.L RESET 22. SECTION P,CODE, LOCATE =H 000100 23 RESET : MOV.

16 c MOV.B #H 0F,R0H ; 47 RLOOP1 : R0L ; 48 MOV.B ; MOV.B ; B 50 ; INC.L #1, ER1 ; 52 DEC.B R0H ; 53 BNE RLOOP1 ; 54 RLOOP 55 ; TIM : MOV.L #D , ER6 57 TIM1 : DEC.L #1, ER6 58 NOP 59 BNE TIM1 60 RTS 61. END A 5 5 H8/3062BF 5: ABWCR H EE020 H WCRH H EE022 L WCRL H EE023 CSCR H EE01F BCR H EE024

B R0H ; 53 BNE RLOOP1 ; 54 JMP @ RLOOP 55 ;100 56 TIM : MOV.L #D 312500, ER6 57 TIM1 : DEC.

c J 2013/11/ H8/3062BF H NOP 2 PUSH.L ER5 1: 3 4, ER7 ), ER5 4 PUSH.L ER5 5 MOV.L 8, ER7 )

c J 2013/11/ H8/3062BF H NOP 2 PUSH.L ER5 1: 3 4, ER7 ), ER5 4 PUSH.L ER5 5 MOV.L 8, ER7 ) c 2013 2013 2J 2013/11/29 1 2 0 H8/3062BF H8 1 2 10 1 1 NOP 2 PUSH.L ER5 1: 3 MOV.L @(H 4, ER7 ), ER5 4 PUSH.L ER5 5 MOV.L ER6,@(H 8, ER7 ) 1 1 1 1 10 1 16 1: 2013 2J c 2013 2 2 5 6 2 1 B 2: 1. CPU 300