AD8191：4:1 HDMI/DVIスイッチ、イコライゼーション機能付き

Transcription

1 :1 HDMI/DVI AD HDMI TM /DVI 1TMDS 250Mbps 1.65Gbps MHz HDMI 1080p 20 50Ω 3.3V V HDCP DDC 2 :1 HDMI/DVI 1 8:1 TMDS21 16:1 TMDS11 AD8191 2HDMI DVI HDMI DVI HDCP I 2 C 1mm 1mm 100LQFP A/V HDTV AD8191TMDS TMDSHDMI/DVI OR TMD AD8191 :1 HDMI/DVI 1 8:1 2 16:1 1 AD LQFP 085 PARALLEL SERIAL I2C_SDA I2C_SCL I2C_ADDR[2:0] VTTI IP_A[3:0] IN_A[3:0] IP_B[3:0] IN_B[3:0] IP_C[3:0] IN_C[3:0] IP_D[3:0] IN_D[3:0] VTTI AUX_A[3:0] AUX_B[3:0] AUX_C[3:0] AUX_D[3:0] MEDIA CENTER SET-TOP BOX PP_CH[1:0] PP_OTO PP_OCL PP_EQ PP_EN PP_PRE[1:0] 2 2 CONFIG INTERFACE EQ HIGH SPEED LOW SPEED UNBUFFERED BIDIRECTIONAL 1 RESET CONTROL LOGIC SWITCH CORE SWITCH CORE HDTV SET HDMI RECEIVER BUFFERED GAME CONSOLE DVD PLAYER AD :18 2. HDTV PE AD8191 AVCC DVCC AMUXVCC AVEE DVEE VTTO + OP[3:0] ON[3:0] AUX_COM[3:0] Gbps 1080p HDMI UXGA DVI p202AWG 3. HDMI 1.2a DDC REV. 0 REVISION 2006 Analog Devices, Inc. All rights reserved MT

2 10/06 Revision 0: Initial Version

3 T A 27AVCC 3.3V VTTI 3.3V VTTO 3.3V DVCC 3.3V AMUXVCC 5V AVEE 0V DVEE 0V1000mV TMDS 50Ω 3.3V 1 Parameter Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel NRZ 1.65 Gbps Bit Error Rate (BER) PRBS Added Deterministic Jitter DR 1.65 Gbps, PRBS ps (p-p) Added Random Jitter 2 ps (rms) Differential Intrapair Skew At output 1 ps Differential Interpair Skew 1 At output 0 ps EQUALIZATION PERFORMANCE Receiver (Highest Setting) 2 Boost frequency = 825 MHz 12 db Transmitter (Highest Setting) 3 Boost frequency = 825 MHz 6 db INPUT CHARACTERISTICS Input Voltage Swing Differential mv Input Common-Mode Voltage (V ICM ) AVCC 800 AVCC mv OUTPUT CHARACTERISTICS High Voltage Level Single-ended high speed channel AVCC 10 AVCC 10 mv Low Voltage Level Single-ended high speed channel AVCC 600 AVCC 00 mv Rise/Fall Time (20% to 80%) ps INPUT TERMINATION Resistance Single-ended 50 Ω AUXILIARY CHANNELS On Resistance, R AUX 100 Ω On Capacitance, C AUX DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 khz 8 pf Input/Output Voltage Range DVEE AMUXVCC V POWER SUPPLY AVCC Operating range V QUIESCENT CURRENT AVCC Outputs disabled 30 0 ma Outputs enabled, no pre-emphasis ma Outputs enabled, maximum pre-emphasis ma VTTI Input termination on ma VTTO Output termination on, no pre-emphasis ma Output termination on, maximum ma pre-emphasis DVCC ma AMUXVCC ma POWER DISSIPATION Outputs disabled mw Outputs enabled, no pre-emphasis mw Outputs enabled, maximum pre-emphasis mw TIMING CHARACTERISTICS Switching/Update Delay High speed switching register: HS_CH 200 ms All other configuration registers 1.5 ms RESET Pulse Width 50 ns

4 Parameter Conditions/Comments Min Typ Max Unit SERIAL CONTROL INTERFACE 5 Input High Voltage, V IH 2 V Input Low Voltage, V IL 0.8 V Output High Voltage, V OH 2. V Output Low Voltage, V OL 0. V PARALLEL CONTROL INTERFACE Input High Voltage, V IH 2 V Input Low Voltage, V IL 0.8 V 1 TMDS 2 AD8191DVI Standard Revision 1.0 HDMI Standard Revision 1.2a 3 DVI Standard Revision 1.0 HDMI Standard Revision 1.2a HDMI/DVIHDMI/DVI 5 AD8191 I 2 C 3.3V I 2 C

5 2 Parameter Rating AVCC to AVEE 3.7 V DVCC to DVEE 3.7 V DVEE to AVEE ±0.3 V VTTI AVCC V VTTO AVCC V AMUXVCC 5.5 V Internal Power Dissipation 2.2 W High Speed Input Voltage AVCC 1. V < V IN < AVCC V High Speed Differential 2.0 V Input Voltage Low Speed Input Voltage DVEE 0.3 V < V IN < AMUXVCC V I 2 C and Parallel Logic Input Voltage DVEE 0.3 V < V IN < DVCC V Storage Temperature Range 65 to +125 Operating Temperature Range 0 to +85 Junction Temperature 150 θ JA JEDEC θ JC 3. Package Type θ JA θ JC Unit 100-Lead LQFP /W AD ESD ESD ESD ESD

6 I2C_ADDR0 I2C_ADDR1 I2C_ADDR2 DVEE PP_CH0 PP_CH1 DVCC ON0 OP0 VTTO ON1 OP1 DVCC ON2 OP2 VTTO ON3 OP3 RESET PP_PRE0 PP_PRE1 DVCC PP_OCL I2C_SCL I2C_SDA PP_OTO AUX_A0 AUX_A1 AUX_A2 AUX_A3 DVEE AUX_B0 AUX_B1 AUX_B2 AUX_B3 AUX_COM0 AUX_COM1 AUX_COM2 AUX_COM3 AUX_C0 AUX_C1 AUX_C2 AUX_C3 AMUXVCC AUX_D0 AUX_D1 AUX_D2 AUX_D3 PP_EQ PP_EN AVCC IN_B0 IP_B AVCC 7 IP_C3 73 IN_C3 AVEE 72 AVEE IN_B IP_C2 IP_B IN_C2 VTTI 7 69 VTTI IN_B IP_C1 IP_B IN_C1 AVEE AVEE IN_B3 IP_B3 AVCC IN_A0 IP_A0 AVEE IN_A1 IP_A1 VTTI IN_A2 IP_A2 AVCC IN_A3 IP_A3 AVEE IP_C0 6 IN_C0 63 AVCC 62 IP_D3 61 IN_D3 60 AVEE 59 IP_D2 58 IN_D2 57 VTTI 56 IP_D1 55 IN_D1 5 AVCC 53 IP_D0 52 IN_D0 51 AVEE PIN 1 INDICATOR AD8191 TOP VIEW (Not to Scale) , 13, 22, 5, 63, 75 AVCC 3.3V 2 IN_B0 HS I B0 3 IP_B0 HS I B0, 10, 16, 25, 51, 60, 66, 72 AVEE 0V 5 IN_B1 HS I B1 6 IP_B1 HS I B1 7, 19, 57, 69 VTTI AVCC 8 IN_B2 HS I B2 9 IP_B2 HS I B2 11 IN_B3 HS I B3 12 IP_B3 HS I B3 1 IN_A0 HS I A0 15 IP_A0 HS I A0

7 1 17 IN_A1 HS I A1 18 IP_A1 HS I A1 20 IN_A2 HS I A2 21 IP_A2 HS I A2 23 IN_A3 HS I A3 2 IP_A3 HS I A3 26 I2C_ADDR0 I 2 C1LSB 27 I2C_ADDR1 I 2 C2LSB 28 I2C_ADDR2 I 2 C3LSB 29, 95 DVEE 0V 30 PP_CH0 LSB 31 PP_CH1 MSB 32, 38, 7 DVCC 3.3V 33 ON0 HS O 0 3 OP0 HS O 0 35, 1 VTTO AVCC 36 ON1 HS O 1 37 OP1 HS O 1 39 ON2 HS O 2 0 OP2 HS O 2 2 ON3 HS O 3 3 OP3 HS O 3 RESET AVCC 5 PP_PRE0 LSB 6 PP_PRE1 MSB 8 PP_OCL 9 I2C_SCL I 2 C 50 I2C_SDA I 2 C 52 IN_D0 HS I D0 53 IP_D0 HS I D0 55 IN_D1 HS I D1 56 IP_D1 HS I D1 58 IN_D2 HS I D2 59 IP_D2 HS I D2 61 IN_D3 HS I D3 62 IP_D3 HS I D3 6 IN_C0 HS I C0 65 IP_C0 HS I C0 67 IN_C1 HS I C1 68 IP_C1 HS I C1 70 IN_C2 HS I C2 71 IP_C2 HS I C2 73 IN_C3 HS I C3 7 IP_C3 HS I C3 76 PP_EN 77 PP_EQ 78 AUX_D3 LS I/O

8 1 79 AUX_D2 LS I/O 80 AUX_D1 LS I/O 81 AUX_D0 LS I/O 82 AMUXVCC 5V typ 83 AUX_C3 LS I/O 8 AUX_C2 LS I/O 85 AUX_C1 LS I/O 86 AUX_C0 LS I/O 87 AUX_COM3 LS I/O 88 AUX_COM2 LS I/O 89 AUX_COM1 LS I/O 90 AUX_COM0 LS I/O 91 AUX_B3 LS I/O 92 AUX_B2 LS I/O 93 AUX_B1 LS I/O 9 AUX_B0 LS I/O 96 AUX_A3 LS I/O 97 AUX_A2 LS I/O 98 AUX_A1 LS I/O 99 AUX_A0 LS I/O 100 PP_OTO 1 HSLSIO

9 T A 27AVCC 3.3V VTTI 3.3V VTTO 3.3V DVCC 3.3V AMUXVCC 5V AVEE 0V DVEE 0V1000mV TMDS 50Ω 3.3V PRBS Gbps HDMI CABLE DIGITAL PATTERN GENERATOR AD8191 EVALUATION BOARD SERIAL DATA ANALYZER SMA COAX CABLE REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3. RX TP2 RX 2m 30AWG 0.125UI/DIV AT 1.65Gbps 7. TP3 RXEQ 6dB 2m 30AWG 250mV/DI V 2 50mV/DI V 250mV/DI V 250mV/DI V 0.125UI/DIV AT 1.65Gbps UI/DIV AT 1.65Gbps 6. TP2 RX 20m 2AWG UI/DIV AT 1.65Gbps 8. TP3 RXEQ 12dB 20m 2AWG

10 T A 27AVCC 3.3V VTTI 3.3V VTTO 3.3V DVCC 3.3V AMUXVCC 5V AVEE 0V DVEE 0V1000mV TMDS 50Ω 3.3V PRBS Gbps HDMI CABLE DIGITAL PATTERN GENERATOR AD8191 EVALUATION BOARD SERIAL DATA ANALYZER SMA COAX CABLE REFERENCE EYE DIAGRAM AT TP1 TP1 TP2 TP3 9. TX UI/DIV AT 1.65Gbps 10. TP2 TXPE 2dB 12. TP3 TXPE 2dB 2m 30AWG 250mV/DI V 0.125UI/DIV AT 1.65Gbps mV/DI V 250mV/DI V UI/DIV AT 1.65Gbps mV/DI V 0.125UI/DIV AT 1.65Gbps TP2 TXPE 6dB 13. TP3 TXPE 6dB 10m 28AWG

11 T A 27AVCC 3.3V VTTI 3.3V VTTO 3.3V DVCC 3.3V AMUXVCC 5V AVEE 0V DVEE 0V1000mV TMDS 50Ω 3.3V PRBS Gbps m CABLE = 30AWG 5m TO 10m CABLES = 28AWG 15m TO 30m CABLES = 2AWG m CABLE = 30AWG 5m TO 10m CABLES = 28AWG 15m TO 20m CABLES = 2AWG DETERMINISTIC JITTER (UI) Gbps, EQ = 12dB 1080p, EQ = 12dB 720p, EQ = 12dB 80p, EQ = 12dB DETERMINISTIC JITTER (UI) p, PE OFF 720p, PE OFF 1080p, MAX PE 720p, MAX PE 80p, PE OFF HDMI CABLE LENGTH (m) p, MAX PE HDMI CABLE LENGTH (m) JITTER (ps) i 80p 1080i/720p 1080p DJ (p-p) 1.65Gbps (mv) HEIGHT EYE RJ (rms) DATA RATE (Gbps) DATA RATE (Gbps) JITTER (ps) 0 30 (mv) HEIGHT EYE DJ (p-p) RJ (rms) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)

12 ( AD8191 T A 27AVCC 3.3V VTTI 3.3V VTTO 3.3V DVCC 3.3V AMUXVCC 5V AVEE 0V DVEE 0V1000mV TMDS 50Ω 3.3V PRBS Gbps JITTER (ps) DJ (p-p) JITTER (ps) DJ (p-p) 5 RJ (rms) 10 5 RJ (rms) DIFFERENTIAL INPUT SWING (mv) INPUT COMMON-MODE VOLTAGE (V) JITTER (ps) DJ (p-p) 10 RJ (rms) TEMPERATURE ( C) DIFFERENTIAL INPUT T ERMINATION RESISTANCE Ω) TEMPERATURE ( C) % TO 80% (ps) TIME RISE/FALL FALL TIME RISE TIME TEMPERATURE ( C)

13 AD8191 1A D HDMI DVI 1 HDMI/DVI 1 3 TMDS Transition Minimized Differential Signaling TMDS 1.65Gbps 105V HDCP TMDS TMDS AD8191 :1 8:1 2 16:1 13 AD81912 I 2 C 1 I 2 CAD8191 8I 2 C AD8191 RESET AD PP_CH[1:0] Ω3.3V VTTI 100ms 16 RX_PT RX_TO AD8191 IP_xx IN_xx AVEE VTTI 50Ω CABLE EQ 25. 6dB 12dB8 RX_EQ PP_EQ8 AD dB 12dBAD Gbps 202AWG 50Ω3.3V VTTO 26 TX_PTO PP_OTO AD8191 TMDS PC AD8191 TMDS AD8191 HS_EN PP_EN AD8191 OR 50Ω

14 26. AD8191 AD8191 TX_PTO PP_OTO AD8191 PP_OTO HDMI/DVI 20mA TX_OCL PP_OCL PP_OCL 10mA TX_OCL PP_OCL TX_PE PP_PE TMDS AD81913 HS_SM AD8191 :1 HDMI/DVI TMDS 8 HS_CH TMDS 26 PP_CH TMDS AD8191 [8:1] TMDS2 8: HS_CH AD :1 TMDS HS_CH I 2 C AUX_A0 AUX_COM0 AD8191 AMUXVCC DDC AD8191 DDC EDID EEPROM EDID VESA EDIDAD8191 DDC AD8191 DDC 28 AD8191 HDMI/DVI 5V AMUXVCC 5V AUX_COM0 AUX_A0 ½C AUX ½C AUX R AUX VTTO 50Ω 50Ω OPx ONx AVEE DISABLE I OUT

15 DDCAD8191 PIN 18 HDMI CONNECTOR PIN 1 DVI CONNECTOR SOURCE A +5V SOURCE B +5V 10kΩ <50mA PERIPHERAL CIRCUITRY PERIPHERAL CIRCUITRY <50mA 10kΩ PIN 18 HDMI CONNECTOR PIN 1 DVI CONNECTOR +5V INTERNAL (IF ANY) 10MΩ AMUXVCC AD8191 PIN 18 HDMI CONNECTOR PIN 1 DVI CONNECTOR 10kΩ <50mA PERIPHERAL CIRCUITRY PERIPHERAL CIRCUITRY <50mA 10kΩ 28. AMUXVCC +5V SOURCE C +5V SOURCE D PIN 18 HDMI CONNECTOR PIN 1 DVI CONNECTOR AD81913 AUX_SM AD8191 :1 13 AUX_CH 27 PP_CH AD8191 [8:1] 28: AUX_CH AD819116:1 TMDS AUX_CH

16 AD RESET RESET 3.3VAD AD AD8191I 2 C AD8191 I 2 C I2C_SCL I2C_SDA 2. AD81917 [1001] 3I2C_ADDR2 I2C_ADDR1 I2C_ADDR0 LSB MSB 3. 0 I2C_SCL. AD MSB 6. AD MSB 8. AD a. I2C_SCL I2C_SDA 29 9b. I2C_SCL I2C_SDA 2 9c. I2C_SCL I2C_SDA 2 9d. I2C_SCL I2C_SDA 8 5 * GENERAL CASE I2C_SDA START FIXED PART ADDR ADDR R/W ACK REGISTER ADDR DATA STOP ACK ACK EXAMPLE I2C_SDA *THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP I 2 C

17 I2C_SCL GENERAL CASE I2C_SDA EXAMPLE I2C_SDA START FIXED PART ADDR ADDR R/W ACK REGISTER ADDR ACK SR FIXED PART ADDR I 2 C ADDR R/W ACK DATA ACK STOP AD8191 I 2 C AD8191 I 2 C I2C_SCL I2C_SDA 2. AD81917 [1001] 3I2C_ADDR2 I2C_ADDR1 I2C_ADDR0 LSB MSB AD MSB 6. AD I2C_SCLI2C_SDA Sr 8. 2AD81917 [1001]3I2C_ADDR2 I2C_ADDR1 I2C_ADDR0 LSB MSB AD AD MSB 12. AD a. I2C_SCL I2C_SDA 30 13b. I2C_SCL I2C_SDA 2 13c. I2C_SCL I2C_SDA 2 13d. I2C_SCL I2C_SDA 8

18 AD8191PP_EN PP_CH[1:0] PP_EQ PP_PRE[1:0] PP_OTO PP_OCL 1 2 AD8191 5

19 I 2 C I2C_SDA I2C_SCL AD8191I2C_ADDR2 I2C_ADDR1 I2C_ADDR0 3.3V 10V 0 AD I 2 C Name Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit 2 Bit 1 Bit 0 Addr. Default High Speed High High speed switching High speed source select 0x00 0x0 Device speed mode select Modes switch enable HS_EN HS_SM[1] HS_SM[0] HS_CH[3] HS_CH[2] HS_CH[1] HS_CH[0] Auxiliary Auxiliary Auxiliary switching Auxiliary switch source select 0x01 0x0 Device switch mode select Modes enable AUX_EN AUX_SM[1] AUX_SM[0] AUX_CH[3] AUX_CH[2] AUX_CH[1] AUX_CH[0] Receiver High speed 0x10 0x01 Settings input termination select RX_TO Input Source A and Source B : input termination pulse-on-source switch select 0x11 0x00 Termination (disconnect termination for a short period of time) Pulse 1 RX_PT[7] RX_PT[6] RX_PT[5] RX_PT[] RX_PT[3] RX_PT[2] RX_PT[1] RX_PT [0] Input Source C and Source D: input termination pulse-on-source switch select 0x12 0x00 Termination (disconnect termination for a short period of time) Pulse 2 RX_PT[15] RX_PT[1] RX_PT[13] RX_PT[12] RX_PT[11] RX_PT[10] RX_PT[9] RX_PT[8] Receive Source A and Source B: input equalization level select 0x13 0x00 Equalizer 1 RX_EQ[7] RX_EQ[6] RX_EQ[5] RX_EQ[] RX_EQ[3] RX_EQ[2] RX_EQ[1] RX_EQ[0] Receive Source C and Source D: input equalization level select 0x1 0x00 Equalizer 2 RX_EQ[15] RX_EQ[1] RX_EQ[13] RX_EQ[12] RX_EQ[11] RX_EQ[10] RX_EQ[9] RX_EQ[8] Transmitter High speed output High speed High speed 0x20 0x03 Settings pre-emphasis level select output termin output current ation select level select TX_PE[1] TX_PE[0] TX_PTO TX_OCL HS_ENTMDS 6. HS_EN HS_EN 0 1 HS_CH[3:0]TMDS 8. [:1] HS_CH[3:0] O[3:0] XX00 A[3:0] A XX01 B[3:0] B XX10 C[3:0] C XX11 D[3:0] D HS_SM[1:0]TMDS 7. HS_SM HS_SM[1:0] 00 [:1] 01 2 [8:1] 10 1 [16:1] 11 HS_SM[1:0]

20 9. 2 [8:1] HS_CH[3:0] O[3:2] O[1:0] X000 A1 A0 A0 A1 X001 A3 A2 A2 A3 X010 B1 B0 B0 B1 X011 B3 B2 B2 B3 X100 C1 C0 C0 C1 X101 C3 C2 C2 C3 X110 D1 D0 D0 D1 X111 D3 D2 D2 D [16:1] HS_CH[3:0] O[3:0] 0000 A0 A A1 A A2 A A3 A B0 B B1 B B2 B B3 B C0 C C1 C C2 C C3 C D0 D D1 D D2 D D3 D3 AUX_EN 11. AUX_EN AUX_EN 0 1 AUX_SM[1:0] 12. AUX_SM[1:0] AUX_SM[1:0] 00 [:1] 01 2 [8:1] 10 1 [16:1] 11 AUX_SM[1:0] AUX_CH[3:0] 13. [:1] AUX_CH[3:0] AUX_COM[3:0] XX00 AUX_A[3:0] A XX01 AUX_B[3:0] B XX10 AUX_C[3:0] C XX11 AUX_D[3:0] D

21 1. 2 [8:1] AUX_CH[3:0] AUX_COM[3:2] AUX_COM[1:0] X000 AUX_C0 AUX_A0 A0 C0 X001 AUX_C1 AUX_A1 A1 C1 X010 AUX_C2 AUX_A2 A2 C2 X011 AUX_C3 AUX_A3 A3 C3 X100 AUX_D0 AUX_B0 B0 D0 X101 AUX_D1 AUX_B1 B1 D1 X110 AUX_D2 AUX_B2 B2 D2 X111 AUX_D3 AUX_B3 B3 D [16:1] AUX_CH[3:0] AUX_COM[3:0] 0000 AUX_A0 A AUX_A1 A AUX_A2 A AUX_A3 A AUX_B0 B AUX_B1 B AUX_B2 B AUX_B3 B AUX_C0 C AUX_C1 C AUX_C2 C AUX_C3 C AUX_D0 D AUX_D1 D AUX_D2 D AUX_D3 D3

22 RX_TOTMDS 16. RX_TO 1 2 RX_EQ[X]TMDS X 19. RX_EQ[X] RX_TO RX_EQ[X] RX_PT[X]TMDSX 17. RX_PT[X] RX_PT[X] 0 TMDS X 1 100ms TMDS X 18. RX_PT[X] RX_PT[X] Bit 0 Bit 1 Bit 2 Bit 3 Bit Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 1 Bit 15 TMDS B0 B1 B2 B3 A0 A1 A2 A3 C3 C2 C1 C0 D3 D2 D1 D0 0 6dB 1 12dB 20. RX_EQ[X] RX_EQ[X] Bit 0 Bit 1 Bit 2 Bit 3 Bit Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 1 Bit 15 TMDS B0 B1 B2 B3 A0 A1 A2 A3 C3 C2 C1 C0 D3 D2 D1 D0 TX_PE[1:0]TMDS TMDS 21. TX_PE[1:0] TX_PE[1:0] 00 0dB 01 2dB 10 db 11 6dB TX_PTOTMDS 22. TX_PTO TX_PTO 0 1 TX_OCLTMDS 23. TX_OCL TX_OCL 0 10mA 1 20mA

23 PP_EN PP_CH[1:0] PP_EQ PP_PRE[1:0] PP_OTO PP_OCL 3.3V 10V 0 2. Name Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit 2 Bit 1 Bit 0 High Speed High speed High speed switching High speed source select Device Modes switch enable mode select (quad) PP_EN PP_CH[1] PP_CH[0] Auxiliary Device Auxiliary Auxiliary switching Auxiliary switch source select Modes switch enable mode select (quad) Receiver Settings Input Termination Pulse PP_CH[1] PP_CH[0] Source A and Source B input termination pulse-on-source switch select (termination always on) Input term. on/off select (termination always on) 1 Input Termination Pulse 2 Source C and Source D input termination pulse-on-source switch select (termination always on) Receive Equalizer 1 Receive Equalizer 2 Source A and Source B input equalization level select PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ Source C and Source D input equalization level select PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ Transmitter Output pre-emphasis Output Output current level Settings level select termination select on/off select PP_PE[1] PP_PE[0] PP_OTO PP_OCL TMDS PP_ENTMDS 25. PP_EN PP_EN 0 1 PP_CH[1:0]TMDS 26. PP_CH[1:0] O[3:0] 00 A[3:0] A 01 B[3:0] B 10 C[3:0] C 11 D[3:0] D PP_CH[1:0] 27. PP_CH[1:0] AUX_COM[3:0] 00 AUX_A[3:0] A 01 AUX_B[3:0] B 10 AUX_C[3:0] C 11 AUX_D[3:0] D

24 TMDS 1 2 TMDS 1 2 PP_EQTMDS TMDS PP_EQ PP_EQ 0 6dB 1 12dB PP_PE[1:0]TMDS TMDS 29. PP_PE[1:0] PP_PE[1:0] 00 0dB 01 2dB 10 db 11 6dB PP_OTOTMDS TMDS 30. PP_OTO PP_OTO 0 1 PP_OCLTMDS TMDS 31. PP_OCL PP_OCL 0 10mA 1 20mA

25 31. AD8191 TMDS AD8191 AD8191TMDS TMDS HDMI/DVI :1 HDMI 1.2a AD8191 HDMI/DVI AD8191 HDMI/DVI AVR 31 AD8191 AD8191 PC AVR AD AD819112dB 6dB TMDS PC AD8191 AD8191 HDMI AD8191 HDMI/DVI PC AD8191 AD8191 AD8191 AD8191 AD8191 AD dB 12dBAD Gbps 1080p 20 2AWG HDMI

26 HDMI/DVI HDMI AD dB PC AD8191HDMI DVI 2 PC AV HDMI/DVI 1.65Gbps 1.65Gbps TMDS 100W AD W HDMI TMDS HDMI HDCP 1 DDCEDID HDCPI2CCEC Consumer Electronics Control HPD Hot Plug Detect I2C TMDS HDMI/DVI TMDS DVI 3 RGB HDMI DVI 1 AV TMDS 1/10 AD8191 TMDS TMDS p n AD8191 AD A0 B0 C0 D0 AD8191 TMDS TMDS PC TMDS TMDS AD8191 RFPC TMDS TMDS PC PC 2 p n 100W 2 PC TMDS 1 AD8191 AD8191 PC TMDS

27 DCD p n 100Ω np 10 TMDSA B C D FR0.05 TMDS PC FR ISI TMDS 2 PC PC 100Ω 2 100Ω 100Ω TMDS AD819150Ω PC TMDS AD8191TMDS PC AD8191 TMDS HDMI/DVI CEC HPD 2 DDC DDC2SDA SCL AD8191 TMDS PC PC HPD CEC DDCAD8191 DDC 100kHz I 2 CDDC 100kHz I 2 C HDMI 1.2aHDMI SDA SCL50pF 50pFHDMI PCAD8191 CEC 100pF PC HDMI PC CECDDC PC 32 AD8191

28 3W W 3W AD SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) AVCC/AVEE VTTI/AVEE VTTO/AVEE DVCC/DVEE AMUXVCC/DVEE PCB DIELECTRIC LAYER : SIGNAL (MICROSTRIP) SILKSCREEN REFERENCE LAYER RELIEVED UNDERNEATH MICROSTRIP AVCC/AVEE 3.3VDVCC/DVEE 3.3V AD8191VTTI/AVEE 3.3V 25 VTTO/AVEE 3.3V 26 AMUXVCC/DVEE 3.3 5V DDC 5V I 2 C5V DVEE AMUXVCC HPD DC EDID AD81911 AD Ω 27 AD8191 AD8191PC HDMI/DVIAD8191 AD8191 AMUXVCC 28 AD8191 TMDS PC TMDS AVEE DVEE AVCC DVCC VTTI VTTO3.3V AMUXVCC 5V AD8191 AVCC DVCC VTTI VTTO 3.3V 0.01µF 33 RECOMMENDED EXTRA ADDED INDUCTANCE NOT RECOMMENDED

29 AD V pF pF 20.01µF 1.7µF3.3V AD8191 AMUXVCC 3 AD8191 DECOUPLING CAPACITORS AUXILIARY LINES TMDS TRACES AD8191

30 1.60 MAX SQ PIN SEATING PLANE VIEW A ROTATED 90 CCW COPLANARITY VIEW A TOP VIEW (PINS DOWN) 0.50 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MS-026-BED SQ A D /06(0)-J LQFP ST-100 mm Package Ordering Model Temperature Range Package Description Option Quantity AD8191ASTZ 1 0 to Lead Low Profile Quad Flat Package [LQFP] ST-100 AD8191ASTZ-RL 1 0 to Lead Low Profile Quad Flat Package [LQFP], Reel ST-100 1,000 AD8191-EVAL Evaluation Kit 1Z I 2 CI 2 C I 2 C I 2 C