User-defined Logic Application Memory Manager (Replacement) Application Specific Prefetcher (ASP) Application Kernel On-chip RAM (BRAM) On-chip RAM I/

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1 RTL 1,2,a) 1,b) CPU Verilog HDL RTL 1. CPU GPU Verilog HDL VHDL RTL HDL Vivado HLS Impulse C CPU 1 2 a) takamaeda@arch.cs.titech.ac.jp b) kise@cs.titech.ac.jp RTL RTL RTL Verilog HDL RTL 2. 1 HDL 1

2 User-defined Logic Application Memory Manager (Replacement) Application Specific Prefetcher (ASP) Application Kernel On-chip RAM (BRAM) On-chip RAM I/O I/O s s User-defined Logic Application I/O s On-chip RAM 3 3 (ASP: Application Specific Prefetecher) 2

3 5 Preprocess (Resolving macros) Lexical Analysis (Separating into tokens) Parse (AST generation) 4 Source Codes Module Analysis (Module / Input / Output / Inout / Parameter) Signal Analysis (Reg / Wire / Localparam) Bind Analysis (dataflow generation from =/<= assignments) Definition Tree Definition Tree Control Flow Analysis (Constructing FSM) Memory Access Timing Analysis Memory Address Analysis (Data Flow Analysis) Generating Definition Tree of Prefetcher Combining Trees of Application and Prefetcher Generating RTL in Verilog HDL Source Code with Prefetcher 3. RTL 3.1 RTL RTL RTL 5?? RTL Verilog HDL (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11), (12) RTL Verilog HDL (7) (8) (9) Python cnt 4 cnt cnt cnt 1 4 cnt 4 CPU 4. Verilog HDL 3

4 情報処理学会研究報告 100.0% % 96.9% Base Prefetch 80.0% Hit rate! Cycle! % 40.0% 20.0% % 0 Base Prefetch (a) 実行サイクル数 図 8 (b) キャッシュヒット率 実行サイクル数とキャッシュヒット率 Read サイクルレベルのタイミングシミュレータを VPI (Verilog Programming Interface) を介して HDL シミュレーション に組み込み使用した キャッシュの構成は ラインサイズ を 64 バイト ウェイ数を 4 キャッシュ容量を 16K バイ ト アクセスレイテンシを 1 とした メインメモリには アクセスレイテンシは 16 サイクル固定としたシンプルな モデルを用いた ベクター加算の扱うデータのメモリフッ トプリントは 96K バイトとした 1 回のベクター加算の処 Write 理には 8 サイクルのレイテンシを要するもとして 演算は パイプライン化されていないものとした 図 8(a) に基準のアプリケーションの実行サイクル数と プリフェッチャーを用いた場合の実行サイクル数を示す また 図 8(b) に両者のキャッシュヒット率を示す プリ フェッチャーの導入により 2.1%の性能向上を達成した またキャッシュヒット率が 3.1%向上した 性能向上率が Source of Address 伸び悩んだ理由としては キャッシュが許可するアウトス タンディングミスの数を 1 としたため プリフェッチリ クエストが後続の読み出しを妨害したことと 今回のプリ 図 6 Verilog HDL で記述したメモリアクセスを制御する状態遷移 フェッチ対象が ループ中の同状態における次回のアクセ コード例 ス先であったため 時系列において後続のリクエストに対 する先行読み出しが行えなかったことなどが挙げられる 前者を回避するには アプリケーションカーネルのリクエ ストを優先し カーネルからリクエストが発行された場合 には プリフェッチャー側の処理をアボートするなどの処 置を施すことなどが必要である 後者を回避するには 時 系列順に次のアクセスを対象としてプリフェッチするよう なプリフェッチャーの構成を検討する必要がある 5. 関連研究 向けのメモリシステムの最適化の研究としては Samuel ら [2] による 高位合成言語で記述されたカーネル 図 7 生成されるプリフェッチ用コード例 のコースコードを解析し オフチップ S へのメモリ アクセスを並べ替えることにより メモリバンド幅を有効 単なベンチマークを用いて 提案手法による性能向上の度 利用する方式や Eric ら [3] による抽象度の高いメモリモ 合いを評価する デルを用いてアプリケーションを記述し 外部メモリとの 性能およびキャッシュヒット率を Icarus Verilog[1] を用 カーネルの間にキャッシュとデータ転送機構を自動的に挿 いてシミュレーションにより評価する ベンチマークには 入するフレームワークの CoRAM などが挙げられる 前者 ベクター加算を用いた キャッシュには C++で記述した は 高位合成系をターゲットしており またループ中のイ 2013 Information Processing Society of Japan 4

5 SMT [4], [5] [4] Lu, J., Das, A., Hsu, W.-C., Nguyen, K. and Abraham, S. G.: Dynamic Helper Threaded Prefetching on the Sun UltraSPARC CMP Processor, Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture, MICRO 38, Washington, DC, USA, IEEE Computer Society, pp (online), DOI: /MI- CRO (2005). [5] Kamruzzaman, M., Swanson, S. and Tullsen, D. M.: Inter-core prefetching for multicore processors using migrating helper threads, Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems, ASPLOS 11, New York, NY, USA, ACM, pp (online), DOI: / (2011). 6. Verilog HDL RTL (CREST) [1] Williams, S. and Baxter, M.: Icarus verilog: opensource verilog more than a year later, Linux J., Vol. 2002, No. 99, pp. 3 (online), available from (2002). [2] Bayliss, S. and Constantinides, G. A.: Optimizing S bandwidth for custom loop accelerators, Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, 12, New York, NY, USA, ACM, pp (online), DOI: / (2012). [3] Chung, E. S., Hoe, J. C. and Mai, K.: CoRAM: an infabric memory architecture for -based computing, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, 11, New York, NY, USA, ACM, pp (online), DOI: / (2011). 5

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