Thesis.dvi

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1 25 (412M528)

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4 Abstract Increasing power consumption has been becoming a major concern not only for mobile computing but also high-performance computing, and processors are required to achieve both low-energy and high-performance at the same time. In particular, it is important to reduce leakage energy consumed in a cache memory because power dissipated by leakage current is a dominant factor in deep submicron technologies and the cache memory dissipates a large amount of leakage energy. To achieve highperformance and low-energy simultaneously, a variable level cache (VLC) is proposed. The VLC dynamically varies the cache capacity according to required cache capacity by running program. If the VLC detects that the current running program does not need large cache memory, half of the cache memory is put into standby mode, and is virtually treated as a lower level exclusive cache. In this way, the VLC succeeded in reducing leakage energy without performance degradation. To reduce more energy consumption this paper proposes two novel approaches for VLC. As the first approach, this paper devises a novel algorithm to control VLC. The improved VLC can expand sleep mode area to 75% of the cache. As a result, this approach can reduce 18% energy consumption compared with the previous VLC. However, if the improved VLC incurs increase in its dynamic energy consumption. The increase in dynamic energy consumption is caused by increasing the number of extra access which accesses the data moved to incorrect place due to the behavior of VLC. To solve this problem, this paper proposes a second approach. As the second approach, this paper focuses on unnecessary accesses which is put on incorrect place. This approach memorizes detailed place that has the data in the extra access. As a result, this second approach further reduce 18% dynamic energy consumption compared with the first approach because it minimizes the dynamic energy of extra access. According to simulation results of these two approaches, proposed VLC can improve 34% energy-delay product compared to the previous VLC.

5 DRI DRI DRI (Exclusive Cache) i

6 ii 34

7 DRI DRI DRI : NoD ED :VSL Bitmap iii

8 iv

9 1 ( ) 1 [6][7] % 75% 18% 1

10 2 18% (ED ) 34%

11 High Speed CPU Register L1-Cache L2-Cache Large Capacity MainMemory 2.1: % ( 2.1 L2 ) 3

12 00101 Accessed Address Tag Index 001 Set Way 1 Way 2 Way 3 Way Hit/Miss + 2.2: SRAM SRAM CPU Tag(00101) Index(001) Index Set Set(001) Tag( ) 4

13 Tag(00101) Set Tag Tag Set Tag Tag 2.3 ( ) % 2.4 5

14 2.3: 2.4: 6

15 Drowsy Cache [1][2] Drowsy Cache NUAL [3] NUAL [4] LRU 1 NUAL 3. 1 DRI [5] 7

16 DRI DRI 3.1 DRI DRI 3.5 DRI DRI (interval) (miss counter) (miss-bound) 256KB 128KB 64KB 32KB 3.6 DRI (size mask) DRI SRAM DRI 8

17 address tag + index offset DRI-CACHE resizing range size-bound min size size mask: masked index upsize v tag data block miss count > miss-bound? miss count < miss-bound? downsize upsize compare miss count downsize miss miss counter yes end of interval? miss-bound 3.5: DRI SRAM DRI DRI SRAM Active Active Active Shutdown Active Shutdown Shutdown Shutdown Shutdown Shutdown Full 1/2 1/4 1/8 3.6: DRI 9

18 DRI DRI 3.2 DRI [6] [7] DRI DRI 1 [8] [9] DRI

19 DRI Cache VLC Cache Active L2 Active L2 Size Change Mode Change Active Half L2 Shutdown Write Back Active Half L2 Sleeping Pseudo L3 Holding Data Data Swap Buffer 3.7: DRI 256KB L2 128KB L3 L3 3.8 DRI (re-access unit) (buffer) L2 L3 L2 L3 L3 L2 L3 11

20 address tag + index offset CACHE MEMORY resizing range size-bound min size size mask: masked index v tag data block mode controller miss counter miss CPU re-access unit victim buffer 3.8: (Exclusive Cache) AMD L1 L2 L1 128KB L2 256KB L2 L2 L1 3.9 Normal Cache K L1 LRU L2 L1 L2 L2 256K 3.9(B) L1 L2 3.9(C) L2 3.9(D) L2 ( 3.9(4)) L1 L2 ( ) =384K 12

21 L1Cache Normal Cache A B C D A B C D E F Read K Exclusive Cache A B C D E F G H I J (A) Victim Buffer A B C E F G H I J (B) Victim Buffer D G H I J K L L2Cache K L N M O P K L N M O P (C) (D) A B C K A B C K A B C K A B C D E F E F G H I J Victim Buffer E F G H I J Victim Buffer D G H I J K L D L N M O P L N M O P 3.9: DRI 3.8 DRI L2 L L3 L3 L3 L3 L2 L3 L2 L3 13

22 index tag L2 LA LB 3.10: [10] 14

23 (corresponding set) NoD NoD 1 n different log 2 ( ) 16way A0-1 A1-4 banka B0-1 B1-4 bankb B0-1 A0-2 banka B A NoD A0-2 B 10 NoD LRU 15

24 banka index 0 0 A1 B1 A2 A3 0 1 B2 A4 B3 A5 corresponding set bankb index B4 B5 A6 B B7 A7 A8 B8 2 ignore n_different ignore n_different 3.11: 3.12: 30% 16

25 4 [6][7] 4.1 NUAL DRI [10] DRI L1 L2 E T = E T (1) [11] [12] 17

26 Energy Consumption W W/2 E1 E1 = W T/2 = WT/2 E2 = W/2 T = WT/2 E1 = E2 E2 0 0 T/2 T Execution Time 4.13: L2 2 E dynamic = E access + E wakeup (2) (2) E access E access = E one access N access (3) E one access N access ( L3) 3. L3 18

27 N access E wakeup = E one wakeup N way N wakeup (4) (2) E wakeup E one wakeup N way N wakeup SRAM E static = E set leak N set N way Cycles Freq (5) N set Cycles Freq CPU 1 E set leak E set leak = R sleep E sleep leak + (1 R sleep ) E active leak (6) R sleep E sleep leak E active leak E dynamic = E access E static = E active leak E P circuit = E controller N access + E buffer N wakeup (7) E P circuit L2 E controller 1 E buffer 19

28 4 Verilog HDL 0.1% L2 DRAM CACTI % 4.3 L2 M5[14] L2 L2 L2 4.4 L2 L KB L2 L2 256KB L3 256KB L2 20

29 4.1: L1 -cache 32KB(64B/entry, 1way, 512entry) L1 -cache 32KB(64B/entry, 1way, 512entry) L2 cache 512KB(64B/entry, 4way, 2048entry) L1 cache L2 cache 1 cycle 10 cycle 250 cycle 10cycle 128KB L3 128KB L2 L4 256KB L2 L (2 13 ) 30% 4.2 SPEC2000 [15] 7 21

30 4.2: ammp bzip2 crafty equake gap gcc gzip mcf vpr C FPGA 5.14: 5 [10] L2 50% [16] NoD 22

31 5.15: : NoD 4 NoD 5.15 NoD2 NoD1 NoD2 NoD A0-4 A C NoD1 C B 10 A0-4 A NoD A NoD C NoD B 01 A0-4 B0-3 NoD NoD 23

32 NoD NoD log(#way) , 5.17, 5.18 ED Previous Proposed % Mcf 19% Bzip2, Gap, Gzip, Vpr Ammp, Crafty, Equake, Gcc % % 22% 170% 24

33 5.16: 6 [17] [10] 25

34 5.17: 5.18: ED 26

35 CMOS 170% 6.2 NoD NoD 27

36 6.19: :VSL Bitmap 6.19 NoD Violated Set Lines Bitmap(VSL Bitmap) VLS Bitmap 6.19 A VLS 1 Bitmap Way 1 10 Way 1 10 Way 1 VSL Bitmap 512Kb 4-way 0.01% 28

37 , 6.21, 6.22 NoD Counter 5 VSL Bitmap VSL bitmap 6.20 NoD Counter VSL Bitmap 1% VSL Bitmap NoD Counter Gzip VSL Bitmap 34% NoD counter 11% Bzip2 Gap Mcf Vpr NoD Counter 35% VSL Bitmap 8% 6.22 VSL Bitmap NoD Counter 18% Mcf 37% Bzip2 Gap Mcf Vpr VSL Bitmap VSL Bitmap NoD Counter 29

38 6.20: 7 50% 75% 18% 18% (ED ) 34% 30

39 6.21: 6.22: 31

40 32

41 33

42 [1] K. Flautner, N.S. Kim, S. Martin, D. Blaauw, and T. Mudge, Drowsy Cache: Simple Techniques for Reducing Leakage Power, Proc. of the 29th Int. Symp on Computer Architecture, pp , May [2] N.S. Kim, K. Flautner, D. Blaauw, and T. Mudge, Drowsy Instruction Caches; Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction, Proc. of the Int. Symp. on Microarchitecture, pp , [3] Akihito Sakanaka Toshinori Sato Reducing Static Energy of Cache Memories via Prediction-Table-less Way Prediction International Workshop on Power And Timing Modeling, September [4], VLD , ICD , pp.13-18, March [5] S.H. Yang, M.D. Powell, B. Falsafi, K. Roy, and T.N. Vijaykumar, An Integrated Circuit / Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches, Proc. of the 7th Int. Symp. on High-Performance Computer Architecture, pp , February [6],, 2007-ARC-174, pp , August [7] CPSY , pp.7-12 December [8] Ying Zheng Brian T Davis Matthew Jordan Performance Evaluationof Exclusive Cache Hierarchies IEEE International Symposium of Performance Analysis of Systems and Software ISPASS pp.89-96, September

43 [9] Advanced Micro Deices AMD, (CurrentJune 2003). [10] ACS pp48-60 August [11] 17, pp , April [12] Drowsy, 2006-ARC-170, pp.37-41, December [13] CACTI 5.3 Shyamkumar Thoziyoor, Naveen Muralimanohar, Jung Ho Ahn, and Norman P. Jouppi [14] Nathan L. Binkert Ronald G. Dreslinski Lisa R. Hsu Kevin T. Lim Ali G. Saidi Steven K. Reinhardt The M5 Simulator: Modeling Networked Systems [15] SPEC -Standard Performance Evaluation Corporation-, URL: [16] Ko Watanabe, Takahiro Sasaki, Kazuhiko Ohno and Toshio Kondo IMPROVEMENT OF WRITEBACK MECHANISM OF VARI- ABLE LEVEL CACHE ITC-CSCC2012 July [17] Ko Watanabe, Takahiro Sasaki, Kazuhiko Ohno and Toshio Kondo Reducing Dynamic Energy of Variable Level Cache, Int. Journal of Comp. and Elec. Eng., vol.5, no.6, pp , December

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