1. Introduction SOI(Silicon-On-Insulator) Monolithic Pixel Detector ~µm) 2

Size: px

Start display at page:

Download "1. Introduction SOI(Silicon-On-Insulator) Monolithic Pixel Detector ~µm) 2"

えみてっちがわら
7 years ago
Views:

1 Introduction TEG 1

2 1. Introduction SOI(Silicon-On-Insulator) Monolithic Pixel Detector ~µm) 2

3 SOI 3

4 SOI : Smart Cut (UNIBOND) by SOITEC Low-R Hi-R 4

5 3µm Process! 5

6 2. SOI SOI 0.15µm 7 ~ --> BOX (Burried Oxide) n+, p+ Implant, TCAD --> 10 TEG Submit SOI SiO2 BOX wafer) p+ n+ 250~350um Al pixel pixel 6

7 TCAD Simulation --> Tsuboyama, (Hazumi) Talk n+ guard ring p+ stop Simulation Model n+ pixel p substrate 7

8 3. n+, p+ implant --> SOI Tr Source/Drain --> 650um 250~350um --> Implant AL Thermal Donor TD generation p or n --> p-wafer, n-wafer p-stop, Guard Ring Back Gate SOI Tr --> I/O Guard Ring SiO 2 ~10MV/cm 500V Metal 1 5MV/cm --> Metal 1 Floating? 8

9 SOI Pixel Process step flow After Gate stack formation (with extension and sidewall formations) SOI Box Handling wafer 650um Box Window photo lithography and etching Handling wafer S/D Implantation followed by S/D annealing and Salicidation Handling wafer p+ n+ 1 st ILD filling and CMP planarization (after Salicide formation) Handling wafer p+ n+ 9

10 Contact etching Handling wafer p+ n+ Contact plug filling and 1 st Metal formation Handling wafer p+ n+ 650um 3 ~ 5Metal formation followed by Backside polishing and Al coating Handling wafer p+ n+ 250~350um Al pixel pixel 10

11 Thermal Donor Generation in high resistivity wafer 11

12 TD generation on High Resistivity Wafer J. Harkonen et. al., Proton irradiation results of p+/n-/n+ Cz-Si detectors processed on p-type boron-doped substrates with thermal donor-induced space charge sign inversion, NIM in Press. n-type p-type 12

13 Space Charge Sign Inversion (SCSI) n-type Si p-type Si Depletion Voltage SCSI Depletion Voltage TD Generated 13

14 Effect of Back Gate Voltage BOX 100 Tr Substrate 14

15 15

16 Detector Edge Side View 16

17 TEG Design status Nick Name Service deadline Contents Principal Designer VDECTEG1 VDEC 10/7 Preamp, TOT, Comparator, Active Feedback, etc. Ikeda Completed! --> Ikeda Talk RadTEG1p shuttle 10/14 Pixel TEG, Tr TEG, Ring Oscillator etc. Arai RadTEG1n Several cells (Tr TEG, Ring Osc.) are completed. PixTEG1p shuttle 10/14 32x32 Pixel Array Arai PixTEG1n Several cells (Adr decoder, Buffer...) are completed. StripTEG1p StripTEG1n shuttle 10/14 Short Strip Sensor Prototype (TCAD Verification --> Hazumi, Tsuboyama Talk Hazumi Tsuboyam HawaiTEG1p HawaiTEG1n shuttle 10/14 Imaging Hard X-ray Compton Polarimeter SOI Sensor --> Gary, Elena Varner 17

18 VDECTEG1 18

19 Pixel TEG 19

20 IHXCP(Imaging Hard X-Ray Compton Polarimeter) U of Hawaii SLAC Pixel Size 200 x 200 µm Pixel Array (Detector) Size 2.1 x 2.1 cm Noise <=10 e- Global Trigger Rate 500 Hz Single Pixel Rate 10? mili-hz Trigger Threshold 0.5 kev Trigger Latency 1-2 µs Power 200 µw/pixel Total Array Power 2 W ADC precision 12 bits 20

21 IHXCP TEG 4x4 array IHXCP pixels Digitizing Trigger/ Encoding 21

22 SOI Pixel 2.5mm TEG 1 TEG 4 x 2 Thermal Donor Back Gate TEG ( 22

Microsoft Word SOIまとめ.doc

Microsoft Word SOIまとめ.doc 19 (SOI Pixel ) 2007.3.31(4.9 revised) [ ] KEK :, JAXA Univ. of Hawaii : Gary Varner, Elena Martin, Stanford Linear Accelerator Center : Hiro Tajima [ ] (KEK) (JAXA) 1. 18 3 (1) SOI (Silicon-On-Insulator)