DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 Gate Gate Source n Drain n Source n BOX Drain n 2 SOI 2 3 TCAD 4 PHITSTCAD (LSI)

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1 DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 28nm UTBB FDSOI SOI 28nm UTBB FDSOI Analysis of Soft Error Rates in a 28nm UTBB FDSOI Structure by DeviceLevel Simulation Shigehiro Umehara Kuiyuan Zhang Masashi Hifumi Jun Furuta Kazutoshi Kobayashi Abstract: The impact of soft errors has been serious with process scaling of integrated circuits. Redundant circuits or SOI strucutes are used for radiation hardened circuits. In this paper, we build a device model and estimate static and dynamic characteristics and the soft error tolerance of 28nm UTBB FDSOI process by devicelevel simulation. The soft error tolerance is decreased by reducing supply voltage or by applying reverse body bias.. Department of Electronics, Kyoto Institute of Technology [] SOI (Silicon On Insulator) SOI (BOX (Buried OXide)) SOI (FD Fully Depleted) SOI BOX UTBB (Ultra Thin Body and Box) UTBB BOX 25 Information Processing Society of Japan 4 c 25 Information Processing Society of Japan

2 DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 Gate Gate Source n Drain n Source n BOX Drain n 2 SOI 2 3 TCAD 4 PHITSTCAD (LSI) LSI [2] [3] [] 2.2 SEE (Single Event Effect) SEE SEU (Single Event Upset) SET (Single Event Transient) [4] SEU MCU (Multiple Cell Upset) [5] NMOS PMOS NMOS 2.3 [6] SOI SOI (Silicon On Insulator) CMOS (BOX Buried OXide) SiO 2 SOI BOX 2 SOI SOI SOI BOX SOI LSI SOI (PDSOI: Partially Depleted SOI) SOI (FDSOI: Fully Depleted SOI) [7] 2.4 UTBB (Ultra Thin Body and BOX) UTBB 3 [8] BOX UTBB (Ultra Thin Body and BOX) FDSOI SOI BOX nm UTBB 25nm BOX 25 Information Processing Society of Japan 42 c 25 Information Processing Society of Japan 2

3 DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 Drain Current [a.u.] SPICE Simulation Device Simulation 3 28nmUTBB [8] Gate Voltage [a.u.] (a) NMOS (a) NMOS Drain Current [a.u.] SPICE Simulation Device Simulation (b) PMOS 4 FDSOI Highk Metal 3. TCAD TCAD 3. 28nm UTBB FDSOI 3D 4 I d V g 5 V gs =V I d V g NMOS, PMOS I d % 2 V in.4ff t LH Gate Voltage[a.u.] (b) PMOS I d V g [a.u.] SPICE[a.u.] t LH.764 t HL % t HL 4.8% 3.2 NMOS LET V.4V LET 6 LET.4V LET V /5 V NMOS PMOS LET 7 NMOS 2MeV PMOS MeV LET V..9 PMOS PMOS 25 Information Processing Society of Japan 43 c 25 Information Processing Society of Japan 3

4 DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 25 LET [MeVcm2/mg] Gate Oxide STI S/D Spacer Substrate Gate [V] 8 PHITS LET [MeVcm2/mg] PMOS NMOS LET [V] LET PMOS 4. PHITSTCAD PHITSTCAD [9] PHYSERD[] PHITSTCAD TCAD PHITS PHYSERD PHITS TCAD 4. PHITS PHITS Particle and Heavy Ion Transport code System 4.2 PHITSTCAD PHITS 8 PHITS 9 Deposit Energy TCAD Deposit charge Deposit Q 5fC Deposit Q MeV Deposit Energy [] LET Deposit Q Deposit Energy Deposit Energy PHITS Deposit Energy Deposit Energy PHITS SER SEU [FIT/Mbit] = A n N SEU F 6 N n () A n PHITS N SEU N n F Flux 4.3 V.4V V 2.FIT/Mbit.4V 48.2FIT/Mbit V V PMOS 25 Information Processing Society of Japan 44 c 25 Information Processing Society of Japan 4

5 DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 Area of Neutrons.9um.2um 5 4 Nuclear Reaction Si Secondary Ion SiO2 (4um) SER [FIT/Mbit] 3 2 Sensitive Volume Si (5um) um 2.4um 9 PHITS [V] Number of Errors Threshould Deposit Energy [MeV] Deposit Energy SER [FIT/Mbit] [V].4V.7FIT/Mbit.33.6V 3.2FIT/Mbit.5.4V V PMOS 5. 28nm UTBB FDSOI V.4V LET No of errors PMOS [V] PMOS LET.9.5 JSPS 5H2677, STARC 25 Information Processing Society of Japan 45 c 25 Information Processing Society of Japan 5

6 DA DA シンポジウム DAS25 Design Automation Symposium 25/8/26 [],,, , (25). [2], SRAM,, , No. 93, pp. 63 7, (25). [3] Y. Tosaka, S. Satoh, T. Itakura, H. Ehara, T. Ueda, GA Woffinden, and SA Wender, Measurement and Analysis of NeutronInduced Soft Errors InsubHalf Micron CMOS Circuits, IEEE Trans. Elec. Dev., Vol. 45, No. 7, pp , (998). [4],,, (24). [5] K. Zhang, J Furuta, K Kobayashi, and H Onodera, Dependence of Cell Distance and Wellcontact Density of MCU Rates by Device Simulations and Neutron Experiments in a 65nm Bulk Process, The conference on Radiation and its Effects on Components and Systems, (23). [6] L. Anghel, D. Alexandrescu, and M. Nicolaidis, Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy, SBCCI, p. 237, (2). [7] Neil H.E. Weste and D. Harris, CMOS VLSI DESIGN A circuts and systems perspective Forth Edition, Addison Wesley, (2). [8] G. Gasiot, D. Soussan, M. Glorieux, C. Bottoni, and P. Roche, SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts, Reliability Physics Symposium, 24 IEEE International, (24), pp. SE.6. SE.6.5. [9] K. Zhang, S Kanda, J. Yamaguchi, J Furuta, and K Kobayashi, Analysis of Soft Error Rates by Supply Voltage in 65nm SOTB and 28nm UTBB Structures by a PHITSTCAD Simulation System, The conference on Radiation and its Effects on Components and Systems, (25, to be presented). [] S. Abe, R. Ogata, and Y. Watanabe, Impact of Nuclear Reaction Models on NeutronInduced Soft Error Rate Analysis, IEEE Trans. Nucl. Sci., Vol. 6, No. 4, pp , (24). [] T. Handa, K Niita, and H Sawamura, Neutroninduced semiconductor soft error simulation using the PHITS Monte Carlo simulator, 23 symposium on nuclear data., (23). 25 Information Processing Society of Japan 46 c 25 Information Processing Society of Japan 6

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