基準電圧源の選択における基本事項

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1 Literature Number: JAJA416

2 Expert tips, tricks, and techniques for powerful designs No David Megaw, Design Engineer... REF REF Dn Dn1 Dn Dn Dn3 Dn1 D1 Dn Dn3 D1 ADC DAC Figure 1. ADC/DAC

3 national.com / JPN / power LM % 10ppm LM431 (ppm/ C) NEW! LM4050 / 51 LM410 LM4030 / LM413 LM418 LM385, LM85 10 LM % 0.1% 0.5% 1.0% (%) NEW NEW NEW () (%) (ppm/ C) (µa) (µpp) 1.04, 1.5,.048, LM4140 (LDO).5, , 6, 10 30/1(). SO8 1.8,.0,.5, 3.0, LM413 (LDO) 3.3, , 0.1, 0., 0.4, , 0, 30 60/3 () 170 SOT35 LM4030.5, , 0.1, , 0, SOT35 LM410 LM4050/51 LM418 (LDO) (LDO) 1.8,.048,.5, 3.0, 3.3, 4.09, 5 0., 0.5.0,.5, 4.096, 5.0, 8., , 0., ,.0,.5, 3.0, 3.3, , 0., 0.5, /1() 0 SOT35 41 (LM4050) (LM4051) 48 SOT33 75,100 60/3 () 170 SOT35 national.com / JPN / power National Semiconductor Corporation, 008. National Semiconductor, PowerWise, and are registered trademarks of National Semiconductor Corporation. All rights reserved.

4 IN IN IN I LOAD R BIAS I BIAS I LOAD IN GND REF C OUT REF I SHUNT C OUT REF IN BG Q 1 I LOAD R BIAS I BIAS I LOAD R 1 REF R 1 = BG (1 R ) R 1 = BG (1 ) I SHUNT REF R 1 R R C OUT R BG Q C OUT Figure. national.com/jpn/power 3

5 Table 1. 3 IN REF GND REF GND I Q I LOAD I LOAD_MAX IN / GND / IN IN PSRR / 3 T T T REF (T) = REF 1 TC TC TC... 5 C 1 5 C 3 5 C 5 C 4

6 TC TC BOX = 10 ENDPOINTS 6 = 10 6 REF_MAX T REF 5 C REF TMAX REF_MIN T REF 5 C T 1 T REF TMIN MAX T MAX MIN 1 T MIN REF MAX REF (TMAX) REF (5 o C) REF (TMAX) REF MAX REF (TMIN) REF (T MIN) REF MIN REF MIN T MIN 5 o C T MAX T MIN 5 o C T MAX T MIN 5 o C T MAX T APPLICATION T SPECIFICATION Figure 3. TC national.com/jpn/power 5

7 LOAD_REG(ppm/mA) = 10 6 REF ILOAD_MAX REF ILOAD_MIN REF ILOAD_MIN I LOAD_MAX 1 I LOAD_MIN 6

8 LINE_REG = 10 6 REF IN_MAX REF IN_MIN REF IN_MIN IN_MAX 1 IN_MIN national.com/jpn/power 7

9 6 1 LSB(ppm) = 10 NOB NOB : Table. LSB LSBppm

10 TEMP = TC (TMAX TMIN) LOAD = LOAD_REG (ILOAD_MAX ILOAD_MIN) LINE = LINE_REG ( IN_MAX IN_MIN) = ERROR ERROR ERROR GUARANTEED INITIAL_ACCURACY TEMP LOAD LINE LM413A_.5: TEMP LOAD LINE o o o = (10 ppm/ C) (55 C 0 C) = 550 ppm = (10 ppm/ma) (0.5 ma 0 ma) = 60 ppm = (50 ppm/) ( ) = 50 ppm GUARANTEED = (0.05% = 500 ppm) 550 ppm 60 ppm 50 ppm = 1160 ppm ERROR LM413A_.5: THERMAL _HYSTERESIS LONG TERM_STABI LITY LF_ NOISE TOT TOT 6 = 10 = THERMAL _HYSTERESIS LONG TERM_STABILITY Hz Peak to Peak REF 3 (75 ppm) = 5 ppm 3 (50 ppm) = 150 ppm 6 40 μp P = 10 = 96 ppm.5 = 1160 ppm 5 ppm 150 ppm 96 ppm = 1631 ppm LF_ NOISE GUARANTEED THERMAL _HYSTERESIS LONG TERM_STABI LITY LF_NOISE national.com/jpn/power 9

11 1631 ppm TOTAL (LSB) = = 1.7 LSB (10 bit) = 6.7 LSB (1 bit) 6.7 LSB (14 bit) ppm LSB = log ERROR (LSB) (MS) = (PFS) = 0. 8 bit (10 bit) =.7 bits (1 bit) = 4.7 bits (14 bit) 0 bit (10 bit) TOTAL = 1.7 bits (1 bit) = 3.7 bits (14 bit) LM413A_.5: RMS = (550) (500) 760 ppm RMS (LSB) = ppm LSB = log (50) (60) (75) (50) ( 96) = 760 ppm ( ERROR (LSB)) PFS= 0 bit (10 bit) = 1.6 bits (1 bit) = MS= 0 bit (10 bit) = 0.6 bits (1 bit) = = 0.8 LSB (10 bit) = 3.1 LSB (1 bit) = 1.5 LSB (14 bit) TOTAL 3.6 bits (14 bit).6 bits (14 bit) 10

12 ref ref ref ref k Analog Edge/ POWER designer Expert tips, tricks, and techniques for powerful designs No Ricardo Capetillo, Application Engineer power.national.com/jpndesigner signalpath.national.com/jpndesigner No. 114 SIGNAL PATH designer Tips, tricks, and techniques from the analog signalpath experts...13, 5 PowerWise / A/D /A/D Scott Kulchycki, Engineer, Ph. D. x(t) fs x(t) xs(kt) xs(t) 4T 5T 6T 4T 5T 6T T T 3T T T 3T Figure 1: / n x D[k] x D[k] ADC 008, National Semiconductor Corporation. National Semiconductor,, PowerWise, and Signal Path Designer are registered trademarks and Analog Edge is a service mark of National Semiconductor. All other brand or product names are trademarks or registered trademarks of their respective holders. All rights reserved JP

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