N12866N2P-H.PDF

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1 16Mx64bits PC133 SDRAM SO DIMM Based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh (16M x 16bit) /. / 1

2 A0 ~ A12 BA0, BA1 CK0, CK1 CKE0 /S0 /RAS /CAS /WE DQM0 ~ DQM7 DQ0 ~ DQ63 SA0~2 SDA SCL VCC 3.3 VSS WP NC 2

3 No. No. No. No. 1 VSS 2 VSS 71 NC 72 NC 3 DQ0 4 DQ32 73 NC 74 CK1 5 DQ1 6 DQ33 75 VSS 76 VSS 7 DQ2 8 DQ34 77 NC 78 NC 9 DQ3 10 DQ35 79 NC 80 NC 11 VCC 12 VCC 81 VCC 82 VCC 13 DQ4 14 DQ36 83 DQ16 84 DQ48 15 DQ5 16 DQ37 85 DQ17 86 DQ49 17 DQ6 18 DQ38 87 DQ18 88 DQ50 19 DQ7 20 DQ39 89 DQ19 90 DQ51 21 VSS 22 VSS 91 VSS 92 VSS 23 DQM0 24 DQM4 93 DQ20 94 DQ52 25 DQM1 26 DQM5 95 DQ21 96 DQ53 27 VCC 28 VCC 97 DQ22 98 DQ54 29 A0 30 A3 99 DQ DQ55 31 A1 32 A4 101 VCC 102 VCC 33 A2 34 A5 103 A6 104 A7 35 VSS 36 VSS 105 A8 106 BA0 37 DQ8 38 DQ VSS 108 VSS 39 DQ9 40 DQ A9 110 BA1 41 DQ10 42 DQ A10/AP 112 A11 43 DQ11 44 DQ VCC 114 VCC 45 VCC 46 VCC 115 DQM2 116 DQM6 47 DQ12 48 DQ DQM3 118 DQM7 49 DQ13 50 DQ VSS 120 VSS 51 DQ14 52 DQ DQ DQ56 53 DQ15 54 DQ DQ DQ57 55 VSS 56 VSS 125 DQ DQ58 57 NC 58 NC 127 DQ DQ59 59 NC 60 NC 129 VCC 130 VCC Voltage Key 131 DQ DQ DQ DQ61 61 CK0 62 CKE0 135 DQ DQ62 63 VCC 64 VCC 137 DQ DQ63 65 /RAS 66 /CAS 139 VSS 140 VSS 67 /WE 68 NC 141 SDA 142 SCL 69 /S0 70 A VCC 144 VCC 3

4 Note : 1. The serial resistor values of DQs are 10ohms 2. The padding capacitance of termination R/C for CK1 is 10pF 4

5 VSS VIN,VOUT -1.0 ~ 4.6 V VSS VDD,VDDQ -1.0 ~ 4.6 V IOS 50 ma PD 4 W T A 0 ~ 70 T STG -55 ~ 125 MIN TYP. MAX VDD,VDDQ V VIH VDDQ+0.3 V VIL V VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V tr / tf 1 ns Voutref 1.4 V * CL 50 pf 2TTL+50pF 5

6 VCC=3.3V, TA=25, f=1mhz MAX CK CI1 35 pf CKE CI2 30 pf /S CI3 30 pf A, BA CI4 30 pf /RAS, /CAS, /WE CI5 30 pf DQM CI6 15 pf DQ CI/O 15 pf 6

7 VCC=3.3V 0.3V, Ta=0 70 MIN MAX ILI 0V VIN VDD, =0V -4 4 A ILO DOUT, 0V Vout VDD A VOH IOH=-4mA V VOL IOL=+4mA V IDD1 Burst length=1, One bank active trc trc(min),iol=0ma ma IDD2P CKE VIL(max), tck=min - 12 IDD2PS CKE VIL(max), tck= ma - 8 IDD2N CKE VIH(min), /CS VIH(min), tck=min DDV-0.2V or 0.2V ma IDD2NS CKE VIH(min), tck= - 36 IDD3P CKE VIL(max), tck=min - 16 ma IDD3N CKE VIH(min), /CS VIH(min), tck=min ma DDV-0.2V or 0.2V IDD4 tck tck(min), IOL=0mA All banks active ma IDD5 trrc trrc(min), ma IDD6 CKE 0.2V - 12 ma 7

8 VCC=3.3V 0.3V, Ta=0 70 MIN MAX tck ns tch ns tcl ns tac ns toh ns tlz 1 - ns thz ns tsi ns thi ns /RAS trc 67.5 ns Active-Precharge tras K ns Active-Read/Write trcd 20 - ns Precharge-Active trp 20 - ns - tdpl 2 - CLK - tdal 2CLK+20ns - Active(a)- Active(b) trrd 15 - ns tt ns tref - 64 ms 8

9 Serial Presence Detect Hex Value Byte Number Function Described SPD Entry Value 16Mx64 0 Number of SPD bytes Total bytes in Serial PD Memory Type SDRAM 04 3 Number of Row Addresses (without BS bits) 13 0D 4 Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (continued) Module Interface Levels LVTTL 01 9 SDRAM Cycle Time at CL=3 7.5 ns SDRAM Access Time from Clock at CL=3 5.4ns Dimm Config (Error Det/Corr.) none Refresh Rate/Type Self-Refresh, 7.81µs SDRAM width, Primary x Error Checking SDRAM Data Width none Minimum Clock Delay from Back to Back Random Column Address t ccd = 1 CLK Burst Length Supported 1, 2, 4, 8 & full Page 8F 17 Number of SDRAM Banks Supported /CAS Latencies CL = 2, /CS Latencies /CS Latency = /WE Latencies WL = SDRAM DIMM Module Attributes Non Buffered/Non Reg SDRAM Device Attributes: General Vcc tol??10% 0E 23 Minimum Clock Cycle Time at /CAS Latency = 2 10 ns A0 24 Maximum Data Access Time from Clock for CL = 2 6 ns Minimum Clock Cycle Time at CL = 1 Not Supported Maximum Data Access Time from Clock at CL = 1 Not Supported Minimum Row Precharge Time 20 ns Minimum Row Active to Row Active Delay trrd 15 ns 0F 29 Minimum /RAS to /CAS Delay trcd 20 ns Minimum RAS Pulse Width tras 45 ns 2D 9

10 Hex Value Byte Number Function Described SPD Entry Value 16Mx64 31 Module Bank Density (Per Bank) 128 MByte SDRAM Input Setup Time 1.5 ns SDRAM Input Hold Time 0.8 ns SDRAM Data Input Setup Time 1.5 ns SDRAM Data Input Hold Time 0.8 ns Superset Information (May be used in Future) SPD Revision Revision Checksum for Bytes 0-62 B9 64 Manufacturer's JEDEC ID Code Manufacturer's JEDEC ID Code (cont.) Manufacturing Location FF Module Part Number (ASCII) FF PCB Identification Code FF 93 Assembly Manufacturing Date (Year) FF 94 Assembly Manufacturing Date (Week) FF Assembly Serial Number FF Reserved Intel Specification for Frequency Intel Specification /CAS# Latency 8F Unused Storage Location FF 1.78 m 0.76 m 10

11 M1 (AREA B) R Y A (AREA B) N Q L M M2 (AREA A) I H C B A D S (OPTIONAL HOLES) E U1 T U2 A1 (AREA A) F detail of A part W D2 D1 X V ITEM MILLIMETERS A 67.6 A1 67.6±0.15 B 23.2 C 29.0 D 4.6 D1 1.5±0.10 D2 4.0 E 32.8 F 3.7 H 0.8 (T.P.) I 3.3 L 20.0 M 25.4±0.15 M1 3.4 M N 3.8 MAX. Q R2.0 R 4.0±0.10 S f 1.8 T 1.0±0.1 U1 3.2 MIN. U2 4.0 MIN. V 0.25 MAX. W 0.6±0.05 X 2.55 MIN. Y 2.0 MIN. 11

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