プロセッサ・アーキテクチャ

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1 2. NII Nios II Nios II Nios II I/O 2-18 JTAG Nios II ISA ISA Nios II Nios II Nios II 2 1 Nios II Altera Corporation 2 1

2 2 1. Nios II Nios II Processor Core JTAG interface to software debugger reset clock cpu_resetrequest cpu_resettaken JTAG Debug Module irq[31..0] Program Controller & Address Generation Exception Controller Interrupt Controller General Purpose Registers Control Registers Instruction Regions Memory Protection Unit Data Regions Instruction Cache Memory Management Unit Translation Lookaside Buffer Tightly Coupled Instruction Memory Tightly Coupled Instruction Memory Instruction Bus Data Bus Custom I/O Signals Custom Instruction Logic Arithmetic Logic Unit Data Cache Tightly Coupled Data Memory Tightly Coupled Data Memory Nios II ALU MMU MPU JTAG 2 2 Altera Corporation Nios II

3 Nios II Nios II Nios II Nios II Nios II Nios II Nios II 3 JTAG Nios II Nios II Nios II Nios II SOPC Builder Nios II Nios II Altera Corporation 2 3 Nios II

4 Nios II Nios II Nios II ALU ALU 1 2 ALU Nios II ALU ALU ALU ==!= >= < ALU AND OR NOR XOR ALU 0 31 / ALU / ALU / 2 1 Nios II Nios II Nios II 2 4 Altera Corporation Nios II

5 Nios II Nios II ALU Nios II Custom Instruction User Guide Nios II IEEE Std IEEE IEEE / (1) NaN ± ± ±0 Round-to-Nearest Round-toward-Zero Round-toward- + Round-toward- - NaN Quiet Signaling Altera Corporation 2 5 Nios II

6 2 2. IEEE / IEEE IEEE : (1) Nios II IDE IEEE % Nios II Nios II C Nios II 2 reset - cpu_resetrequest - Nios II 1 cpu_resettaken cpu_resetrequest cpu_resetrequest JTAG cpu_resetrequest JTAG cpu_resetrequest 2 6 Altera Corporation Nios II

7 Nios II 1 SOPC Builder Nios II 32 irq0 irq31 32 IQR IQR IRQ ienable status PIE 3 status PIE 1 irq<n> ienable n 1 Nios II 1 Nios II Nios II Altera Corporation 2 7 Nios II

8 32 50 LE f MAX Nios II SOPC Builder Nios II Nios II ALT_CI_EXCEPTION_VECTOR_N : if (ipending == 0) (estatus.pie == 0) then rc else rc 8 ipending ctl4 1 : custom ALT_CI_EXCEPTION_VECTOR_N, rc, r0, r0 : custom ALT_CI_EXCEPTION_VECTOR_N, et, r0, r0 blt et, r0, not_irq : : : : rc R C = rc N = ALT_CI_EXCEPTION_VECTOR_N C N 0x32 Nios II 2 8 Altera Corporation Nios II

9 I/O Nios II I/O Nios II Nios II I/O Nios II Nios II I/O Nios II 1 I/O Avalon-MM Nios II Avalon-MM Nios II Nios II Nios II Nios II Nios II 2 2 Nios II I/O Altera Corporation 2 9 Nios II

10 I/O 2 2. Nios II I/O Nios II Processor Core M Tightly Coupled Instruction Memory 1 Instruction Bus Selector Logic MPU Instruction Regions M Tightly Coupled Instruction Memory N Program Counter Instruction Cache M Avalon Switch Fabric S Memory MMU Translation Lookaside Buffer General Purpose Register File Data Bus Selector Logic Data Cache Bypass Logic Data Cache MPU Data Regions M M Tightly Coupled Data Memory 1 S Slave Peripheral M Tightly Coupled Data Memory N M S Avalon Master Port Avalon Slave Port Nios II Harvard Avalon-MM Avalon-MM Avalon-MM Avalon Memory Mapped Interface Specification 2 10 Altera Corporation Nios II

11 Nios II I/O Nios II Nios II Nios II Nios II 32 Avalon-MM 1 Avalon-MM Avalon-MM f MAX Nios II 32 Nios II Nios II 2-13 Nios II 2-15 Altera Corporation 2 11 Nios II

12 I/O Nios II 32 Avalon-MM 2 4 Nios II 4 Avalon-MM 4 1 Nios II Nios II Nios II 1 / Nios II Avalon 2 12 Altera Corporation Nios II

13 Nios II Nios II SDRAM Nios II Nios II Nios II / / Altera Corporation 2 13 Nios II

14 I/O Nios II 2 K 1 K 2-15 Nios II I/O 31 I/O ldio stioi/o Avalon-MM Nios II Nios II 2 14 Altera Corporation Nios II

15 Nios II Nios II 1 Nios II 1 Nios II DSP Altera Corporation 2 15 Nios II

16 I/O Nios II 3 Nios II MMU - Nios II MMU G 4 G 4 K 512 M TLB TLB n TLB TLB TLB TLB MMU Nios II 2 16 Altera Corporation Nios II

17 Nios II Nios II MMU MMU VIPT Virtually-Indexed, Physically-Tagged MMU Nios II MMU SOPC Builder Nios II Nios II Nios II MMU Nios II MPU Nios II MMU MPU MMU MPU Nios II MPU Nios II MPU MPU Nios II Nios II Nios II MPU MPU MPU Nios II MPU SOPC Builder Nios II Nios II Altera Corporation 2 17 Nios II

18 JTAG Nios II MPU Nios II MMU Nios II MPU MMU MPU MMU JTAG Nios II JTAG PC PC JTAG Nios II MMU JTAG FPGA JTAG FPGA JTAG Nios II Nios II JTAG 2 18 Altera Corporation Nios II

19 Nios II JTAG Nios II IDE JTAG JTAG FPGA JTAG CPU / JTAG Nios II IDE JTAG JTAG RAM RAM JTAG JTAG JTAG Altera Corporation 2 19 Nios II

20 JTAG 2 4 JTAG 2 4. (1) D I D D D D I 2-20 D 2-21 : (1) I D JTAG 2 5 Nios II JTAG JTAG 2 JTAG A B A B 2 20 Altera Corporation Nios II

21 JTAG (1) JTAG 1 : (1) 1 JTAG JTAG JTAG Altera Corporation 2 21 Nios II

22 JTAG Nios II First Silicon Solution FS2 Lauterbach JTAG JTAG Altera Corporation Nios II

23 100% Nios II Nios II Instantiating the Nios II Processor in SOPC BuilderNios II Nios II Custom Instruction User Guide Instruction Set ReferenceNios II Nios II Avalon Memory Mapped Interface Specification Altera Corporation 2 23 Nios II

24 v v v v v v v5.1.0 MMU MPU cpu_resetrequest cpu_resettaken MMU MPU v v v v1.0 ctl5 Nios II Altera Corporation Nios II

Nios IIプロセッサ・リファレンス・ハンドブック、セクション I. Nios IIプロセッサ Ver. 1.2

Nios IIプロセッサ・リファレンス・ハンドブック、セクション I. Nios IIプロセッサ Ver. 1.2 I. Nios II Nios II 1 2 3 4 SOPC Builder Nios II Altera Corporation I 1 Nios II 1 4 Nios II Nios II / 1 2004 9 v1.1 Nios II 1.01 2004 5 v1.0 2 2004 12 v1.2 ctl5 2004 9 v1.1 Nios II 1.01 2004 5 v1.0 3 2004