インテル(R) Xeon(R) プロセッサーおよびインテル(R) Pentium(R) 4 プロセッサーのパフォーマンス・カウンター
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- しげのぶ おなか
- 6 years ago
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1 Core Intel Intel Intel Itanium Pentium Xeon Intel Corporation 2007Intel Corporation.
2 VTune 9.0 VTune 1 Randy Camp R&D MUSICMATCH Inc. Core 2 Duo Core 2 Quad Windows: Microsoft Vista* Linux: hotspot Windows* Linux* Mac* IA32 Intel64 IA Intel Corporation. Intel Intel Intel Corporation
3 Core Intel Corporation. Intel Intel Intel Corporation
4 Core Intel Corporation. Intel Intel Intel Corporation
5 VTune : = * (SAV) Intel Corporation. Intel Intel Intel Corporation
6 Core FSB L2 2/4MB CPU-0 L1D=32KB L0/L1 DTLB PMH CPU-0 L1I=32KB CPU-1 L1D=32KB L0/L1 DTLB PMH CPU-1 L1I=32KB CPU-0 CPU Intel Corporation. Intel Intel Intel Corporation
7 Intel Corporation. Intel Intel Intel Corporation
8 4 L1 Core Duo DCU DCU Data Cache Unit IP IP L2 Pentium Intel Corporation. Intel Intel Intel Corporation
9 P P CPU_CLK_UNHALTED BUS_DRDY_CLOCKS.ALL_AGENTS BUSY INST_RETIRED_ANY_P P BUS_DRDY_CLOCKS.THIS_AGENT BUSY INST_RETIRED_LOADS MEM_LOAD_RETIRED.L2_LINE_MISS P L2 INST_RETIRED_STORES MMX2_PRE_MISS.T1 LSW BUS_TRANS_ANY MMX2_PRE_MISS.T2 L2SW BUS_TRANS_MEM MMX2_PRE_MISS.STORES BUS_TRANS_BURST L2_LINES_IN.SELF.DEMAND SW L2 BUS_TRANS_BRD L2_LINES_IN.SELF.PREFETCH HW L2 BUS_TRANS_WB NT L2_LINES_OUT.SELF.DEMAND L2 BUS_TRANS_RFO RFOHW L2_LINES_OUT.SELF.PREFETCH HW L2 = 64 * Bus_Trans_Mem * / Cpu_Clk_Unhalted Intel Corporation. Intel Intel Intel Corporation
10 X86 OOO Intel Corporation. Intel Intel Intel Corporation
11 Intel Corporation. Intel Intel Intel Corporation
12 IP OOO 4 L2 BW DTLB FE CPU Intel Corporation. Intel Intel Intel Corporation
13 X86 CPU_CLK_UNHALTED = + NON_RET_DISPATCH + RET_DISPATCH PGO ILP RESOURCE_STALLS.BR_MISS_CLEAR Intel Corporation. Intel Intel Intel Corporation
14 UOP // L2 32KB IP 32KB 4 (BTB) (RAT) RESOURCE_STALLS RS 32 MOB) SIMD SIMD SIMD FP Add / FP DIV/MUL ROB) 96 IA Intel Corporation. Intel Intel Intel Corporation
15 UOP // L2 32KB IP 32KB 4 (BTB) (RAT) RS 32 MOB) SIMD SIMD SIMD FP Add / FP DIV/MUL ROB) 96 RS_UOPS_DISPATCHED IA Intel Corporation. Intel Intel Intel Corporation
16 UOP // L2 32KB IP 32KB 4 (BTB) (RAT) UOPS_RETIRED RS 32 MOB) SIMD SIMD SIMD FP Add / FP DIV/MUL ROB) 96 IA Intel Corporation. Intel Intel Intel Corporation
17 OOO RS RS_UOPS_DISPATCHED CPU RS PMU* * Performance Monitoring Unit (PMU) Intel Corporation. Intel Intel Intel Corporation
18 // L2 32KB IP 32KB 4 (BTB) (RAT) RS_UPOS_DISPACHED RS 32 MOB) SIMD SIMD SIMD FP Add / FP DIV/MUL ROB) 96 IA Intel Corporation. Intel Intel Intel Corporation
19 VTune Intel Corporation. Intel Intel Intel Corporation
20 PMU GE LT CMASK I NV E N I N T P C E OS US R umask Event # 3 APIC 0 RS_UOPS_DISPATCHED CMASK = 1 INV = 1 UOPS == RS_UOPS_DISPATCHED.CYCLES_NONE Intel Corporation. Intel Intel Intel Corporation
21 RS_UOPS_DISPATCH: cmask = 1 ~ CPU_CLK_UNHALTED RS_UOPS_DISPATCH: cmask = 1 : inv = 1 CPU_CLK_UNHALTED OOO >99% CPU PL HALT Intel Corporation. Intel Intel Intel Corporation
22 UOP / RS_UOPS_DISPATCHED:cmask=1:inv=1 RS_UOPS_DISPATCHED:cmask=2:inv=1 RS_UOPS_DISPATCHED:cmask=3:inv=1 RS_UOPS_DISPATCHED:cmask=4:inv=1 RS_UOPS_DISPATCHED:cmask=5:inv=1 RS_UOPS_DISPATCHED:cmask=6:inv=1 RS_UOPS_DISPATCHED:cmask=7:inv=1 N-1 uops dispatched per cycle a[i] = exp(x[i]); Series Intel Corporation. Intel Intel Intel Corporation
23 // L2 32KB IP 32KB 4 (BTB) (RAT) RESOURCE_STALL RS 32 MOB) SIMD SIMD SIMD FP Add / FP DIV/MUL ROB) 96 IA Intel Corporation. Intel Intel Intel Corporation
24 RESOURCE_STALL OOO UOP RESOURCE_STALLS.BR_MISS_CLEAR FP RESOURCE_STALLS.CLEAR RESOURCE_STALLS.ROB_FULL ROB 96 RESOURCE_STALLS.LD_ST RESOURCE_STALLS.RS_FULL RS Intel Corporation. Intel Intel Intel Corporation
25 // L2 32KB IP 32KB 4 (BTB) (RAT) UOPS_RETIRED RS 32 MOB) SIMD SIMD SIMD FP Add / FP DIV/MUL ROB) 96 IA Intel Corporation. Intel Intel Intel Corporation
26 "Stalls" at Retirement vs Dispatch Cycles(Ret_uops=0) Cycles(Disp_uops=0) OOO Intel Corporation. Intel Intel Intel Corporation
27 X86 = rs_uops_dispatched.cycles_none + rs_uops_dispatched:cmask=1 + ~ CPU_CLK_UNHALTED.CORE CPU Intel Corporation. Intel Intel Intel Corporation
28 X86 ~ cycles_dispatch_retiring_uops + cycles_dispatch_non_retiring_uops / UOP UOP = rs_uops_dispatched (uops_retired.any + Uops_retired.fused) UOP ~ uops / avg_uops_per_cycle = rs_uops_dispatched / (uops_retired.any + uops_retired.fused) Intel Corporation. Intel Intel Intel Corporation
29 Cycle Accounting Executing Stalls = UOP = RS_UOPS_DISPATCH.CYCLES_NONE Intel Corporation. Intel Intel Intel Corporation
30 Stall Decomposition Executing FE + Scoreboard Pipeline Flush DTLB L2 Hits L2 Misses Stall Total = RESOURCE_STALLS.BR_MISS_CLEAR / L2 = ( MEM_LOAD_RETIRED.L1D_LINE_MISS - MEM_LOAD_RETIRED.L2_LINE_MISS )*12/ DTLB/L2 = * / FE + = Intel Corporation. Intel Intel Intel Corporation
31 Decomposing Unstalled Cycles Uops Retiring OOO Bursts Non_retired Stalls = (( 1 (Uops_retired.any+Uops_retired.fused)/RS_Uops_Dispatched) * RS_Uops_Dispatched:cmask=1 / CPU_CLK_UNHALTED.CORE OOO = Uops_Retired.Any.cycles_none Intel Corporation. Intel Intel Intel Corporation
32 Cycle Decomposition 1 Uops Retiring OOO Bursts Non_retired FE + Scoreboard Pipeline Flush DTLB L2 Hits L2 Misses / FE Intel Corporation. Intel Intel Intel Corporation
33 Load_Blocks.ADR ~5 8 4 Load_Blocks.Overlap_Store ~6 N*4096 Load_Blocks. Overlap_Store ~6 L2 2 Load_Blocks.UNTIL_RETIRE ~22 L2 2 Load_Blocks.UNTIL_RETIRE ~20 16 ILD_STALLS ~6 FE Intel Corporation. Intel Intel Intel Corporation
34 CPU_CYCLES CPU_CLK_UNHALTED.CORE BACK_END_BUBBLE.ALL RS_UOPS_DISPATCHED.CYCLES_NONE BUS_MEMORY.ALL.SELF BUS_TRANS_ANY.SELF DEAR_LATENCY_GT_64 MEM_LOAD_RETIRED.L2_LINE_MISS Intel Corporation. Intel Intel Intel Corporation
35 1 SAV (Sample After Value) CPU_CLK_UNHALTED.CORE 2,000,000 RS_UOPS_DISPATCHED.CYCLES_NONE 2,000,000 UOPS_RETIRED.ANY + UOPS_RETIRED.FUSED 2,000,000 RS_UOPS_DISPATCHED 2,000,000 MEM_LOAD_RETIRED.L2_LINE_MISS 10,000 INST_RETIRED.ANY_P 2,000,000 BUS_TRANS_ANY.SELF 100,000 BUS_TRANS_ANY.ALL_AGENTS 100,000 RESOURCE_STALLS.BR_MISS_CLEAR 2,000,000 SAV Intel Corporation. Intel Intel Intel Corporation
36 2 SAV (Sample After Value) MEM_LOAD_RETIRED.DTLB_MISS 20,000 MEM_LOAD_RETIRED.L2_MISS 10,000 MEM_LOAD_RETIRED.L1_LINE_MISS 200,000 BR_CND_MISSP_EXEC 2,000,000 BR_CND_EXEC 2,000,000 BR_CALL_EXEC 200,000 BR_CALL_MISSP_EXEC 200,000 ILD_STALLS 200,000 LOAD_BLOCK.STORE_OVERLAP 200,000 SAV : L1 / L2_hit Intel Corporation. Intel Intel Intel Corporation
37 FP L2 OOO Intel Corporation. Intel Intel Intel Corporation
38 Core 2 2 SIMD 1 Core 2 PMU LLC Intel Corporation. Intel Intel Intel Corporation
39 Intel Corporation. Intel Intel Intel Corporation
40 MEM_LOAD_RETIRED.L2_MISS L Intel Corporation. Intel Intel Intel Corporation
41 Core Core BR_INST_RETIRED.MISPRED INST_RETIRED.ANY_P MEM_LOAD_RETIRED.DTLB_MISS MEM_LOAD_RETIRED.L1D_LINE_MISS EIP MEM_LOAD_RETIRED.L1D_MISS MEM_LOAD_RETIRED.L2_LINE_MISS MEM_LOAD_RETIRED.L2_MISS SIMD_INST_RETIRED.ANY X87_OPS_RETIRED.ANY Intel Corporation. Intel Intel Intel Corporation
42 Core CPU_CLK_UNHALTED.CORE INST_RETIRED.ANY CPU_CLK_UNHALTED.CORE CPU HALT CPU CPU_CLK_UNHALTED.CORE / = 1 INST_RETIRED.ANY = CPI = CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY CPI Intel Corporation. Intel Intel Intel Corporation
43 Core CPU_CLK_UNHALTED.CORE CPU_CLK_UNHALTED.NO_OTHER CPU_CLK_UNHALTED.NO_OTHER HALT 1 CPU_CLK_UNHALTED.CORE HALT CPU_CLK_UNHALTED.NO_OTHER Intel Corporation. Intel Intel Intel Corporation
44 VTune Xeon Pentium 4 Web Intel Corporation. Intel Intel Intel Corporation
45 Intel s Terms and conditions of Sales ( ) * 2007 Intel Corporation Intel Corporation. Intel Intel Intel Corporation
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