DAS27 27/9/ BTI BTI [5] CMOS NMOS PMOS [6] NMOS PMOS NOR BTI 2 BTI 3 BTI 4 BTI Bias Temperature Instability (BTI) BTI BTI 2 NBTI (Negative BTI)

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1 DAS27 27/9/ NOR PMOS 6 NMOS 3 Threshold Voltage Conversion Method of Frequency Fluctuations Using Current Starved Ring Oscillators Ryo Kishida Jun Furuta Kazutoshi Kobayashi Abstract: It has been difficult to predict lifetime of integrated circuits with the miniaturization of electronic devices. In this paper, Threshold voltage (V th ) conversion method of frequency fluctuations are proposed using current starved ring oscillators (ROs). Measured transistors are inserted between supply voltage line (VDD) and virtual VDD in the ROs. ROs are not composed by inverters but NORs to suppress aging degradation in ROs and only effects of measured transistors are observed. Measured frequencies are converted to V th and extrapolated. Estimations of V th degradations are different between exponential and logarithm functions. Exponential estimation is six and three times larger than logarithm in PMOS and NMOS respectively in ten years.. CPU [] µm Department of Electronics, Kyoto Institute of Technology 27 nm [2] 3 6 Bias Temperature Instability (BTI) [3] BTI [4] 5 5 V/cm V/cm BTI 27 Information Processing Society of Japan 98

2 DAS27 27/9/ BTI BTI [5] CMOS NMOS PMOS [6] NMOS PMOS NOR BTI 2 BTI 3 BTI 4 BTI Bias Temperature Instability (BTI) BTI BTI 2 NBTI (Negative BTI) PBTI (Positive BTI) 2. BTI BTI [3] MOSFET BTI BTI BTI Atomistic Trap-based BTI (ATB) [7], [8] ATB Oxide Trap 9 9 s S G Gate Oxide Vg Oxide Trap Defect Carrieres Interface Trap Atomistic Trap-based BTI (ATB) 9 s BTI [9] Interface Trap 2 [] t t n log(t) n BTI BTI NBTI (Negative BTI) PBTI (Positive BTI) 2 NBTI PMOS (V gs < V) PBTI (Positive BTI) NMOS V gs > V 65 nm PBTI 65 nm SiON NMOS 45 nm high-k PBTI [] high-k Hf ( ) SiON 5 high-k Si D 27 Information Processing Society of Japan 99

3 DAS27 27/9/ Virtual VDD VDD RO VDD NOR type Ring Oscillator (RO) RO GND PMOS switch (PMOS-SW) GND (a) to 6-bit embedded counter ENB 3 to embedded 6-bit counter NOR ENB NOR ENB 2 Virtual GND VDD RO VDD NOR type Ring Oscillator (RO) RO GND NMOS switch (NMOS-SW) GND (b) to 6-bit embedded counter (a) PMOS (VDD) (RO VDD) PMOS (b) NMOS (GND) (RO GND) NMOS 4 ENB RO VDD PMOS ENB Vgs = Vth Vth Vgs = Vth Vth PMOS RO NMOS RO NMOS ENB RO GND NOR PMOS RO (V gs ) (V th ) NBTI PMOS SiON high-k SiON high-k NMOS PBTI 65 nm SOI (silicon-on-insulator) high-k PBTI high-k PBTI 3. BTI 3. 2 RO 2(a) PMOS (VDD) RO (RO VDD) PMOS PMOS PMOS-SW RO VDD RO RO 2(b) NMOS RO NMOS (GND) RO (RO GND) NMOS NMOS RO GND 3.2 NOR NOR 3 NOR RO NOR RO 2 NOR type Ring Oscillator NOR 2 (ENB) NOR NOR RO BTI 4 NOR BTI ENB NOR RO PMOS RO NMOS RO PMOS RO (V gs ) (V th ) NBTI NMOS RO V gs V PBTI ENB PMOS RO NMOS RO PMOS RO NMOS RO ENB NOR RO BTI 27 Information Processing Society of Japan 2

DAS27 27/9/ V RO_OUT Initial frequency Frequency after BTI stress Time Oscillation 2 µs BTI stress > s Oscillation 2 µs BTI stress > s Oscillation 2 µs 5 7 5 65 nm SOI (siliconon-insulator) 7 4.

4 DAS27 27/9/ V RO_OUT Initial frequency Frequency after BTI stress Time Oscillation 2 µs BTI stress > s Oscillation 2 µs BTI stress > s Oscillation 2 µs nm SOI (siliconon-insulator) 7 4. BTI ENB 2 µs ENB RO BTI 5 BTI 2 µs BTI 3 BTI BTI 2. V 2 C 4.2 BTI 7 NBTI PMOS (D rate ) () D rate = F F (t) F () F F (t) t BTI 7 D rate NBTI 6 Freq. Degradation Rate [a.u.] 7 BTI BTI PMOS-NBTI PMOS NBTI 5. BTI 5. (V th ) PMOS-SW, NMOS-SW 8 V th V th PMOS NMOS V th PMOS (2) NMOS (3) 27 Information Processing Society of Japan 2

5 DAS27 27/9/ Frequency ratio [%] NMOS PMOS Threshold voltage shift [%] PMOS 7 V th 2 F P =.384V th (2) F N =.34V th (3) F P F N PMOS NMOS 7 D rate (2) (3) 5.2 V th (2) (3) 2 f(t) = mt n + l (4) g(t) = a log(t + ) + b (5) t f(t) g(t) a, b, l, m, n 9 7 (3 8 s) V th V th 6 NMOS 2 NMOS PMOS PMOS NMOS 27 Information Processing Society of Japan 22

6 DAS27 27/9/ NMOS NMOS PMOS BTI NOR BTI BTI JSPS 5H2677 [] M. Bohr, The Evolution of Scaling from the Homogeneous Era to the Heterogeneous Era, IEDM, (2), pp [2] S. Yang, Y. Liu, M. Cai, J. Bao, P. Feng, X. Chen, L. Ge, J. Yuan, J. Choi, P. Liu, Y. Suh, H. Wang, J. Deng, Y. Gao, J. Yang, X.-Y. Wang, D. Yang, J. Zhu, P. Penzes, S. C. Song, C. Park, S. Kim, J. Kim, S. Kang, E. Terzioglu, K. Rim, and P. C. Chidambaram, nm High Performance Mobile SoC Design and Technology Co-Developed for Performance, Power, and Area Scaling, VLSI Tech., (27), p. T6.2. [3] V. Huard, C. Parthasarathy, C. Guerin, T. Valentin, E. Pion, M. Mammasse, N. Planes, and L. Camus, NBTI Degradation: From Transistor to SRAM Arrays, IRPS, (28), pp [4] D. K. Schroder and J. A. Babcock, Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing, Journal of Applied Physics, Vol. 94, No., pp. 8, (23). [5] J. Franco, B. Kaczer, M. Toledano-Luque, P. J. Roussel, G. Groeseneken, B. Schwarz, M. Bina, M. Waltl, P. J. Wagner, and T. Grasser, Reduction of the BTI Time-Dependent Variability in Nanoscaled MOSFETs by Body Bias, IRPS, (23), pp. 2D.3. 2D.3.6. [6] W. H. Choi, S. Satapathy, J. Keane, and C. H. Kim, A Test Circuit Based on a Ring Oscillator Array for Statistical Characterization of Plasma-Induced Damage, CICC, (24), p.4-3. [7] H. Kukner, S. Khan, P. Weckx, P. Raghavan, S. Hamdioui, B. Kaczer, F. Catthoor, L. Van der Perre, R. Lauwereins, and G. Groeseneken, Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates, IEEE Trans. on Dev. and Mat. Rel., Vol. 4, No., pp , (24). [8] B. Kaczer, S. Mahato, V. V. de Almeida Camargo, M. Toledano-Luque, P. J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth, and G. Groeseneken, Atomistic Approach to Variability of Bias-Temperature Instability in Circuit Simulations, IRPS, (2), pp. XT.3. XT.3.5. [9] S. Mahapatra, S. De, K. Joshi, S. Mukhopadhyay, R. K. Pandey, and K. V. R. M. Murali, Understanding Process Impact of Hole Traps and NBTI in HKMG p- MOSFETs Using Measurements and Atomistic Simulations, IEEE Electron Device Letters, Vol. 34, No. 8, pp , (23). [] C. Ma, H. J. Mattausch, K. Matsuzawa, S. Yamaguchi, T. Hoshida, M. Imade, R. Koh, T. Arakawa, and M. Miura-Mattausch, Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions, IEEE Transactions on Device and Materials Reliability, Vol. 4, No. 3, pp , (24). [] S. Zafar, Y. Kim, V. Narayanan, C. Cabral, V. Paruchuri, B. Doris, J. Stathis, A. Callegari, and M. Chudzik, A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates, VLSI Tech. Symp., (26), pp Information Processing Society of Japan 23

A シンポジウム esign Automation ymposium A216 MOFET NBTI NBTI 2 NBTI NBTI NBTI [6] NBTI 2 NBTI NBTI NBTI 1 ate ate N-well N-well V PMO ate (a) PMO

A シンポジウム esign Automation ymposium A216 NBTI 1 1 NBTI (Negative Bias Temperature Instability) (RBB) NBTI RBB RBB NBTI 65 nm OI (ilicon on Insulator) RBB NBTI RBB V 1 V 4 RBB NBTI RBB V 1 V 77 Measurements