MAX4814E DS.J

Transcription

1 19-106; Rev 0; 11/07 ± μ ± PART TEMP RANGE PIN- PACKAGE * PKG CODE ECB+ -40 C to +8 C 64 TQFP-EP* C64E-10 4.V TO.V 0.1μF DVI/HDMI 1 DVI/HDMI 2 V DD A B MODE V DD SW0 SW1 SW2 SW3 DVI/HDMI 1 DVI/HDMI 2 DVI/HDMI 1 DVI/HDMI 2 μcontroller SCL SDA DVI/HDMI 1 DVI/HDMI 2 DVI/HDMI 1 DVI/HDMI 2 ADDRESS SELECTION* AD2 AD1 AD0 DO EFN 4 0.1μF MAX384 *SEE DEVICE ADDRESS SECTION. Maxim Integrated Products 1

2 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to. Note 1.) V DD, A_, B_, SW_, EFN V to +6.0V All Other Pins (except ) V to V DD + 0.3V Continuous Current, A_, B_...±60mA Continuous Current, V DD or...±100ma Continuous Power Dissipation (T A = +70 C) 64-Pin TQFP (derate 31.3mW/ C above +70 C)...208mW Operating Temperature Range C to +8 C Junction Temperature C Storage Temperature Range...-6 C to +10 C Lead Temperature (soldering) C Note 1: EFN must be either connected to V DD or left unconnected. EFN must not be connected to ground. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = +V ±10%, T A = -40 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C, V DD = +V. Note 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Power-Supply Voltage V DD 4.. V E FN = unconnected ; al l i np uts = 0; Power-Supply Current I DD al l outp uts hi g h or l ow, no l oad s 10 μa EFN Leakage Current I L V EFN = V DD - 0.2V μa LOGIC INPUTS (DA_, DB_, MODE, AD_) Input Low Voltage DA_, DB_ V IL MODE = 0V 0.8 V Input High Voltage DA_, DB_ V IH MODE = 0V 2 V Input-Voltage Hysteresis DA_, DB_ V HYST MODE = 0V 10 mv Input Low Voltage AD_ V IL MODE = V DD 0.8 V Input High Voltage AD_ V IH MODE = V DD 2 V Input-Voltage Hysteresis AD_ V HYST MODE = V DD 10 mv Input Low Voltage MODE V IL 0.8 V Input High Voltage MODE V IH 2 V Input-Voltage Hysteresis MODE V HYST 10 mv Input Leakage Current DA_, DB_ I L MODE = 0V ±1 μa Input Leakage Current AD_ I L MODE = V DD ±1 μa Input Leakage Current MODE I L ±1 μa LOGIC OUTPUTS DO_ Output-Voltage Low V OL MODE = V DD, I SINK = 30μA 0. V Output-Voltage High V OH MODE = V DD, I SOURCE = 26μA 2 V Output Leakage Current I L M OD E = V D D, outp ut at hi g h i m p ed ance, V I N = 1.V ±1 μa Output Rise Time t R V OUT from 0.8V to 2.2V, C LOAD = 10pF 600 ns I SOURCE -1 Output Short-Circuit Current I SC I SINK +3 ma 2

3 ELECTRICAL CHARACTERISTICS (continued) (V DD = +V ±10%, T A = -40 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C, V DD = +V. Note 2.) ANALOG SWITCHES PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT On-Resistance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] On-Resistance-Flatness Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] On-Channel -3dB Bandwidth Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] Off-Isolation Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] R ON V IN = 2.V, I IN = ±10mA 12 Ω R FLAT V IN = 0.8V, 2.V, 3.7V 2. Ω BW R S = R L = 0Ω, C L = 3pF, Figure MHz V ISO R S = R L = 0Ω, f = 1MHz, Figure 1 6 db Crosstalk Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] On-Capacitance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] Off-Capacitance Standard Switches: A[1], A[2], A[3], B[1], B[2], B[3] V CT R S = R L = 0Ω, f = 1MHz, Figure 1 7 db C ON V DD = 4.V, f = 1MHz, Figure 2 37 pf C OFF V DD = 4.V, f = 1MHz, Figure 2 1 pf Charge Injection On-Resistance +V/Drain: A[0], A[4], B[0], B[4] Q V GEN = 1.V, R GEN = 0Ω, C L = 100pF, Figure 3 13 pc R ON V DD = 4.V, V IN = 0V or V DD 3 Ω Switch Leakage Current I L ±10 μa I 2 C SPECIFICATIONS (SDA, SCL, MODE = V DD ) Input Low Voltage V IL 0.8 V Input High Voltage V IH 2.4 V Input-Voltage Hysteresis V HYST 40 mv Input Leakage Current I L ±1 μa Output-Voltage Low SDA V OL I SINK = 3mA 0.4 V TIMING CHARACTERISTICS (Figure 4), MODE = V DD Serial Clock Frequency f SCL V DD = 4.V khz Hold Time (Repeated) START Condition (after this period the first clock pulse is generated) t HD,STA f SCL = 100kHz 4 μs Low Period of the SCL Clock t LOW f SCL = 100kHz 4.7 μs 3

4 ELECTRICAL CHARACTERISTICS (continued) (V DD = +V ±10%, T A = -40 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C, V DD = +V. Note 2.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT High Period of the SCL Clock t HIGH f SCL = 100kHz 4 μs Setup Time for a Repeated START Condition t SU,STA f SCL = 100kHz 4.7 μs Data Hold Time t HD,DAT f SCL = 100kHz 2 μs Data Setup Time t SU,DAT f SCL = 100kHz 20 ns ESD PROTECTION (HUMAN BODY MODEL) SW_, A_, B_ Referenced to ±6 ESD All Other I/Os ±2 kv Note 2: Limits at T A = -40 C are guaranteed by design. 4

5 0Ω B_ +V 0.1μF V DD A_ SW_ V IN V OUT MEAS 0Ω NETWK ANALYZER 0Ω 0Ω 0Ω REF OFF-ISOLATION = 20log V OUT V IN ON-LOSS = 20log V OUT V IN CROSSTALK = 20log V OUT V IN MEASUREMENTS ARE STANDARDIZED AGAINST SHTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN SW_ AND "OFF" A_ B_ TERMINAL ON EACH SWITCH. ON-LOSS IS MEASURED BETWEEN SW_ AND "ON" A_ B_TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WST VALUES ARE RECDED. 0.1μF +V CAPACITANCE METER f = 1MHz V DD SW_ A_ B_ DB_ DA_ SDA SCL V IL V IH +V 0.1μF ΔV OUT V GEN R GEN A_ B_ V DD SW_ DB_ SDA DA_ SCL V INL TO V INH C L V OUT V OUT DB_ DA_ SDA SCL DB_ DA_ SDA SCL OFF OFF ON ON OFF OFF Q = (ΔV OUT )(C L ) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

6 (V DD = +V, T A = +2 C, unless otherwise noted.) ON-RESISTANCE (Ω) ON-RESISTANCE vs. V A V B V DD = 4.V V DD =.V V DD =.0V V DD = 4.V V DD =.0V V/DRAIN V DD =.V V A V B (V) toc01 ON-RESISTANCE (Ω) ON-RESISTANCE vs. V A V B T A = +8 C T A = +2 C V/DRAIN T A = +8 C T A = +2 C V A V B (V) T A = -40 C T A = -40 C toc02 LEAKAGE CURRENT (pa) 100,000 10, LEAKAGE CURRENT vs. TEMPERATURE +V/DRAIN OFF-LEAKAGE STD. SWITCH OFF-LEAKAGE +V/DRAIN ON-LEAKAGE STD. SWITCH ON-LEAKAGE TEMPERATURE ( C) toc03 SUPPLY CURRENT (μa) SUPPLY CURRENT vs. TEMPERATURE SWITCH I/O_ = 0V V DD =.V V DD = 4.V V DD =.0V TEMPERATURE ( C) toc04 FREQUENCY RESPONSE (db) FREQUENCY RESPONSE 20 0 OFF-ISOLATION -20 ON-LOSS CROSS-TALK FREQUENCY (MHz) toc0 6

7 1, 16, 24, 2, 33, 48, 6, 7 2, 1, 34 I.C. 3 A[0] 4 A[1] A[2] 6 A[3] 7 A[4] 8, 9, 17, 32, 40, 41, 49, 64 V DD 10 B[0] 11 B[1] 12 B[2] 13 B[3] 14 B[4] 18 MODE 19 SDA 20 SCL 21 AD0 22 AD1 23 AD2 26 SW3[4] 27 SW3[3] 28 SW3[2] 29 SW3[1] 30 SW3[0] 31, 0 EFN 3 SW2[4] 36 SW2[3] 37 SW2[2] 38 SW2[1] 39 SW2[0] 42 SW1[4] 43 SW1[3] 44 SW1[2] μ ± μ 7

8 4 SW1[1] 46 SW1[0] 47 N.C. 1 SW0[4] 2 SW0[3] 3 SW0[2] 4 SW0[1] SW0[0] 8 DA0/DO0 9 DA1/DO1 60 DA2/DO2 61 DB0/DO3 62 DB1 63 DB2 EP EP 8

9 V DD A_ A0 SW0_ A1 SW1_ A2 SW2_ A3 SW3_ B_ B0 B1 B2 B3 B_ A_ DECODER 6 MUX 6 6 DO[3:0] 4 4 HI-Z DB0 DA_ I 2 C SERIAL PT AND REGISTERS I.C. N.C. EFN EN EN EN EN EN MODE SDA SCL AD0 AD1 AD2 DB_ DA_ 9

10 INPUT PIN MODE OPERATION 0 Puts the device in mode 0. The direct-control inputs DA_ and DB_ control the switches. 1 REGISTER R0 R1 P uts the d evi ce i n m od e 1. The sw i tches ar e contr ol l ed b y the I 2 C i nter face. D O _ b ecom es an acti ve outp ut. Inp uts D B1 and D B2 ar e hi g h i m p ed ance. BIT BBEN D O3 H i g h Im p ed ance BBSE L1 DO3 Data BBSEL0 BAEN BASEL1 DO2 High Im p ed ance DO2 Data DO1 High Im p ed ance BASE L0 DO1 Data X X 0x00 DO0 High Im p ed ance DO0 Data ADDRESS BINARY 0x01 POWER-UP HEX 00 AA 10

11 MODE PIN CONFIGURATION DA0/DO0 DA1/DO1 DA2/DO2 DB0/DO3 DB1 DB2 0 DA0, Input DA1, Input DA2, Input DB0, Input DB1, Input DB2, Input 1 DO0, Output DO1, Output DO2, Output DO3, Output High Impedance High Impedance PIN CONNECTION OPERATION DA2 0 Bank A switches are disabled 1 Bank A switches are enabled. Switch A connections depend on the DA0 and DA1 inputs. PIN CONNECTION OPERATION DB2 0 Bank B switches are disabled 1 Bank B switches are enabled. Switch B connections depend on the DB0 and DB1 inputs. PIN CONNECTION DB1 DB0 DA1 DA0 OPERATION Connect A to SW0 B is high impedance Connect A to SW1 Connect B to SW Connect A to SW2 Connect B to SW Connect A to SW3 Connect B to SW Connect A to SW0 Connect B to SW Connect A to SW1 B is high impedance Connect A to SW2 Connect B to SW Connect A to SW3 Connect B to SW Connect A to SW0 Connect B to SW Connect A to SW1 Connect B to SW Connect A to SW2 B is high impedance Connect A to SW3 Connect B to SW Connect A to SW0 Connect B to SW Connect A to SW1 Connect B to SW Connect A to SW2 Connect B to SW Connect A to SW3 B is high impedance 11

12 PIN REGISTER R1 (0x01) OUTPUT PIN MODE BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 CONFIGURATION DO DO X DO0 Hi-Z DO DO X DO1 Hi-Z DO DO X DO2 Hi-Z DO DO X DO3 Hi-Z REGISTER R0 (0x00) BIT 7 BIT 6 BIT BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BBEN BBSEL1 BBSEL0 BAEN BASEL1 BASEL0 X X ± ± 12

13 DB2/ BBEN DA_, DB_ INPUTS/REGISTER R0 BITS DB1/ BBSEL1 DB0/ BBSEL0 DA2/ BAEN DA1/ BASEL1 DA0/ BASEL0 B TO SW3 SWITCH A AND B TO SW_ CONNECTIONS 0 X X 0 X X 0 X X X X X X X X X X X X X X X X B TO SW2 B TO SW1 B TO SW0 A TO SW3 A TO SW2 A TO SW1 A TO SW0 B7 B6 B B4 B3 B2 B1 B AD2 AD1 AD0 R/W Fixed User Selected μ 13

14 SDA SCL t HD, STA t SU, DAT t LOW t HD, DAT t HIGH t SU, STA t r t f START CONDITION REPEATED START CONDITION MODE = 1: I 2 C CONTROL 8 3-STATE CONTROL 96 MODE = 0: DIRECT CONTROL MAX V DD SDA SCL I 2 C CONTROL SETS 3 LSBs OF I 2 C ADDRESS. AS SHOWN ADDRESS = LSB = THERE ARE 8 POSSIBLE I 2 C ADDRESSES. BY HARDWIRING PINS 23, 22, AND 21 TO 1 0 USER CAN CHANGE ADDRESS. SEE TABLE 4 F I 2 C REGISTERS MODE = 0 DA0 DA1 DA2 DB0 DB1 DB2 SEE TABLE 3b F CONTROL FUNCTIONS. R C 1MΩ CHARGE-CURRENT- LIMIT RESIST R D 100Ω DISCHARGE RESISTANCE AMPERES I P 100% 90% Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) HIGH- VOLTAGE DC SOURCE Cs 100pF STAGE CAPACIT DEVICE UNDER TEST 36.8% 10% 0 0 t RL TIME t DL CURRENT WAVEFM 14

15 TOP VIEW N.C. SW1[0] SW1[1] SW1[2] SW1[3] SW1[4] VDD VDD SW2[0] SW2[1] SW2[2] SW2[3] SW2[4] I.C V DD 49 EFN 0 SW0[4] 1 SW0[3] 2 SW0[2] 3 SW0[1] SW0[0] DA0/DO0 DA1/DO1 DA2/DO2 DB0/DO3 DB DB2 63 V DD V DD EFN SW3[0] SW3[1] SW3[2] SW3[3] SW3[4] AD2 AD1 21 AD0 20 SCL *EP 19 SDA 18 MODE 17 V DD A[0] I.C. A[1] A[2] A[3] A[4] VDD VDD B[0] B[1] B[2] B[3] B[4] I.C. TQFP *CONNECT EXPOSED PADDLE TO. μ PROCESS: BiCMOS 1

16 japan.maxim-ic.com/packages 64L, TQFP.EPS PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP OPTION C

17 japan.maxim-ic.com/packages PACKAGE OUTLINE, 64L TQFP, 10x10x1.0mm EP OPTION C 2 2 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.