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1 1
2 CMOS 0.35um CMOS, 3V CMOS 2
3 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3
4 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4
5 5
6 f T [GHz] Technology loadmap L[nm] f T [GHz] Gate length [nm] Technology loadmap year year CMOS Vdd [V] 1.4 Vdd (Vdd), 6
7 SNR LSI 7
8 8
9 Controller 9
10 1 Ts = 2 / s 10
11 2 Ts = 2 / s 11
12 - - CMOS CMOS 12
13 CMOS CMOS CMOS 4 13
14 14
15 15
16 RF CMOS Nauta OTA) RF P Vinp Vin P N 0 Vout Vinn N P N P N P N Nauta OTA P N P N Von Vop 16
17 MOS 17
18 - - CMOS 18
19 19
20 CMOS 20
21 - - Voltage 1/fs fs Time 1/2fs 2fs Time 21
22 - - Down-sampling Vin RF signal Baseband signal Sampling LPF LPF Vout 22
23 - - Frequency conversion Band selection 23
24 V1 clk clk C clk clk V2 C R MOS R R = T / C T: clk clk 24
25 TIUCLA 25
26 26
27 3b ADC 3b DAC 27
28 LPF b ADC b DAC LPF PDM () 28
29 OSR=28 OSR=210 OSR=216 OSRON,OFF OSR: Sampling 29
30 Low-IF RF Zero-IF DC1/f RF Low-IF AD 30
31 31
32 DAC I Iin Qin + Analog Input H(z) Complex Banpass Filter E i ADC I ADC Q E q Iout Digital Output Qout DAC Q I out + jq H 1+ H out (I in = + jq in ) H (E i + je q ) 32
33 33
34 34
35 35
36 CMOS TDC 1988 VLSI Circuit Symp All Digital PLL Bogdan Staszewski ( Digital Radio Processor MOS 36
37 ref(t) T D Q D Q D Q in(t) D0 D1 D2 ref D0=1 D1=1 D2=1 D3=0 D4=0 Encoder Dout in CMOS 37
38 ADC 1 ADC 38
39 ADC Signal Level Signal Comparator Output Reference Clock Tout1 Tout2 Tout3 Time Time 39
40 40 ADC t = T t A t V ref π 2 cos ) ( = A t A T t in n ) ( arccos ) ( 2 cos t A T t A in = π Ain Vref
41 VDD)
42 0.6V 160ps t 1 t 2 t 3 t 4 t 5 t 6 160ps 160ps 160ps 160ps 160ps 160ps q 1 =1 q 2 =1 q 3 =0 q 4 =0 q 5 =0 q 6 =0
43 43 t 1 t 2 t 3 t 4 t 5 1.0V 100ps 100ps 100ps 100ps 100ps 100ps 100ps q 1 =1 q 2 =1 q 3 =1 q 4 =1 q 5 =0 q 6 =0 t 6
44 CLKin R A B TDC Dout Cmeasure CLKin A B T TDC TRCmeasure
45 CLK TDC (NTU, Harvard Univ.) A TDC Dout B A A B B TDC
46 All Digital PLL FreqData CKref TDC Phase error DCO CKout 46
47 PWM PWM ON CLK PWM. 47
48 10bit
49 A0B3 A1B21-2 A2B A3B A1B3 1 4 A2B A3B A4B A2B A3B A4B A5B
50 A0,B3. A2,B1. 2 A3,B
51 Digital Input e1 e2 e3 e4 en N L+ N
52 0010 M U X M U X M U X M U X N M U X e1 e2 e3 e4 en N N 52
53 RC (ISI) 53
54 PWM Twente VDD GND PE 1bit PWM 1bit ISI 54
55 55
56 56
57 ElectroMagnetic Interference EMS EMI EMC EMS EMI Electro Magnetic Compatibility 57
58 EMI EMI () f ( ) f 58
59 59
60 RFout 60
61 UCSD Larson RFout 61
62 MADCM ADC ADC 62
63 ADC1 ADC2 dc 0.2V 1ch dc 0.2V 2ch DCDC DCDC 63
64 ADC χ(0)χ(1)χ(2)χ(3)χ(4) CLK0 ADC0 ADC1 X 0 (f) X 1 (f) 1 4Ts 2 4Ts 3 4Ts 4 4Ts CLK1 ADC2 X 2 (f) CLK2 ADC3 X 3 (f) CLK3
65 ADC X 0 (f) χ(0)χ(1)χ(2)χ(3)χ(4) 1 4Ts 2 4Ts 3 4Ts 4 4Ts f X 1 (f) f χ(0) f s =1/T s χ(4) X 2 (f) f 1 4Ts 2 4Ts 3 4Ts 4 4Ts f X 3 (f) X(f)= X 0 (f)+ X 1 (f)+ X 2 (f)+ X 3 (f) f = χ (0) + χ(4) 65
66 ADC X 0 (f) X 1 (f) χ(0) χ(1) χ(2) χ(3) χ(4) 1 4Ts 2 4Ts 3 4Ts 4 f 4Ts f Spurious components χ(0) χ(4) X 2 (f) X 3 (f) f Ts 2 4Ts 3 4Ts 4 4Ts X(f)= X 0 (f)+ X 1 (f)+ X 2 (f)+ X 3 (f) f λ 0χ (0) + λ 1χ (1) + λ 2χ (2) + λ 3χ (3) + λ 4χ (4) f
67 67
68 AD 68
69 DAC 69
70 Vin Vin 16 Vin16 Vin< Vin>20 Vin>22 Vin> = = 23 70
71 k d(k) : +1 or -1 2 Dout=2 4 +d(1)2 3 +d(2)2 2 +d(3)2 1 +d(4)+d(5) Dout=2 4 +d(1) 4 +d(2) 3 +d(3) 2 +d(4) 1 +d(5)+d(6) <<2 γ =
72 : = = = = = + + = Dout Dout Dout 2
73 73
74 74
75 x x Rx Tx IC 75
76 ADPLL Rx, Tx Rx, Tx 76
77 77
78 UC Santa Barbara Prof. Chen 78
79 79
80
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