30-80 MHz 10Bit Bus LVDS Serial/Deserial w/ IEEE (JTAG) & at-speed B(jp)
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- よしじろう すずがみね
- 5 years ago
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1 SCAN921025,SCAN SCAN and SCAN MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE (JTAG) and at-speed BIST Literature Number: JAJS977
2 SCAN921025/SCAN MHz 10 Bus BLVDS / IEEE (JTAG) at-speed BIST SCAN LVCMOS/LVTTL Bus LVDS SCAN Bus LVDS 10 IEEE IEEE (TAP) ( ) at-speed BIST (at-speed) SCAN PCB PCB 1 CMOS 30MHz - 80MHz 10-Bit Deserializer with IEEE Test Access SCAN CMOS 30MHz - 80MHz 10-Bit Serializer with IEEE Test Access SCAN ds Converted to nat2000 DTD Changed to released status, added subscripts to description of graphic 28.tif removed tjit figure reference, changed seconds units to lowercase, added pagebreak before pinout General updates More final cleanup and spec updates Corrected and clairified TJit and TRNM specs Changed from 35-80Mhz to 30-80Mhz throught Removed bullet for "flow through pinout" remove TBD's and fix front page break Change to 80Mhz serdes datasheet 12 SCAN TRI-STATE PLL 30MHz 80MHz IEEE (JTAG) at-speed BIST PLL (Tx Rx) 600mW ( )(80MHz ) Bus LVDS 800Mbps (80MHz ) PLL / 27 Bus LVDS 49 BGA SCAN921025/SCAN MHz 10 Bus BLVDS / IEEE (JTAG) at-speed BIST National Semiconductor Corporation DS JP 1
3 SCAN921025/SCAN ( ) SCAN SCAN / 30MHz 80MHz (UTP) ( ) 3 TRI-STATE 2 JTAG at-speed BIST PLL 1: / V CC TRI-STATE V CC V CC OK (2.5V) PLL ASIC (TCLK) REFCLK PLL TCLK TRI- STATE TCLK SYNC SYNC1 SYNC2 SYNC LOCK PLL SYNC HIGH 2: PLL SYNC Figure 9 SYNC1 SYNC2 LOCK 1 2 Application SYNC LOW SYNC Bus LVDS Bus LVDS LOCK LOW LOCK LOW Bus LVDS DIN0 DIN9 TCLK TCLK_R/F TCLK_R/F HIGH LOW SYNC 5*TCLK HIGH DIN0 DIN9 HIGH LOW TCLK 12 DO TCLK 80MHz Mbps 10 TCLK 10 TCLK 80MHz Mbps TCLK 30MHz 80MHz (DO ) (DEN) HIGH PWRDN HIGH SYNC1 SYNC2 LOW DEN LOW TRI-STATE LOCK LOW ROUT0 ROUT9 LOCK LOW HIGH 2
4 ( ) ROUT0 ROUT9 RCLK RCLK RCLK_R/F Figure 13 ROUT0 ROUT9 LOCK RCLK 80MHz 3 CMOS (15pF ) PLL LOCK LOW LOCK HIGH RCLK TRI-STATE LOCK SYNC1 SYNC2 1 LOCK SYNC1 SYNC2 SYNC 2 SCAN SYNC SCAN Table 1 REFCLK (RMT:Repetitive Multi-Transition) 1 LOW-HIGH DIN9 LOW 0-1 HIGH SCAN LOCK RMT Figure 1 DIN0 DIN8 RMT PWRDN REN LOW PWRDN LOW PLL TRI-STATE PWRDN HIGH 510 TCLK Bus LVDS LOCK HIGH TRI-STATE DEN LOW (DO DO ) TRI-STATE (SYNC1 SYNC2 PWRDN TCLK_R/F) DEN HIGH REN LOW (ROUT0 ROUT9) RCLK TRI-STATE LOCK PLL TABLE 1. Random Lock Times for the SCAN MHz Units Maximum 18 s Mean 3.0 s Minimum 0.43 s Conditions: PRBS 2 15, V CC 3.3V 1) SCAN SCAN TTL IEEE LVDS 2 1 EXTEST LVDS go/no go 1 RUNBIST at-speed 66MHz 33ms RX BIST PASS/FAIL TEST_COMPLETE2 PASS BER ( ) 10-7 RUNBIST 4,000 RTI (SCLK 66MHz TCK 1MHz 60 TCLK ) LSP ( ) SCANSTA111 SCAN921025/SCAN
5 SCAN921025/SCAN NSID Function Package SCAN921025SLC Serializer SLC49a SCAN921226SLC Deserializer SLC49a DIN0 Held Low-DIN1 Held High Creates an RMT Pattern DIN4 Held Low-DIN5 Held High Creates an RMT Pattern DIN8 Held Low-DIN9 Held High Creates an RMT Pattern FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output 4
6 (Note 1) (V CC ) 0.3V 4V LVCMOS/LVTTL 0.3V (V CC 0.3V) LVCMOS/LVTTL 0.3V (V CC 0.3V) Bus LVDS 0.3V 3.9V Bus LVDS 0.3V 3.9V Bus LVDS 10mS ( 4 ) 220 (25 ) 49L BGA 1.47 W 49L BGA mw/ ja 85 /W ESD 2kV 250V (V CC ) V (T A ) V CC ) 100 mv P-P SCAN921025/SCAN Symbol Parameter Conditions Min Typ Max Units SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN) V IH High Level Input Voltage 2.0 V CC V V IL Low Level Input Voltage GND 0.8 V V CL Input Clamp Voltage I CL 18 ma V I IN Input Current V IN 0V or 3.6V A DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK inputs; apply to pins ROUT, RCLK, LOCK outputs) V IH High Level Input Voltage 2.0 V CC V V IL Low Level Input Voltage GND 0.8 V V CL Input Clamp Voltage I CL 18 ma V I IN Input Current V IN 0V or 3.6V A V OH High Level Output Voltage I OH 9 ma V CC V V OL Low Level Output Voltage I OL 9 ma GND V I OS Output Short Circuit Current VOUT 0V ma I OS Output Short Circuit Current, ma TDO output I OZ TRI-STATE Output Current PWRDN or REN 0.8V, V OUT 0V or VCC A SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO and DO ) V OD Output Differential Voltage RL 27, Figure 17 (DO ) (DO ) mv V OD Output Differential Voltage Unbalance 35 mv V OS Offset Voltage V V OS Offset Voltage Unbalance mv I OS Output Short Circuit Current D0 0V, DIN High,PWRDN and DEN 2.4V ma I OZ TRI-STATE Output Current PWRDN or DEN 0.8V, DO 0V or VCC A I OX Power-Off Output Current VCC 0V, DO 0V or 3.6V A 5
7 SCAN921025/SCAN ( ) Symbol Parameter Conditions Min Typ Max Units DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI and RI ) VTH Differential Threshold High VCM 1.1V Voltage 6 50 mv VTL Differential Threshold Low Voltage mv I IN Input Current V IN 2.4V, V CC 3.6V or 0V A V IN 0V, V CC 3.6V or 0V A SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I CCD Serializer Supply Current RL 27 f 30 MHz ma Worst Case Figure 2 f 80 MHz ma I CCXD Serializer Supply Current PWRDN 0.8V, f 80MHz Powerdown ma DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC) I CCR Deserializer Supply Current C L 15 pf f 30 MHz ma Worst Case Figure 3 f 80 MHz ma I CCXR Deserializer Supply Current Powerdown PWRDN 0.8V, REN 0.8V ma SCAN CIRCUITRY DC SPECIFICATIONS, SERIALIZER AND DESERIALIZER (applies to SCAN pins as noted) V IH High Level Input Voltage V CC 3.0 to 3.6V, pins TCK, TMS, TDI, and TRST 2.0 V CC V V IL Low Level Input Voltage V CC 3.0 to 3.6V, pins TCK, TMS, TDI, and TRST GND 0.8 V V CL Input Clamp Voltage V CC 3.0V, I CL 18 ma, pins TCK, TMS, TDI, and TRST V I IH Input Current V CC 3.6V, V IN 3.6V, pins TCK, TMS, TDI, and TRST 1 10 A I IL Input Current V CC 3.6V, V IN 0.0V, TCK Input 10 1 A I ILR Input Current V CC 3.6V, V IN 0V, pins TMS, TDI, and TRST A V OH High Level Output Voltage V CC 3.0V, I OH 12 ma, TDO output V V OL Low Level Output Voltage V CC 3.0V, I OL 12 ma, TDO output V I OS Output Short Circuit Current V CC 3.6V, V OUT 0.0V, TDO output ma I OZ TRI-STATE Output Current PWRDN or REN 0.8V, V OUT 0V or VCC A TCLK Symbol Parameter Conditions Min Typ Max Units t TCP Transmit Clock Period 12.5 T 33.3 ns t TCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns t TCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns t CLKT TCLK Input Transition Time 3 6 ns t JIT TCLK Input Jitter 150 ps (RMS) Symbol Parameter Conditions Min Typ Max Units t LLHT Bus LVDS Low-to-High ns Transition Time t LHLT Bus LVDS High-to-Low Transition Time R L 27 C L 10pF to GND Figure 4 (Note 4) ns 6
8 ( ) Symbol Parameter Conditions Min Typ Max Units t DIS DIN (0-9) Setup to TCLK R L 27, 0 ns t DIH DIN (0-9) Hold from TCLK C L 10pF to GND Figure ns t HZD DO HIGH to TRI-STATE Delay 3 10 ns t LZD t ZHD t ZLD DO LOW to TRI-STATE Delay DO TRI-STATE to HIGH Delay DO TRI-STATE to LOW Delay R L 27, C L 10pF to GND Figure 8 (Note 5) 3 10 ns 5 10 ns ns t SPW SYNC Pulse Width R L 27 5*t TCP ns t PLD Serializer PLL Lock Time Figure *t TCP 513*t TCP ns t SD Serializer Delay R L 27, Figure 11 t TCP 1.0 t TCP 2.5 t TCP 3.5 ns t DJIT Deterministic Jitter R L 27, ps t C L 10pF RJIT Random Jitter 80 MHz to GND, 6 10 ps (RMS) (Note 6) SCAN921025/SCAN REFCLK Symbol Parameter Conditions Min Typ Max Units t RFCP REFCLK Period 12.5 T 33.3 ns t RFDC REFCLK Duty Cycle t RFCP / t TCP Ratio of REFCLK to TCLK t RFTT REFCLK Transition Time 3 6 ns Symbol Parameter Conditions Pin/Freq. Min Typ Max Units t RCP Receiver out Clock t RCP t TCP RCLK ns Period Figure 11 t CLH t CHL CMOS/TTL Low-to-High Transition Time CMOS/TTL High-to-Low Transition Time Deserializer Delay Figure 12 CL 15 pf Figure 5 Rout(0-9), LOCK, RCLK ns ns t DD All Temp./ All Freq. 1.75*t RCP *t RCP *t RCP 8.5 ns Room Temp./3.3V/30MHz 1.75*t RCP *t RCP *t RCP 8.0 ns Room Temp./3.3V/80MHz 1.75*t RCP *t RCP *t RCP 8.0 ns t ROS ROUT Data Valid before Figure 13 RCLK RCLK 30MHz 0.4*t RCP 0.5*t RCP ns RCLK 80MHz 0.35*t RCP 0.5*t RCP ns t ROH ROUT Data valid after Figure 13 30MHz 0.4*t RCP 0.5*t RCP ns RCLK 80MHz 0.35*t RCP 0.5*t RCP ns t RDC RCLK Duty Cycle
9 SCAN921025/SCAN ( ) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units t HZR HIGH to TRI-STATE Delay Figure 14 Rout(0-9) ns t LZR LOW to TRI-STATE Delay ns t ZHR TRI-STATE to HIGH Delay ns t ZLR TRI-STATE to LOW Delay ns t DSR1 Deserializer PLL Lock Figure 15 30MHz s Time from PWRDWN Figure 16 (with SYNCPAT) (Note 7) 80MHz s t DSR2 Deserializer PLL Lock time 30MHz s from SYNCPAT 80MHz s t ZHLK TRI-STATE to HIGH Delay (power-up) LOCK ns t RNMI-R Ideal Noise Margin Right Figure MHz 350 ps t RNMI-L Ideal Noise Margin Left Figure MHz 385 ps SCAN Symbol Parameter Conditions Min Typ Max Units f MAX Maximum TCK Clock Frequency R L 500, C L 35 pf MHz t S TDI to TCK, H or L 1.0 ns t H TDI to TCK, H or L 2.0 ns t S TMS to TCK, H or L 2.5 ns t H TMS to TCK, H or L 1.5 ns t W TCK Pulse Width, H or L 10.0 ns t W TRST Pulse Width, L 2.5 ns t REC Recovery Time, TRST to TCK 2.0 ns Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Typ V CC 3.3V T A 25 VOD VOD VTH VTL t LLHT t LHLT TRI-STATE PLL t DJIT REFCLK (SYNCPAT) PLL t DSR1 t DSR2 t DSR1 t DSR2 t DSR1 t DSR2 (R R ) (SYNCPAT) t RNM ( ) 8
10 AC FIGURE 2. Worst Case Serializer ICC Test Pattern SCAN921025/SCAN FIGURE 3. Worst Case Deserializer ICC Test Pattern FIGURE 4. Serializer Bus LVDS Output Load and Transition Times FIGURE 5. Deserializer CMOS/TTL Output Load and Transition Times FIGURE 6. Serializer Input Clock Transition Time 9
11 SCAN921025/SCAN AC ( ) TCLK_R/F LOW FIGURE 7. Serializer Setup/Hold Times FIGURE 8. Serializer TRI-STATE Test Circuit and Timing FIGURE 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays 10
12 AC ( ) SCAN921025/SCAN FIGURE 10. SYNC Timing Delays FIGURE 11. Serializer Delay FIGURE 12. Deserializer Delay 11
13 SCAN921025/SCAN AC ( ) RCLK_R/F LOW (t RDC ) FIGURE 13. Deserializer Data Valid Out Times FIGURE 14. Deserializer TRI-STATE Test Circuit and Timing 12
14 AC ( ) SCAN921025/SCAN FIGURE 15. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays FIGURE 16. Deserializer PLL Lock Time from SyncPAT 13
15 SCAN921025/SCAN AC ( ) V OD (DO ) (DO ) (DO ) (DO ) FIGURE 17. V OD Diagram 14
16 SCAN SCAN LVTTL 800Mbps Bus LVDS PPL 2 PLL (REFCLK) PLL LOCK HIGH CMOS Bus LVDS CMOS I CC SCAN REFCLK TRI-STATE SYNC SYNC1 SYNC2 HIGH SYNC LOCK HIGH LOCK SYNC SYNC LOCK LOW (ROUT0 9) ( ) : TCLK V CC ( ) : ISI V CM : V CC 3 4 LOCK LOW 3 SYNC ( ) BLVDS V CC I/O I/O V CC Figure 21 PCB Bus LVDS 1 Bus LVDS PCB Bus LVDS 1.2V SCAN DS92LV1210 DS92LV mV SCAN mV SCAN SCAN (R 1 ) (R L ) (R 2 ) 15mV Figure 18 SCAN921025/SCAN
17 SCAN921025/SCAN ( ) t DJIT t RNM t RNM t RNM t RNM t DJIT t RNM Figure t RNM AN-1217 How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask SCAN mV FIGURE 18. Failsafe Biasing Setup FIGURE 19. Deterministic Jitter and Ideal Bit Position t RNMI-L t RNMI-R FIGURE 20. Ideal Deserializer Noise Margin (t RNMI ) and Sampling Window 16
18 ( ) SCAN921025/SCAN FIGURE 21. Random Lock Hot Insertion 17
19 SCAN921025/SCAN SCAN921025SLC - Serializer (Top View) SCAN921226SLC - Deserializer (Top View) 18
20 I/O DIN I A3, B1, C1, D1, D2, D3, E1, E2, F2, F4 LVTTL 10 TCLKR/F I G3 / LVTTL DIN TCLK HIGH LOW DO O D7 Bus LVDS DO O D5 Bus LVDS DEN I D6 LVTTL LOW Bus LVDS TRI-STATE PWRDN I C7 LVTTL PWRDN LOW PLL TRI-STATE TCLK I E4 LVTTL 30MHz 80MHz SYNC I A4, B3 Bus LVDS 1024 (HIGH) SYNC 1024 TTL 2 SYNC OR DVCC I C3, C4, E5 DGND I A1, C2, F5, E6, G4 AVCC I A5, A6, B4, (PLL ) B7, G5 AGND I B5, B6, C6, (PLL ) E7, F7 TDI I F1 IEEE IEEE HIGH TDO O G1 IEEE TMS I E3 IEEE IEEE HIGH TCK I F3 IEEE TRST I G2 IEEE IEEE HIGH N/C N/A A2, A7, B2, C5, D4, F6, G6, G7 SCAN921025/SCAN
21 SCAN921025/SCAN I/O ROUT O A5, B4, B6, C4, C7, D6, F5, F7, G4, G5 9mA CMOS RCLKR/F I B3 / TTL ROUT RCLK HIGH LOW RI I D2 Bus LVDS RI I C1 Bus LVDS PWRDN I D3 TTL PWRDN LOW PLL TRI-STATE LOCK O E1 PLL LOCK LOW CMOS RCLK O E2 ROUT CMOS REN I D1 TTL LOW ROUT0 9 LOCK RCLK TRI-STATE DVCC I A7, B7, C5, C6, D5 DGND I A1, A6, B5, D7, E4, E7, G3 AVCC I B1, C2, F1, (PLL ) F2, G1 AGND I A4, B2, F3, (PLL ) F4, G2 REFCLK I A3 PLL REFCLK TDI I F6 IEEE IEEE HIGH TDO O G6 IEEE TMS I G7 IEEE IEEE HIGH TCK I E5 IEEE TRST I E6 IEEE IEEE HIGH N/C N/A A2, C3, D4, E3 INPUTS OUTPUTS PWRDN REN ROUT [0:9] LOCK RCLK H (4) H Z H Z H H Active L Active L X Z Z Z H L Z Active Z 1) LOCK Active LOCK 2) RCLK Active RCLK ROUT RCLK RCLK_R/F 3) ROUT RCLK LOCK HIGH TRI-STATE 4) 20
22 millimeters Order Number SCAN921025SLC or SCAN921226SLC NS Package Number SLC49A (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright 2003 National Semiconductor Corporation SCAN921025/SCAN MHz 10 Bus BLVDS / IEEE (JTAG) at-speed BIST / TEL.(03)
23 IMPORTANT NOTICE
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