SEIKO EPSON CORPORATION 2011, All rights reserved.
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- きょうすけ こしの
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1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17003 Rev. 1.1
2 SEIKO EPSON CORPORATION 2011, All rights reserved.
3 S1 C F 00E : & 0A : TCP BL 2 0B : & BACK 0C : TCP BR 2 0D : TCP BT 2 0E : TCP BD 2 0F : & FRONT 0G: TCP BT 4 0H : TCP BD 4 0J : TCP SL 2 0K : TCP SR 2 0L : & LEFT 0M: TCP ST 2 0N : TCP SD 2 0P : TCP ST 4 0Q: TCP SD 4 0R : & RIGHT 99 : D: F: QFP B: BGA C: S1: S5U1 C H : 1: Version 1 Hx : ICE Dx : Ex : ROM Mx: ROM Tx : Cx : Sx : 33L01: S1C33L01 C: S5U1:
4 CPU S1C CPU PSR , ROM ROM ROM x5320: ROM Control Register (MISC_FL) RAM RAM x5326: IRAM Size Select Register (MISC_IRAMSZ) x4000~ x5000~ I/O LVDD, VSS I/O HVDD AVDD #RESET P ITC ITC S1C17003 TECHNICAL MANUAL Seiko Epson Corporation i
5 6.3.2 ITC S1C NMI HALT, SLEEP x4306: Interrupt Level Setup Register 0 (ITC_LV0) x4308: Interrupt Level Setup Register 1 (ITC_LV1) x430a: Interrupt Level Setup Register 2 (ITC_LV2) x430c: Interrupt Level Setup Register 3 (ITC_LV3) x430e: Interrupt Level Setup Register 4 (ITC_LV4) x4310: Interrupt Level Setup Register 5 (ITC_LV5) x4312: Interrupt Level Setup Register 6 (ITC_LV6) x4314: Interrupt Level Setup Register 7 (ITC_LV7) x4316: Interrupt Level Setup Register 8 (ITC_LV8) x4318: Interrupt Level Setup Register 9 (ITC_LV9) OSC OSC OSC OSC OSC FOUTH, FOUT RESET, NMI x5060: Clock Source Select Register (OSC_SRC) x5061: Oscillation Control Register (OSC_CTL) x5062: Noise Filter Enable Register (OSC_NFEN) x5064: FOUT Control Register (OSC_FOUT) x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) CLG CPU CCLK PCLK x5080: PCLK Control Register (CLG_PCLK) x5081: CCLK Control Register (CLG_CCLK) PSC x4020: Prescaler Control Register (PSC_CTL) P MUX ii Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
6 10.5 P0/P x5200/0x5210/0x5220/0x5230/0x5240: Px Port Input Data Registers (Px_IN) x5201/0x5211/0x5221/0x5231/0x5241: Px Port Output Data Registers (Px_OUT) x5202/0x5212/0x5222/0x5232/0x5242: Px Port Output Enable Registers (Px_OEN) x5203/0x5213/0x5223/0x5233/0x5243: Px Port Pull-up Control Registers (Px_PU) x5205/0x5215: Px Port Interrupt Mask Registers (Px_IMSK) x5206/0x5216: Px Port Interrupt Edge Select Registers (Px_EDGE) x5207/0x5217: Px Port Interrupt Flag Registers (Px_IFLG) x5208/0x5218: P0/P1 Port Chattering Filter Control Register (Px_CHAT) x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) x520a/0x521a/0x522a/0x523a/0x524a: Px Port Input Enable Registers (Px_IEN) x52a0: P0 Port Function Select Register (P0_PMUX) x52a1: P0 Port Function Select Register (P0_PMUX) x52a2: P1 Port Function Select Register (P1_PMUX) x52a3: P1 Port Function Select Register (P1_PMUX) x52a4: P2 Port Function Select Register (P2_PMUX) x52a5: P2 Port Function Select Register (P2_PMUX) x52a6: P3 Port Function Select Register (P3_PMUX) x52a7: P3 Port Function Select Register (P3_PMUX) x52a8: P4 Port Function Select Register (P4_PMUX) T RUN/STOP x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx) x4228/0x4248/0x4268: 16-bit Timer Ch.x Interrupt Control Registers (T16_INTx) T8F RUN/STOP S1C17003 TECHNICAL MANUAL Seiko Epson Corporation iii
7 x4200/0x4280: 8-bit Timer Ch.x Input Clock Select Register (T8F_CLKx) x4202/0x4282: 8-bit Timer Ch.x Reload Data Register (T8F_TRx) x4204/0x4284: 8-bit Timer Ch.x Counter Data Register (T8F_TCx) x4206/0x4286: 8-bit Timer Ch.x Control Register (T8F_CTLx) x4208/0x4288: 8-bit Timer Ch.x Interrupt Control Register (T8F_INTx) PWM T16E PWM PWM / PWM RUN/STOP PWM x5300: PWM Timer Compare Data A Registers (T16E_CA) x5302: PWM Timer Compare Data B Registers (T16E_CB) x5304: PWM Timer Counter Data Registers (T16E_TC) x5306: PWM Timer Control Registers (T16E_CTL) x5308: PWM Timer Input Clock Select Registers (T16E_CLK) x530a: PWM Timer Interrupt Mask Registers (T16E_IMSK) x530c: PWM Timer Interrupt Flag Registers (T16E_IFLG) OSC1 T8OSC OSC OSC OSC OSC1 RUN/STOP OSC PWM x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK) x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) x50c5: 8-bit OSC1 Timer PWM Duty Data Register (T8OSC1_DUTY) CT RUN/STOP x5000: Clock Timer Control Register (CT_CTL) x5001: Clock Timer Counter Register (CT_CNT) x5002: Clock Timer Interrupt Mask Register (CT_IMSK) iv Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
8 0x5003: Clock Timer Interrupt Flag Register (CT_IFLG) SWT BCD RUN/STOP x5020: Stopwatch Timer Control Register (SWT_CTL) x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) WDT NMI/ RUN/STOP x5040: Watchdog Timer Control Register (WDT_CTL) x5041: Watchdog Timer Status Register (WDT_ST) UART UART UART UART IrDA x4100/0x4120: UART Ch.x Status Registers (UART_STx) x4101/0x4121: UART Ch.x Transmit Data Registers (UART_TXDx) x4102/0x4122: UART Ch.x Receive Data Registers (UART_RXDx) x4103/0x4123: UART Ch.x Mode Registers (UART_MODx) x4104/0x4124: UART Ch.x Control Registers (UART_CTLx) x4105/0x4125: UART Ch.x Expansion Registers (UART_EXPx) SPI SPI SPI SPI S1C17003 TECHNICAL MANUAL Seiko Epson Corporation v
9 SPI x4320: SPI Status Register (SPI_ST) x4322: SPI Transmit Data Register (SPI_TXD) x4324: SPI Receive Data Register (SPI_RXD) x4326: SPI Control Register (SPI_CTL) I 2 C I 2 CM I 2 C I 2 C I 2 C I 2 C x4340: I 2 C Enable Register (I2C_EN) x4342: I 2 C Control Register (I2C_CTL) x4344: I 2 C Data Register (I2C_DAT) x4346: I 2 C Interrupt Control Register (I2C_ICTL) I 2 C I 2 CS I 2 C I 2 C I 2 C I 2 C I 2 C x4360: I 2 C Slave Transmit Data Register (I2CS_TRNS) x4362: I 2 C Slave Receive Data Register (I2CS_RECV) x4364: I 2 C Slave Address Setup Register (I2CS_SADRS) x4366: I 2 C Slave Control Register (I2CS_CTL) x4368: I 2 C Slave Status Register (I2CS_STAT) x436a: I 2 C Slave Access Status Register (I2CS_ASTAT) x436c: I 2 C Slave Interrupt Control Register (I2CS_ICTL) REMC REMC REMC REMC x5340: REMC Configuration Register (REMC_CFG) x5342: REMC Carrier Length Setup Register (REMC_CAR) x5344: REMC Length Counter Register (REMC_LCNT) x5346: REMC Interrupt Control Register (REMC_INT) vi Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
10 A/D ADC10SA A/D ADC A/D A/D A/D x5380: ADC10 Conversion Result Register (ADC10_ADD) x5382: ADC10 Trigger/Channel Select Register (ADC10_TRG) x5384: ADC10 Control/Status Register (ADC10_CTL) x5386: ADC10 Divided Frequency Register (ADC10_DIV) DBG x5322: OSC1 Peripheral Control Register (MISC_OSC1) x5326: IRAM Size Select Register (MISC_IRAMSZ) xffff90: Debug RAM Base Register (DBRAM) xffffa0: Debug Control Register (DCR) xffffb8: Instruction Break Address Register 2 (IBAR2) xffffbc: Instruction Break Address Register 3 (IBAR3) xffffd0: Instruction Break Address Register 4 (IBAR4) A/D SPI I 2 C TQFP12-64pin WCSP S1C17003 TECHNICAL MANUAL Seiko Epson Corporation vii
11 Appendix A I/O... AP-1 0x4020 Prescaler... AP-5 0x4100 0x4125 UART (with IrDA)... AP-6 0x4200 0x bit Timer (with Fine Mode) Ch.0... AP-8 0x4220 0x bit Timer... AP-9 0x4280 0x bit Timer (with Fine Mode) Ch.1... AP-11 0x4306 0x4318 Interrupt Controller... AP-12 0x4320 0x4326 SPI... AP-13 0x4340 0x4346 I 2 C Master... AP-14 0x4360 0x436c I 2 C Slave... AP-15 0x5000 0x5003 Clock Timer... AP-16 0x5020 0x5023 Stopwatch Timer... AP-17 0x5040 0x5041 Watchdog Timer... AP-18 0x5060 0x5065 Oscillator... AP-19 0x5080 0x5081 Clock Generator... AP-20 0x50c0 0x50c5 8-bit OSC1 Timer... AP-21 0x5200 0x52a8 P Port & Port MUX... AP-22 0x5300 0x530c PWM & Capture Timer... AP-26 0x5320 0x532c MISC Registers... AP-27 0x5340 0x5346 Remote Controller... AP-28 0x5380 0x5386 ADC10SA... AP-29 0xffff84 0xffffd0 S1C17 Core I/O... AP-30 Appendix B... AP-31 B.1... AP-31 Appendix C... AP-34 Appendix D ROM... AP-38 viii Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
12 1 1 S1C17003 ICE 16 MCU A/D I/F S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-1
13 1 1.1 S1C17003 CPU EPSON 16 RISC CPU S1C OSC3 20MHz (max.) ( / ) OSC kHz(typ.) ( ) Mask ROM 64K RAM 4K A/D 10 4ch 30 4 SPI / 1ch. I 2 C 1ch. I 2 C 1ch. UART bps IrDA1.0 2ch. REMC 1ch. 8 T8F 2ch. 16 T16 3ch. PWM T16E 1ch. CT 1ch. SWT 1ch. WDT 1ch. 8 OSC1 PWM T8OSC1 1ch. NMI P HVDD(I/O) 1.65~3.6V LVDD( ) 1.65~1.95V AVDD(I/O) 2.7V 3.6V C SLEEP 1µA (typ.)off/1.8v HALT 3.3µA (typ.)32khz/1.8v 4.0mA (typ.)20mhz/1.8v TQFP12-64pin(7mm 7mm 1.2mm 0.4mm) WCSP-48pin(3.124mm 3.124mm 0.78mm 0.4mm) (3.124mm 3.124mm 0.40mm) 1-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
14 bits 1 cycle Internal RAM (4K bytes) CPU Core S1C17 8/16 bits 1 cycle I/O 2 (0x5000 ) DCLK, DST2, DSIO(P41 43) Mask ROM (64K bytes) 16 bits 1 5 cycles A/D converter AIN0 3,#ADTRG (P22 20, P17) MISC register TEST Test circuit #RESET Reset circuit Oscillator/ Clock generator OSC1 2, OSC3 4 FOUT1(P35), FOUTH(P40) I/O 1 (0x4000 ) Interrupt controller 8/16 bits 1 cycle Interrupt system 8-bit OSC1 PWM timer TOUT4(P37) Prescaler Clock timer 8-bit timer Stopwatch timer EXCL0 2 (P02, P13, P14) SIN0, SOUT0, SCLK0(P12 10), SIN1, SOUT1, SCLK1(P30 29,P16) 16-bit timer UART (2ch) Watchdog timer 16-bit PWM timer EXCL3(P15), TOUT3(P36), TOUTN3(P37) SDI, SDO, SPICLK(P06 04) #SPISS(P07) SPI Remote controller REMI(P01), REMO(P00) SDA0, SCL0(P32 31) or (P34 33) SDA1, SCL1(P34 33) #BFR(P35) I 2 C master (1ch) I 2 C slave (1ch) I/O port/ I/O MUX P00 07, P10 17, P20 24, P27, P30 37, P S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-3
15 S1C17003 TQFP12-64pin WCSP-48 TQFP12-64pin P23 VSS P24 (SOUT1) P27 (SIN1) P30 LVDD HVDD (SCL0) P31 (SDA0) P32 (SCL1/SCL0) P33 (SDA1/SDA0) P34 (FOUT1/#BFR) P35 HVDD (TOUT3) P36 (TOUTN3) P37 VSS LVDD N.C. P07 (#SPISS) P06 (SDI) HVDD P05 (SDO) P04 (SPICLK) VSS OSC4 VSS N.C. OSC3 VSS OSC2 VSS OSC1 (SCLK) P10 LVDD (SOUT) P11 (SIN) P12 (EXCL1) P13 (EXCL2) P14 HVDD VSS (EXCL3) P15 (SCLK1) P16 N.C. AVDD (AIN3) P17 (AIN2) P20 (AIN1) P21 (AIN0) P VSS P03 (#ADTRG) P02 (EXCL0) P01 (REMI) P00 (REMO) N.C. #RESET LVDD TEST DCLK (P43) LVDD DST2 (P42) HVDD VSS DSIO (P41) P40 (FOUTH) TQFP12-64pin 1-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
16 1 WCSP-48 A1 Corner Top View Bottom View A1 Corner A A B C D E F G Index B C D E F G Top View A 1 P P24 P30 P31 P34 P36 P40 SIN1 SCL0 SDA1 TOUT3 FOUTH SDA0 B P21 AIN1 P22 AIN0 P27 SOUT1 P32 SDA0 P35 FOUT1 #BFR P37 TOUTN3 DSIO P41 C P17 AIN3 P20 AIN2 HVDD P33 SCL1 SCL0 VSS DST2 P42 D P15 EXCL3 P16 SCLK1 AVDD VSS LVDD DCLK P43 TEST E P14 EXCL2 P13 EXCL1 P12 SIN HVDD P01 REMI P00 REMO #RESET F P11 SOUT LVDD P06 SDI P04 SPICLK VSS P03 #ADTRG P02 EXCL0 G P10 SCLK P07 #SPISS P05 SDO OSC4 OSC3 OSC2 OSC WCSP-48 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-5
17 1 CHIP-88pad Y (0, 0) X mm mm 1-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
18 1 PAD No. X (mm) Y (mm) PAD No. X (mm) Y (mm) P NC VSS OSC VSS VSS P VSS NC OSC P NC P VSS LVDD OSC LVDD NC HVDD VSS HVDD OSC P VSS P NC P P P P P HVDD HVDD P P P P NC VSS LVDD VSS NC NC NC NC P P NC NC LVDD DSIO LVDD VSS P VSS P HVDD P DST P LVDD HVDD DCLK VSS TEST P LVDD VSS LVDD P #RESET AVDD NC NC P AVDD P P17/AIN P P20/AIN NC AVDD P P21/AIN VSS P22/AIN VSS NC S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-7
19 PAD / / No. CHIP TQFP WCSP I/O / 1 1 A1 P23 I/O I(Pull-UP) *2 2 *2 VSS - - ( ) 4 3 A2 P24 I/O I(Pull-UP) 6 4 B3 P27/SOUT1 I/O I(Pull-UP) *1 / UART Ch1 7 5 A3 P30/SIN1 I/O I(Pull-UP) *1 / UART Ch1 *3 6 *3 LVDD - - (+) *4 7 *4 HVDD - - I/O (+) 12 8 A4 P31/SCL0 I/O I(Pull-UP) *1 /I2C 13 9 B4 P32/SDA0 I/O I(Pull-UP) *1 /I2C C5 P33/SCL1/SCL0 I/O I(Pull-UP) *1/I2C /I2C A5 P34/SDA1/SDA0 I/O I(Pull-UP) *1/I2C /I2C B5 P35/FOUT1/#BFR I/O I(Pull-UP) *1/OSC1 /I2C *4 13 *4 HVDD - - I/O (+) A6 P36/TOUT3 I/O I(Pull-UP) *1 /T16E Ch0 PWM ( ) B6 P37/TOUTN3 I/O I(Pull-UP) *1 /T16E Ch0 PWM ( ) *2 16 *2 VSS - - ( ) A7 P40/FOUTH I/O I(Pull-UP) *1 /HSCLK ( ) B7 DSIO/P41 I/O I(Pull-UP) *1 / *2 19 *2 VSS - - ( ) *4 20 *4 HVDD - - I/O (+) C7 DST2/P42 I/O O(L) *1 / *3 22 *3 LVDD - - (+) D6 DCLK/P43 I/O O(H) *1 / D7 TEST I I(Pull-DN) ( VSS ) *3 25 *3 LVDD - - (+) E7 #RESET I I(Pull-UP) ( ) NC E6 P00/REMO I/O I(Pull-UP) *1 /REMC E5 P01/REMI I/O I(Pull-UP) *1 /REMC F7 P02/EXCL0 I/O I(Pull-UP) *1/T16 Ch F6 P03/#ADTRG I/O I(Pull-UP) *1 /AD *2 32 *2 VSS - - ( ) G7 OSC1 I I OSC1 *6 *2 34 *2 VSS - - ( ) G6 OSC2 O O OSC1 1-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
20 1 PAD / / No. CHIP TQFP WCSP I/O / *2 36 *2 VSS - - ( ) G5 OSC3 I I OSC3 * NC *2 39 *2 VSS - - ( ) G4 OSC4 O O OSC3 *2 41 *2 VSS - - ( ) F4 P04/SPICLK I/O I(Pull-UP) *1 /SPI G3 P05/SDO I/O I(Pull-UP) *1 /SPI *4 44 *4 HVDD - - I/O (+) F3 P06/SDI I/O I(Pull-UP) *1 /SPI G2 P07/#SPISS I/O I(Pull-UP) *1/SPI NC *3 48 *3 LVDD - - (+) G1 P10/SCLK I/O I(Pull-UP) *1/UART Ch0 *3 50 *3 LVDD - - (+) F1 P11/SOUT I/O I(Pull-UP) *1/UART Ch E3 P12/SIN I/O I(Pull-UP) *1 /UART Ch E2 P13/EXCL1 I/O I(Pull-UP) *1/T16 Ch E1 P14/EXCL2 I/O I(Pull-UP) *1/T16 Ch2 *4 55 *4 HVDD - - I/O (+) *2 56 *2 VSS - - ( ) D1 P15/EXCL3 I/O I(Pull-UP) *1/T16E Ch D2 P16/SCLK1 I/O I(Pull-UP) *1/UART Ch NC *5 60 D3 AVDD - - (+) C1 P17/AIN3 I I *1 / AD Ch C2 P20/AIN2 I I *1 / AD Ch B1 P21/AIN1 I I *1 / AD Ch B2 P22/AIN0 I I *1 / AD Ch0 *1 *2 VSS PAD No. 2, 3, 20, 21, 27, 28, 43, 44, 47, 48, 51, 54, 56, 76, 78 VSS BALL No. C6, D4, F5 *3 LVDD PAD No. 8, 9, 31, 34, 35, 64, 69, 70 LVDD BALL No. D5, F2 *4 HVDD PAD No. 10, 11, 17, 29, 60, 75 HVDD BALL No. C4, E4 *5 AVDD PAD No. 80, 82, 85 *6 OSC3 OSC1 LVDD NC pin TQFP NC CHIP/WCSP No. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-9
21 2 CPU 2 CPU S1C17003 S1C17 S1C17 16 RISC 1 8 CPU S1C17 S1C17 Family S1C S1C17 16 RISC µm CMOS C , 16M NMI 32 HALT halt SLEEP slp S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-1
22 2 CPU 2.2 CPU S1C PC 7 SP 6 PSR IL[2:0] IE C V Z N R7 R6 R5 R4 R3 R2 R1 R Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
23 2 CPU 2.3 S1C S1C17 Family S1C S1C17 ld.b %rd,%rs ( ) ( ) %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) [imm7],%rs ( ) ld.ub %rd,%rs ( ) ( ) %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] ( ) ( ) ( ) ( ) %rd,[imm7] ( ) ( ) ld %rd,%rs (16 ) %rd,sign7 ( ) %rd,[%rb] %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs (16 ) (16 ) (16 ) (16 ) (16 ) [imm7],%rs (16 ) ld.a %rd,%rs (24 ) %rd,imm7 ( ) %rd,[%rb] (32 ) (*1) %rd,[%rb]+ %rd,[%rb]- %rd,-[%rb] %rd,[%sp+imm7] (32 ) (*1) %rd,[imm7] (32 ) (*1) [%rb],%rs (32 ) (*1) [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs (32 ) (*1) [imm7],%rs (32 ) (*1) %rd,%sp SP %rd,%pc PC %rd,[%sp] (32 ) (*1) %rd,[%sp]+ %rd,[%sp]- %rd,-[%sp] S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-3
24 2 CPU ld.a [%sp],%rs (32 ) (*1) [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs (24 ) SP %sp,imm7 SP add %rd,%rs 16 add/c add/nc add %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 add.a %rd,%rs 24 add.a/c (/c: C = 1, /nc: C = 0 ) add.a/nc add.a %sp,%rs SP 24 %rd,imm7 24 %sp,imm7 SP 24 adc %rd,%rs 16 adc/c adc/nc adc %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 sub %rd,%rs 16 sub/c sub/nc sub %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 sub.a %rd,%rs 24 sub.a/c sub.a/nc sub.a %sp,%rs (/c: C = 1, /nc: C = 0 ) SP 24 %rd,imm7 24 %sp,imm7 SP 24 sbc %rd,%rs 16 sbc/c sbc/nc sbc %rd,imm7 (/c: C = 1, /nc: C = 0 ) 16 cmp %rd,%rs 16 cmp/c cmp/nc cmp %rd,sign7 (/c: C = 1, /nc: C = 0 ) 16 cmp.a %rd,%rs 24 cmp.a/c cmp.a/nc cmp.a %rd,imm7 (/c: C = 1, /nc: C = 0 ) 24 cmc %rd,%rs 16 cmc/c cmc/nc cmc %rd,sign7 (/c: C = 1, /nc: C = 0 ) 16 and %rd,%rs and/c and/nc and %rd,sign7 (/c: C = 1, /nc: C = 0 ) or %rd,%rs or/c or/nc or %rd,sign7 (/c: C = 1, /nc: C = 0 ) xor %rd,%rs xor/c xor/nc xor %rd,sign7 (/c: C = 1, /nc: C = 0 ) not %rd,%rs (1 ) not/c not/nc not %rd,sign7 (/c: C = 1, /nc: C = 0 ) (1 ) 2-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
25 2 CPU & sr %rd,%rs ( ) %rd,imm7 ( ) sa %rd,%rs ( ) %rd,imm7 ( ) sl %rd,%rs ( ) %rd,imm7 ( ) swap %rd,%rs 16 ext imm13 cv.ab %rd,%rs 8 24 cv.as %rd,%rs cv.al %rd,%rs cv.la %rd,%rs cv.ls %rd,%rs sign10 jpr jpr.d jpa jpa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d PC %rb imm7 %rb sign7 PC :!Z &!(N ^ V) sign7 PC :!(N ^ V) sign7 PC : N ^ V sign7 PC : Z N ^ V sign7 PC :!Z &!C sign7 PC :!C sign7 PC : C sign7 PC : Z C sign7 PC : Z sign7 PC :!Z sign10 PC %rb imm7 %rb int imm5 intl imm5,imm3 reti reti.d brk retd nop halt HALT slp SLEEP ei di ld.cw %rd,%rs %rd,imm7 ld.ca %rd,%rs %rd,imm7 ld.cf %rd,%rs %rd,imm7 *1 ld.a S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-5
26 2 CPU %rs %rd [%rb] [%rb]+ [%rb]- -[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]- -[%sp] imm3,imm5,imm7,imm13 sign7,sign ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 2-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
27 2 CPU 2.4 S1C17 6. ITC MISC_TTBRL MISC_TTBRH 0x5328 0x532a TTBR MISC_TTBRL/MISC_TTBRH 0x8000 MISC_TTBRL x5328 0x532a: Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) Register name Address Bit Name Function Setting Init. R/W Remarks Vector Table 0x5328 D15 8 TTBR[15:8] Vector table base address A[15:8] 0x0 0xff 0x80 R/W Address Low Register (MISC_TTBRL) (16 bits) D7 0 TTBR[7:0] Vector table base address A[7:0] (fixed at 0) 0x0 0x0 R Vector Table Address High Register (MISC_TTBRH) 0x532a (16 bits) D15 8 reserved 0 when being read. D7 0 TTBR[23:16] Vector table base address A[23:16] 0x0 0xff 0x0 R/W : MISC_TTBRL/MISC_TTBRH MISC Protect Register 0x5324 0x96 MISC_TTBRL/MISC_TTBRH MISC Protect Register 0x5324 0x96 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-7
28 2 CPU 2.5 PSR S1C17003 S1C17 PSR Processor Status Register PSR Register 0x532c PSR PSR 0x532c: PSR Register (MISC_PSR) Register name Address Bit Name Function Setting Init. R/W Remarks PSR Register (MISC_PSR) 0x532c (16 bits) D15 8 reserved 0 when being read. D7 5 PSRIL[2:0] PSR interrupt level (IL) bits 0x0 to 0x7 0x0 R D4 PSRIE PSR interrupt enable (IE) bit 1 1 (enable) 0 0 (disable) 0 R D3 PSRC PSR carry (C) flag 1 1 (set) 0 0 (cleared) 0 R D2 PSRV PSR overflow (V) flag 1 1 (set) 0 0 (cleared) 0 R D1 PSRZ PSR zero (Z) flag 1 1 (set) 0 0 (cleared) 0 R D0 PSRN PSR negative (N) flag 1 1 (set) 0 0 (cleared) 0 R D[7:5] D4 D3 D2 D1 D0 PSRIL[2:0]: PSR Interrupt Level (IL) Bits PSR IL : 0x0 PSRIE: PSR Interrup Enable (IE) Bit PSR IE 1 R : 1 0 R : 0 PSRC: PSR Carry (C) Flag PSR C 1 R : 1 0 R : 0 PSRV: PSR Overflow (V) Flag PSR V 1 R : 1 0 R : 0 PSRZ: PSR Zero (Z) Flag PSR Z 1 R : 1 0 R : 0 PSRN: PSR Negative (N) Flag PSR N 1 R : 1 0 R : Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
29 2 CPU 2.6 S1C17003 Processor ID Register 0xffff84 CPU 0xffff84: Processor ID Register (IDIR) Register name Address Bit Name Function Setting Init. R/W Remarks Processor ID Register (IDIR) 0xffff84 (8 bits) D7 0 IDIR[7:0] Processor ID 0x10: S1C17 Core 0x10 0x10 R ID S1C17 ID 0x10 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-9
30 3, 3, 3.1 S1C17003 ( ) 0xff ffff 0xff fc00 0xff fbff 0x x01 7fff 0x x00 7fff 0x x00 5fff 0x x00 4fff 0x x00 43ff 0x x00 3fff 0x x00 0fff 0x00 0fc0 0x I/O (1K, 1 ) reserved Mask ROM (64K ) reserved 2 (4K, 1 ) reserved 1 (1K, 1 ) reserved RAM (64 ) RAM (4K, 1 ) ( : 32 ) 0x5400~0x5fff reserved 0x53c0~0x53ff reserved 0x53a0~0x53bf reserved 0x5380~0x539f A/D 0x5360~0x537f reserved 0x5340~0x535f 0x5320~0x533f MISC 0x5300~0x531f PWM Ch.0 0x52c0~0x52ff reserved 0x52a0~0x52bf MUX 0x5280~0x529f reserved 0x5200~0x527f P 0x5140~0x51ff reserved 0x5120~0x513f reserved 0x5100~0x511f reserved 0x50e0~0x50ff reserved 0x50c0~0x50df 8 OSC1 0x50a0~0x50bf reserved 0x5080~0x509f 0x5060~0x507f 0x5040~0x505f 0x5020~0x503f 0x5000~0x501f 0x4380~0x43ff reserved 0x4360~0x437f I 2 C 0x4340~0x435f I 2 C 0x4320~0x433f SPI 0x42c0~0x431f 0x4280~0x42ff 8 Ch.1 0x4260~0x427f 16 Ch.2 0x4240~0x425f 16 Ch.1 0x4220~0x423f 16 Ch.0 0x4200~0x421f 8 Ch.0 0x4120~0x41ff UART Ch.1 0x4100~0x411f UART Ch.0 0x4040~0x40ff reserved 0x4020~0x403f 0x4000~0x401f reserved (16 ) (16 ) (16 ) (16 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (8 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (16 ) (8 ) (8 ) (8 ) 3.1 S1C17003 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 3-1
31 3, 3.1 CPU CCLK CCLK 8.2 CPU CCLK CCLK 1 CCLK CPU CPU * * * 1 * PSR / RAM RAM 3-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
32 3, 3.2 ROM ROM 0x8000 0x17fff 64K ROM 0x8000 ( 2.4 ) MISC_TTBRL/MISC_TTBRH (0x5328 0x532a) ROM ROM S1C17602 ROM FLCYC[2:0](D[2:0]/ MISC_FL ) FLCYC[2:0] 0x4 0x5320: ROM Control Register (MISC_FL) Register name Address Bit Name Function Setting Init. R/W Remarks ROM Control 0x5320 D15-3 reserved 0 when being read. Register (MISC_FL) (16bits) D2-0 FLCYC[2:0] FLASHC read access cycle FLCYC[2:0] Read cycle 0x3 R/W 0x7-0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 cycle 5 cycles 4 cycles 3 cycles 2 cycles D[2:0] FLCYC[2:0]: FLASHC Read Access Cycle Setup Bits ROM ROM FLCYC[2:0] CCLK 0x7 0x5 Reserved 0x4 1 20MHz max. 0x3 5 20MHz max. 0x2 4 20MHz max. 0x1 3 20MHz max. 0x0 2 20MHz max. : 0x3 : CCLK FLCYC[2:0]=0x4 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 3-3
33 3, 3.3 RAM RAM 0x0 0xfff 4K RAM RAM / 1 RAM : RAM 64 0xfc0 0xfff S1C17003 RAM 4KB 2KB S1C17003 ROM RAM RAM IRAMSZ[1:0] D[1:0]/MISC_IRAMSZ 0x5326: IRAM Size Select Register (MISC_IRAMSZ) Register name Address Bit Name Function Setting Init. R/W Remarks IRAM Size 0x5326 D15 2 reserved 0 when being read. Select Register (MISC_IRAMSZ) (16 bits) D1 0 IRAMSZ[1:0] IRAM size select IRAMSZ[1:0] Read cycle 0x2 R/W 0x3 0x2 0x1 0x0 reserved reserved reserved reserved D[1:0] IRAMSZ[1:0]: IRAM Size Select Bits RAM RAM IRAMSZ[1:0] RAM 0x3 reserved 0x2 reserved 0x1 reserved 0x0 reserved : 0x2 : IRAM Size Select Register MISC Protect Register 0x5324 0x96 IRAM Size Select Register MISC Protect Register 0x5324 0x96 IRAMSZ[2:0]/MISC_IRAMSZ 3-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
34 3, 3.4 0x4000 1K 0x5000 4K I/O x4000~ 0x I/O 1 PSC, 8 UART UART, 8 8 T8F, T16, 16 ITC, 16 SPI SPI, 16 I 2 C I2C, 16 I 2 C I2C, x5000~ 0x I/O 1 CT, 8 SWT, 8 WDT, 8 OSC, 8 CLG, 8 8 OSC1 PWM T8OSC1, 8 & MUX P, 8 PWM T16E, 16 MISC MISC, 16 REMC, 16 A/D ADC10, 16 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 3-5
35 3, 3.5 I/O 0xfffc00 0xffffff 1K CPU I/O I/O I/O I/O S1C17 I/O 0xffff84 IDIR Processor ID Register ID 0xffff90 DBRAM Debug RAM Base Register RAM 0xffffa0 DCR Debug Control Register 0xffffb8 IBAR2 Instruction Break Address Register 2 #2 0xffffbc IBAR3 Instruction Break Address Register 3 #3 0xffffd0 IBAR4 Instruction Break Address Register 4 #4 IDIR DBG S1C17 S1C Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
36 4 4 SIC S1C TQFP Pin No. WCSP I/O PU/PD HVDD 7, 13, 20, 44, 55 C4, E4 3.3V I/O (+)(1.8V/2.5V/3.3V) LVDD 6, 22, 25, 48, 50 D5, F2 1.8V (+)(1.8V) VSS 2, 16, 19, 32, 34, 36, D4, C6, F5 GND GND 39, 41, 56 AVDD 60 D3 3.3V (3.0V/3.3V) 1.8V Typ. ( V) GND LVDD VSS CPU V HVDD I/O V AVDD (A/D ) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 4-1
37 4 4.2 LVDD, VSS S1C17003 CPU LVDD VSS LVDD = 1.65V 1.95V 1.80V ± 0.15V VSS = GND : S1C17003 TQFP 5 LVDD 9 VSS WCSP 2 LVDD 3 VSS 4.3 I/O HVDD HVDD S1C17003 High HVDD Low VSS GND LVDD VSS HVDD HVDD = 1.65V 3.60V VSS = GND : S1C17003 TQFP 5 WCSP 2 HVDD OSC3 OSC1 LVDD 4.4 AVDD A/D LVDD HVDD AVDD AVDD VSS GND AVDD AVDD = 2.70V 3.60V 1.65V 3.60V VSS = GND : AVDD V HVDD ADC P0x AVDD = V High AVDD Low GND A/D 4-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
38 4 4.5 HVDD, AVDD LVDD OSC3 tlvdd LVDD min. tsta3 trst #RESET tlvdd: : LVDD HVDD I/O, AVDD A/D LVDD, HVDD I/O, AVDD A/D " " 2 tsta3: OSC3 3 trst: 6 #RESET Low : HVDD : HVDD I/O, AVDD A/D LVDD HVDD I/O, AVDD A/D, LVDD : LVDD LVDD HVDD AVDD HVDD AVDD LVDD HVDD AVDD 1 HVDD AVDD CMOS CMOS IC PNPN HVDD VSS HVDD HVDD VSS 1 VSS 2 3 HVDD AVDD VSS 4 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 4-3
39 S1C #RESET 2 P0 P00 P VDD S Q #RESET R P00 P01 P02 P03 P0KRST WDTMD CPU CPU #RESET #RESET Low S1C17003 #RESET Low 26.4 #RESET Low High CPU #RESET S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 5-1
40 P0 P00 P03 Low P0KRST[1:0] D[1:0]/P0_KRST * P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits in the P0 Port Key-Entry Reset Configuration (P0_KRST) Register (D[1:0]/0x5209) P0 P0KRST[1:0] 0x3 0x2 0x1 0x0 P00, P01, P02, P03 P00, P01, P02 P00, P01 P0KRST[1:0] 0x3 P00 P03 4 Low : P0 Low P0 SLEEP P S1C17003 CPU 4 CPU NMI WDTMD D1/WDT_ST 1 WDTMD 0 NMI * WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041) 17 WDT : Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
41 5 5.2 #RESET CPU CPU fosc3 * fosc3: OSC3 : SLEEP S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 5-3
42 5 5.3 CPU R0 R7: 0x0 PSR: 0x0 = 0 SP: 0x0 PC: RAM Appendix I/O 5-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
43 6 ITC 6 ITC 6.1 ITC ITC / S1C17 NMI S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-1
44 6 ITC 6.2 S1C17 MISC_TTBRL MISC_TTBRH 0x5328 0x532a TTBR MISC_TTBRL/MISC_TTBRH 0x S1C No./ No. 0 (0x00) TTBR + 0x00 #RESET Low *2 1 (0x01) TTBR + 0x04 2 (0xfffc00) brk 3 2 (0x02) TTBR + 0x08 NMI *2 4 3 (0x03) TTBR + 0x0c C reserved C 4 (0x04) TTBR + 0x10 P0 P00~P07 *1 5 (0x05) TTBR + 0x14 P1 P10~P17 6 (0x06) TTBR + 0x18 100Hz 10Hz 1Hz 7 (0x07) TTBR + 0x1c 32Hz 8Hz 2Hz 1Hz 8 (0x08) TTBR + 0x20 8 OSC1 9 (0x09) TTBR + 0x24 reserved 10 (0x0a) TTBR + 0x28 reserved 11 (0x0b) TTBR + 0x2c PWM Ch.0 A B 12 (0x0c) TTBR + 0x30 8 Ch.0/Ch.1 13 (0x0d) TTBR + 0x34 16 Ch.0 14 (0x0e) TTBR + 0x38 16 Ch.1 15 (0x0f) TTBR + 0x3c 16 Ch.2 16 (0x10) TTBR + 0x40 UART Ch.0 17 (0x11) TTBR + 0x44 UART Ch.1 /I 2 C UART Ch1 UART Ch1 UART Ch1 I 2 C I 2 C I 2 C 18 (0x12) TTBR + 0x48 SPI 19 (0x13) TTBR + 0x4c I 2 C 20 (0x14) TTBR + 0x50 21 (0x15) TTBR + 0x54 reserved 22 (0x16) TTBR + 0x58 A/D 23 (0x17) TTBR + 0x5c reserved 24 (0x18) TTBR + 0x60 reserved : : : : 31 (0x1f) TTBR + 0x7c reserved *1 *1 *2 NMI 4 8, 11 20, 22 S1C Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
45 6 ITC ITC S1C ITC 1 ITC 1 reti ITC ITC S1C ITC S1C17 IL PSR S1C ITC 0 0 S1C17 ITC P0 ILV0[2:0] D[2:0]/ITC_LV0 0x4306 P1 ILV1[2:0] D[10:8]/ITC_LV0 0x4306 ILV2[2:0] D[2:0]/ITC_LV1 0x4308 ILV3[2:0] D[10:8]/ITC_LV1 0x OSC1 ILV4[2:0] D[2:0]/ITC_LV2 0x430a reserved ILV5[2:0] D[10:8]/ITC_LV2 0x430a reserved ILV6[2:0] D[2:0]/ITC_LV3 0x430c PWM Ch.0 ILV7[2:0] D[10:8]/ITC_LV3 0x430c 8 Ch.0/Ch.1 ILV8[2:0] D[2:0]/ITC_LV4 0x430e 16 Ch.0 ILV9[2:0] D[10:8]/ITC_LV4 0x430e 16 Ch.1 ILV10[2:0] D[2:0]/ITC_LV5 0x Ch.2 ILV11[2:0] D[10:8]/ITC_LV5 0x4310 UART Ch.0 ILV12[2:0] D[2:0]/ITC_LV6 0x4312 UART Ch.1/I 2 C ILV13[2:0] D[10:8]/ITC_LV6 0x4312 SPI ILV14[2:0] D[2:0]/ITC_LV7 0x4314 I 2 C ILV15[2:0] D[10:8]/ITC_LV7 0x4314 ILV16[2:0] D[2:0]/ITC_LV8 0x4316 reserved ILV17[2:0] D[10:8]/ITC_LV8 0x4316 A/D ILV18[2:0] D[2:0]/ITC_LV9 0x4318 reserved ILV19[2:0] D[10:8]/ITC_LV9 0x4318 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-3
46 6 ITC ITC ITC S1C S1C17 ITC S1C17 S1C17 ITC S1C17 S1C17 PSR S1C17 IE 1 PSR IL NMI 1 S1C17 S1C17 S1C17 1 PSR PC 2 PSR IE 0 3 PSR IL NMI 4 PC 2 IE 1 3 IL reti PSR 6-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
47 6 ITC 6.4 NMI S1C17003 NMI NMI S1C17 NMI 17 WDT S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-5
48 6 ITC 6.5 S1C17 int imm5 intl imm5,imm3 imm intl imm3 PSR IL Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
49 6 ITC 6.6 HALT, SLEEP HALT SLEEP CPU ITC CPU NMI ITC CPU HALT SLEP CPU halt slp ITC HALT SLEP Appendix B B.1 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-7
50 6 ITC ITC 0x4306 ITC_LV0 Interrupt Level Setup Register 0 P0 P1 0x4308 ITC_LV1 Interrupt Level Setup Register 1 SWT CT 0x430a ITC_LV2 Interrupt Level Setup Register 2 T8OSC1 0x430c ITC_LV3 Interrupt Level Setup Register 3 T16E Ch.0 0x430e ITC_LV4 Interrupt Level Setup Register 4 T8F Ch.0/Ch.1 T16 Ch.0 0x4310 ITC_LV5 Interrupt Level Setup Register 5 T16 Ch.1 Ch.2 0x4312 ITC_LV6 Interrupt Level Setup Register 6 UART CH.0 Ch.1/I 2 C 0x4314 ITC_LV7 Interrupt Level Setup Register 7 SPI I 2 C 0x4316 ITC_LV8 Interrupt Level Setup Register 8 REMC 0x4318 ITC_LV9 Interrupt Level Setup Register 9 A/D ITC 16 : Reserved Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
51 6 ITC 0x4306: Interrupt Level Setup Register 0 (ITC_LV0) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4306 Setup Register 0 (16 bits) (ITC_LV0) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV1[2:0] P1 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV0[2:0] P0 interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV1[2:0]: P1 Port Interrupt Level Bits P1 0 7 : 0 S1C17 PSR IL ITC ITC ITC_LVx 0x4306 0x4318 S1C17 S1C17 ITC S1C17 S1C17 ITC Reserved ILV0[2:0]: P0 Port Interrupt Level Bits P0 0 7 : 0 ILV1[2:0] D[10:8] S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-9
52 6 ITC 0x4308: Interrupt Level Setup Register 1 (ITC_LV1) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4308 Setup Register 1 (16 bits) (ITC_LV1) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV3[2:0] CT interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV2[2:0] SWT interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV3[2:0]: Clock Timer Interrupt Level Bits 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV2[2:0]: Stopwatch Timer Interrupt Level Bits 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
53 6 ITC 0x430a: Interrupt Level Setup Register 2 (ITC_LV2) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x430a Setup Register 2 (16 bits) (ITC_LV2) D15 3 reserved 0 when being read. D2 0 ILV4[2:0] T8OSC1 interrupt level 0 to 7 0x0 R/W D[15:3] D[2:0] Reserved ILV4[2:0]: 8-bit OSC1 Timer Interrupt Level Bits 8 OSC1 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-11
54 6 ITC 0x430c: Interrupt Level Setup Register 3 (ITC_LV3) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x430c Setup Register 3 (16 bits) (ITC_LV3) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV7[2:0] T16E Ch.0 interrupt level 0 to 7 0x0 R/W D7 0 reserved 0 when being read. D[10:8] D[7:0] ILV7[2:0]: PWM & Capture Timer Ch.0 Interrupt Level Bits PWM Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved 6-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
55 6 ITC 0x430e: Interrupt Level Setup Register 4 (ITC_LV4) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x430e Setup Register 4 (16 bits) (ITC_LV4) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV9[2:0] T16 Ch.0 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV8[2:0] T8F Ch.0/Ch.1 interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV9[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits 16 Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV8[2:0]: 8-bit Timer Ch.0/Ch.1 Interrupt Level Bits : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-13
56 6 ITC 0x4310: Interrupt Level Setup Register 5 (ITC_LV5) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4310 Setup Register 5 (16 bits) (ITC_LV5) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV11[2:0] T16 Ch.2 interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV10[2:0] T16 Ch.1 interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV11[2:0]: 16-bit Timer Ch.2 Interrupt Level Bits 16 Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV10[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits 16 Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
57 6 ITC 0x4312: Interrupt Level Setup Register 6 (ITC_LV6) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4312 D15 11 reserved 0 when being read. Setup Register 6 (16 bits) (ITC_LV6) D10 8 ILV13[2:0] UART Ch.1/I 2 C (slave) interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV12[2:0] UART Ch.0 interrupt level 0 to 7 0x0 R/W D[15:11] Reserved D[10:8] D[7:3] D[2:0] ILV13[2:0]: UART Ch.1/I 2 C (slave) Interrupt Level Bits UART Ch.1 I2C slave 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV12[2:0]: UART Ch.0 Interrupt Level Bits UART Ch : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-15
58 6 ITC 0x4314: Interrupt Level Setup Register 7 (ITC_LV7) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4314 Setup Register 7 (16 bits) (ITC_LV7) D[15:11] Reserved D15 11 reserved 0 when being read. D10 8 ILV15[2:0] I 2 C (master) interrupt level 0 to 7 0x0 R/W D7 3 reserved 0 when being read. D2 0 ILV14[2:0] SPI interrupt level 0 to 7 0x0 R/W D[10:8] D[7:3] D[2:0] ILV15[2:0]: I 2 C (master) Interrupt Level Bits I 2 C 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] Reserved ILV14[2:0]: SPI Interrupt Level Bits SPI 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
59 6 ITC 0x4316: Interrupt Level Setup Register 8 (ITC_LV8) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4316 Setup Register 8 (16 bits) (ITC_LV8) D15 3 reserved 0 when being read. D2 0 ILV16[2:0] REMC interrupt level 0 to 7 0x0 R/W D[15:3] D[2:0] Reserved ILV16[2:0]: REMC Interrupt Level Bits 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-17
60 6 ITC 0x4318: Interrupt Level Setup Register 9 (ITC_LV9) Register name Address Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4318 Setup Register 9 (16 bits) (ITC_LV9) D15 3 reserved 0 when being read. D2 0 ILV18[2:0] A/D converter interrupt level 0 to 7 0x0 R/W D[15:3] D[2:0] Reserved ILV18[2:0]: A/D Convertere Interrupt Level Bits A/D 0 7 : 0 ITC_LV0 0x4306 ILV1[2:0] D[10:8] 6-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
61 6 ITC 6.8 PSR reti S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-19
62 7 OSC 7 OSC 7.1 OSC S1C OSC3 OSC1 OSC3 S1C17 OSC1 OSC3 On/Off OSC3 OSC1 HSCLK( ) OSC OSC OSC CLG OSC3 OSC4 OSC3 wakeup HSCLK OSC1 (1/1~1/8) HALT CCLK BCLK S1C17, RAM, ROM FOUTH OSC1 OSC2 FOUT1 RESET NMI SLEEP, On/Off FOUTH On/Off SLEEP, On/Off OSC1 FOUT1 On/Off On/Off (1/1~1/4) S1C17 S1C17 OSC1 On/Off On/Off (1/128) (1/1~1/32) HALT (1/1~1/16K) PSC PCLK T16, T8F, UART, SPI, I2C( ), T16E, P, MISC, REMC, ADC, I2C( ) T8F, T16, T16E, REMC, P, UART, SPI, I2C( ), ADC CLK_256Hz CT, SWT, WDT T8OSC1 On/Off On/Off OSC Appendix B S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-1
63 7 OSC 7.2 OSC3 OSC3 S1C OSC3 CG3 Rf OSC3 X'tal3 or Ceramic fosc3 CD3 VSS OSC OSC3 SLEEP OSC3 OSC4 X'tal3 Ceramic Rf OSC3 OSC4 VSS 2 CG3 CD3 OSC3 On/Off OSC3 OSC3EN D0/OSC_CTL 0 1 OSC3 SLEEP * OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061) OSC3EN 1 OSC3 OSC3 On/Off 7.4 OSC3 OSC3 SLEEP OSC3 On OSC3 OSC3 OSC3 OSC3WT[1:0] D[5:4]/OSC_CTL 4 * OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061) OSC3 OSC3WT[1:0] 0x x x x : 0x OSC3 : OSC3 OSC3 max. OSC3 OSC3 OSC3 VSS Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
64 7 OSC 7.3 OSC1 OSC kHz OSC1 8 OSC1 OSC OSC1 OSC1 SLEEP fosc1 CG1 X'tal1 OSC2 VSS OSC1 VSS OSC1 OSC2 X'tal1 Typ kHz OSC1 VSS CG1 0 25pF OSC1 On/Off OSC1 OSC1EN D1/OSC_CTL 0 1 OSC1 SLEEP * OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061) OSC1EN 0 OSC1 OSC1 SLEEP OSC1 On OSC1 OSC1 OSC1 256 OSC OSC1 max. OSC1 OSC1 OSC1 OSC2 : OSC1 OSC2 OSC1EN D1/OSC_CTL 0 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-3
65 7 OSC 7.4 S1C17003 OSC1-HSCLK CLKSRC OSC3 =HSCLK OSC OSC1 HSCLK S1C17003 OSC1 OSC1 HSCLK HSCLK OSC1 OSC1 On 7.4 CLKSRC D0/OSC_SRC 1 HSCLK HSCLK SRCSRC 0 * CLKSRC: System Clock Source Select Bit in the Clock Source Select (OSC_SRC) Register (D0/0x5060) : OSC1_HSCLK OSC1 HSCLK CLKSRC CLKSRC Off CLKSRC CLKSRC 1 OSC1 HSCLK HSCLK OSC1 HSCLK 1 OSC Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
66 7 OSC OSC1 OSC 8 OSC1 8 OSC1 OSC OSC1 T8OSC1 OSC1 (1/1~1/32) 8 OSC1 On/Off OSC1 T8O1CK[2:0] D[3:1]/OSC_T8OSC1 OSC1 * T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D[3:1]/0x5065) T8OSC1 T8O1CK[2:0] 0x7 0x6 Reserved 0x5 OSC1 1/32 0x4 OSC1 1/16 0x3 OSC1 1/8 0x2 OSC1 1/4 0x1 OSC1 1/2 0x0 OSC1 1/1 : 0x0 8 OSC1 T8O1CE D0/OSC_T8OSC1 T8O1CE 0 T8O1CE 1 8 OSC1 8 OSC1 * T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) : T8O1CK[2:0] D[3:1]/0x5065 T8O1CE D0/0x OSC1 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-5
67 7 OSC 7.6 FOUTH, FOUT1 HSCLK FOUTH OSC1 FOUT1 P40 HSCLK (1/1~1/4) FOUTH FOUTH(P40) On/Off P35 P40 OSC1 FOUT1 FOUT1(P35) On/Off P35 FOUTH FOUTH HSCLK FOUTH P40 P40 FOUTH P40MUX D0/P4_PMUX 1 * P40MUX: P40 Port Function Select Bit in the P4 Port Function Select (P4_PMUX) Register (D0/0x52a8) FOUTH 3 FOUTHD[1:0] D[3:2]/OSC_FOUT HSCLK * FOUTHD[1:0]: FOUTH Clock Division Ratio Select Bits in the FOUT Control (OSC_FOUT) Register (D[3:2]/0x5064) FOUTH FOUTHD[1:0] 0x3 Reserved 0x2 HSCLK 1/4 0x1 HSCLK 1/2 0x0 HSCLK 1/1 : 0x0 FOUTHE D1/OSC_FOUT FOUTHE 1 FOUTH FOUTH FOUTHE 0 * FOUTHE: FOUTH Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064) FOUTHE FOUTH (P30) FOUTH : FOUTH FOUTHE On/Off FOUTH 1 FOUTHD[1:0] D[3:2]/0x5064 FOUTHE D1/ 0x Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
68 7 OSC FOUT1 FOUT1 OSC1 FOUT1 P35 P35 FOUT1 P35MUX D3/P1_PMUX 1 * P35MUX: P35 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D3-2/0x52a7) FOUT1E D0/OSC_FOUT FOUT1E 1 FOUT1 FOUT1 FOUT1E 0 * FOUT1E: FOUT1 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D0/0x5064) FOUT1E FOUT1 (P13) FOUT1 : FOUT1 FOUT1E On/Off S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-7
69 7 OSC 7.7 RESET, NMI S1C17 RESET NMI NMI OSC S1C17 RESET : RSTFE D1/OSC_NFEN = 1 RSTFE = 0 NMI : NMIFE D0/OSC_NFEN = 1 NMIFE = 0 * RSTFE: Reset Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D1/0x5062) * NMIFE: NMI Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D0/0x5062) : RESET S1C17003 NMI NMI 7-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
70 7 OSC OSC 0x5060 OSC_SRC Clock Source Select Register 0x5061 OSC_CTL Oscillation Control Register 0x5062 OSC_NFEN Noise Filter Enable Register ON/OFF 0x5063 reserved reserved reserved 0x5064 OSC_FOUT FOUT Control Register 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register 8 OSC1 0x5066 reserved reserved reserved 0x5067 reserved reserved reserved OSC 8 : Reserved 0 1 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-9
71 7 OSC 0x5060: Clock Source Select Register (OSC_SRC) Register name Address Bit Name Function Setting Init. R/W Remarks Clock Source Select Register (OSC_SRC) 0x5060 (8 bits) D7 2 reserved 0 when being read. D1 HSCLKSEL High-speed clock select 1 OSC3 1 R 1 when being read. D0 CLKSRC System clock source select 1 OSC1 0 HSCLK 0 R/W D[7:2] D1 D0 Reserved HSCLKSEL: High-speed Clock Select Bit HSCLK 1 R : OSC3 CLKSRC: System Clock Source Select Bit 1 R/W : OSC1 0 R/W : HSCLK HSCLK OSC3 HSCLK OSC1 HSCLK OSC3 : OSC1 HSCLK OSC1 OSC1 OSC1 256 CLKSRC D0/0x5060 CLKSRC Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
72 7 OSC 0x5061: Oscillation Control Register (OSC_CTL) Register name Address Bit Name Function Setting Init. R/W Remarks Oscillation Control Register (OSC_CTL) 0x5061 (8 bits) D7 6 reserved 0 when being read. D5 4 OSC3WT[1:0] OSC3 wait cycle select OSC3WT[1:0] Wait cycle 0x0 R/W 0x3 0x2 0x1 0x0 128 cycles 256 cycles 512 cycles 1024 cycles D3-2 reserved 0 when being read. D1 OSC1EN OSC1 enable 1 Enable 0 Disable 0 R/W D0 OSC3EN OSC3 enable 1 Enable 0 Disable 1 R/W D[5:4] OSC3WT[1:0]: OSC3 Wait Cycle Select Bits OSC3 SLEEP OSC3 On OSC3 OSC OSC3 OSC3WT[1:0] 0x x x x : 0x OSC3 : OSC3 26 D[3:2] D1 D0 Reserved OSC1EN: OSC1 Enable Bit OSC1 / 1 R/W : On 0 R/W : Off : OSC1 OSC1 OSC1EN 0 1 OSC1 OSC1 256 OSC3EN: OSC3 Enable Bit OSC3 / 1 R/W : On 0 R/W : Off : OSC3 OSC3 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-11
73 7 OSC 0x5062: Noise Filter Enable Register (OSC_NFEN) Register name Address Bit Name Function Setting Init. R/W Remarks Noise Filter Enable Register (OSC_NFEN) 0x5062 (8 bits) D7 2 reserved 0 when being read. D1 RSTFE Reset noise filter enable 1 Enable 0 Disable 1 R/W D0 NMIFE NMI noise filter enable 1 Enable 0 Disable 0 R/W D[7:2] D1 Reserved RSTFE: Reset Noise Filter Enable Bit RESET / 1 R/W : 0 R/W : HSCLK OSC1 16 RESET S1C17 D0 NMIFE: NMI Noise Filter Enable Bit NMI / 1 R/W : 0 R/W : HSCLK OSC1 16 NMI S1C17 16 : S1C17003 NMI NMI 7-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
74 7 OSC 0x5064: FOUT Control Register (OSC_FOUT) Register name Address Bit Name Function Setting Init. R/W Remarks FOUT Control 0x5064 D7 4 reserved 0 when being read. Register (OSC_FOUT) (8 bits) D3 2 FOUTHD [1:0] FOUTH clock division ratio select FOUTHD[1:0] Division ratio 0x0 R/W 0x3 0x2 0x1 0x0 reserved HSCLK 1/4 HSCLK 1/2 HSCLK 1/1 D1 FOUTHE FOUTH output enable 1 Enable 0 Disable 0 R/W D0 FOUT1E FOUT1 output enable 1 Enable 0 Disable 0 R/W D[7:4] D[3:2] Reserved FOUTHD[1:0]: FOUTH Clock Division Ratio Select Bits HSCLK FOUTH FOUTH FOUTHD[1:0] 0x3 Reserved 0x2 HSCLK 1/4 0x1 HSCLK 1/2 0x0 HSCLK 1/1 : 0x0 D1 D0 FOUTHE: FOUTH Output Enable Bit FOUTH HSCLK / 1 R/W : On 0 R/W : Off FOUTHE 1 FOUTH FOUTH FOUTHE 0 FOUT1E: FOUT1 Output Enable Bit FOUT1 OSC1 / 1 R/W : On 0 R/W : Off FOUT1E 1 FOUT1 FOUT1 FOUT1E 0 : FOUTH 1 FOUTHD[1:0] D[3:2]/0x5064 FOUTHE D1/ 0x S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-13
75 7 OSC 0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) Register name Address Bit Name Function Setting Init. R/W Remarks T8OSC1 Clock Control Register (OSC_T8OSC1) 0x5065 (8 bits) D7 4 reserved 0 when being read. D3 1 T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio 0x0 R/W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved OSC1 1/32 OSC1 1/16 OSC1 1/8 OSC1 1/4 OSC1 1/2 OSC1 1/1 D0 T8O1CE T8OSC1 clock output enable 1 Enable 0 Disable 0 R/W D[7:4] D[3:1] Reserved T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits OSC1 8 OSC T8OSC1 T8O1CK[2:0] 0x7 0x6 Reserved 0x5 OSC1 1/32 0x4 OSC1 1/16 0x3 OSC1 1/8 0x2 OSC1 1/4 0x1 OSC1 1/2 0x0 OSC1 1/1 : 0x0 D0 T8O1CE: T8OSC1 Clock Output Enable Bit 8 OSC1 / 1 R/W : On 0 R/W : Off T8O1CE 0 T8O1CE 1 8 OSC1 8 OSC1 : T8O1CK[2:0] D[3:1]/0x5065 T8O1CE D0/0x OSC Seiko Epson Corporation S1C17003 TECHNICAL MANUAL
76 7 OSC 7.9 OSC3 26 OSC1 HSCLK OSC1 OSC1 OSC1 256 OSC3 OSC3 OSC1 OSC1 FOUTH/FOUT1 FOUTHE/FOUT1E On/Off CLKSRC D0/0x5060 CLKSRC 1 T8O1CK[2:0] D[3:1]/0x5065 T8O1CE D0/0x OSC1 FOUTH 1 FOUTHD[1:0] D[3:2]/0x5064 FOUTHE D1/0x OSC3 OSC3 (max.)+osc3 OSC3 OSC4 OSC3EN D0/OSC_CTL 0 OSC1 OSC2 OSC1EN(D1/OSC_CTL ) 0 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-15
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4 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Xeon Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0B60: DIMM group #1 has been disabled. : Press to resume, to
PIN S 5 K 0 K 1 K 2 K 3 K 4 V DD V 0 V 1 V 2 V SS OSC SEG 32 SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 1
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1.0 1. Display Format 8*2 Character 2. Power Supply 3.3V 3. Overall Module Size 30.0mm(W) x 19.5mm(H) x max 5.5mm(D) 4. Viewing Aera(W*H) 27.0mm(W) x 10.5mm(H) 5. Dot Size (W*H) 0.45mm(W) x 0.50mm(H) 6.
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20 II 7. 1 409, 3255 e-mail: namba@faculty.chiba-u.jp 2 1 1 1 4 2 203 2 1 1 1 5 503 1 3 1 2 2 Web http://www.icsd2.tj.chiba-u.jp/~namba/lecture/ 1 2 1 5 501 1,, \,", 2000 7. : 1 1 CPU CPU 1 Intel Pentium
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EPX-64S Rev 1.2 1.. 3 1.1.......... 3 1.2....... 3 1.3....... 4 1.4... 4 1.5... 4 2........ 5 2.1.... 5 EPX64S_GetNumberOfDevices........ 5 EPX64S_GetSerialNumber........ 6 EPX64S_Open....... 7 EPX64S_OpenBySerialNumber
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7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
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13 Verilog HDL 16 CPU CPU IP 16 1023 2 reg[ msb: lsb] [ ]; reg [15:0] MEM [0:1023]; //16 1024 16 1 16 2 FF 1 address 8 64 `resetall `timescale 1ns/10ps module mem8(address, readdata,writedata, write, read);
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Version2.0(2009.2.6) Copyright 2008 by WAGO Kontakttechnik GmbH All rights reserved. WAGO Kontakttechnik GmbH Hansastraße 27 D-32423 Minden Phone: +49 (0) 571/8 87 0 Fax: +49 (0) 571/8 87 1 69 E-Mail:
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7 7 Phoenix BIOS 4.0 Release 6.0.XXXX : CPU=Pentium III Processor XXX MHz 0640K System RAM Passed 0127M Extended RAM Passed WARNING 0212: Keybord Controller Failed. : Press to resume, to setup
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1 CMOS 0.35um CMOS, 3V CMOS 2 RF CMOS RF CMOS RF CMOS RFCMOS (ADC Fabless 3 RF CMOS 1990 Abidi (UCLA): Fabless RF CMOS CMOS 90% 4 5 f T [GHz] 450 400 350 300 250 200 150 Technology loadmap L[nm] f T [GHz]
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COPAL ELECTRONICS 32 (DP) DP INC 2 3 3 RH RL RWB 32 C S U/D INC U/D CS 2 2 DP7114 32 SOIC CMOS 2.5 V - 6.0 V / 10 kω 50 kω 100 kω TSSOP MSOP /BFR INC / U/D RH RoHS GND RWB RL CS VCC 2017 6 15 1 : R = 2
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Lab GPIO_35 GPIO
6,GPIO, PSoC 3/5 GPIO HW Polling and Interrupt PSoC Experiment Lab PSoC 3/5 GPIO Experiment Course Material 6 V2.02 October 15th. 2012 GPIO_35.PPT (65 Slides) Renji Mikami Renji_Mikami@nifty.com Lab GPIO_35
変更履歴 Revision 日付 内容 /10/10 初版 /10/24 車載関連説明文削除 /10/06 会社所在地を本社に修正 2
DATA SHEET TE7740RPF Processor Peripheral I/O Expander 1 変更履歴 Revision 日付 内容 1.00 2014/10/10 初版 1.01 2014/10/24 車載関連説明文削除 1.02 2015/10/06 会社所在地を本社に修正 2 目次 1. 概要... 7 2. 特徴... 7 3. ブロック図... 9 4. 端子配列...