AND9062JP - NCP1611を使用したコンパクトかつ高効率のPFCステージを設計するための5つの主要ステップ

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1 APPLICATION NOTE NCP6PFC 60 W 60 W RMS90 V~65 V 390 V 450 ma SO 8NCP6 PFC (CCFF) CrM(CrM) 0 khz CCFF () 0.75 V V CC B (NCP6B) V CC A (NCP6A).5 V-V V CC (9.5 V~35 V) /( OVP)PFC NCP6PFC ()ac 50% PFC / NCP6(GND ) AND906NCP6 PFC[]. FCCrM. ( V SENSE )() Semiconductor Components Industries, LLC, 03 January, 03 Rev. Publication Order Number: AND906JP/D

2 AND906/D PFC STAGE DIMENSIONING V in IL L V bulk AC Line R X Feedback V bulk R fb D zcd D EMI Filter R X C in R bo R z V CC R zcd R ocp Q LOAD R bo R fb C z C p R FF R sence C bulk Figure. Generic Schematic f line :50 Hz/60 Hz 47~63 Hz (V line,rms ) LL : PFCRMS 00 V 0~% (V line,rms ) LL =90V (V line,rms ) HL : RMS( 40 V)0% (V line,rms ) HL = 64 V (V line,rms ) boh : RMS (V line,rms ) boh NCP60% RMS (90% (V line,rms ) boh )(V line,rms ) bol (V line,rms ) boh 90% (V line,rms ) LL 8 V (V line,rms ) bol 90% (V line,rms ) boh 73 V V out,nom :PFC () V out,nom ( (V line,rms ) HL ) 390 V (V out ) pk pk : (DRE) 8% t HOLD UP PFC (V out,min ) (V out,min = 350 V) P out :PFC P out,max 60 W (P in,avg ) max : 95% (P in,avg ) max W 95% I line,max P FF(%) : I line,max (CCFF)00% PFC P FF(%) PFC CrM() 0~0% NCP6(CrM) CrM PFC

3 AND906/D. PFC L PFC (P in,avg ) HL V line,rms T on,max (eq. ) L PFC L L (V line,rms ) LL (P in,avg ) max T on,max (eq. ) CrM RMS (I L,pk ) max (P in,avg ) max (eq. 3) (V line,rms ) LL (I L,rms ) max (I L,pk ) max (eq. 4) 6 L H (I L,pk ) max A (eq. 5) 90 (I L,rms ) max A (T on,max = 0s)T on,max (5 s) (T on,max = 0 s)l 55% 00-H/6-A pk (WURTH ELEKTRONIK ref: ) 0 CrM f sw V line (t) Vout V line (t) 4 P in,avg V out L (eq. 6) () f sw ( 90) (390 90) 80 khz (eq. 7) MOSFET 4% (95%) % 6.4 W COLUMBIA STAVER( TP07ST/0/.5/NA/SP/03) 6C/W P bridge V f P out.8 V f P out V line,rms V line,rms (eq. 8) V f MOSFET (P on ) max (eq. 9) 4 3 R DS(on) P out,max (V line,rms ) LL 8 (V line,rms ) LL 3 V out,nom P BRIDGE = 3.4 WV f V (P on ) max = 3.4 R DS(on) R DS(on) MOSFET MOSFETR DS(on).7 W 5. W MOSFET MOSFETFigure Q NPN (TO9)MOSFET 3

4 AND906/D DRV R D N448 Q R R0 0 k M I C,rms A (eq. 5) Figure. Q Speeds Up the MOSFET Turn Off (I out V f ) I out V f 0.4 A 0.4 W (V f = V ) P DIODE = 0.4 W 3. 3/ (V out ) pk pk P out,max C bulk V out,nom (eq. 0) (= f line ) (8% )4% (47 Hz) C bulk F (eq. ) 8% C bulk P out,max t HOLDUP V out,nom V out,min (eq. ) 0 ms 60 0 m C bulk 08 F (eq. 3) RMS RMS (3) (I c,rms ) max (eq. 4) 3 (P in,avg ) max 9 (V line,rms ) LL V out,nom P out,max V out,nom 3 Figure 8 34 (Figure 7R 8 R 9 R 0 ) 8 nf C fb 50 Rfb R fb fline.5 V (Figure R fb Figure 7R ) I FB V REF R fb.5 R fb (eq. 6) 56 k(i FB 50 A) PCB 50 na( 40C~5C 500 na) I FB 50 A50 na 3. It remains wise to verify the bulk capacitor heating on the bench! 4

5 AND906/D R fb R fb V out,nom V REF (eq. 7) R f b 7 k (I FB 9 A)R fb,800 k560 k (R fb = 4.6 M) 388 V PFC V SENSE NCP6. V PWM(V SENSE 5 ms.7 V Figure 3 Figure 5)3 Loop Gain ( ) 3*G 0 G 0 V line,rms (V in,rms ) BOH.7*(V in,rms ) BOH.*(V in,rms ) BOH 3*(V in,rms ) BOH e.g.: 78 V e.g.: 33 V e.g.: 7 V e.g.: 34 V Figure 3. -step Feed-forward Limits the Loop Gain Variation with Respect to Line [][]PFC ( ) (eq. 8) V^ out V in,rms R load V^ L V control out,nom s R load C bulk (eq. 9) V^ V out in,rms R load V^ L V control out,nom s R load C bulk C bulk R load LPFC V out,nom PFC PFC PF0 Hz NCP6 5

6 AND906/D V CONTROL I CONTROL V OUT R C C R fb R fb FB OTA V REF To PWM Comparator Figure 4. Regulation Trans-conductance Error Amplifier, Feed-back and Compensation Network V^ control V^ out sr C C sr o (C C ) sr C C C (eq. 0) R o V out,nom V ref G EA, G EA 00-S V out,nom V REF OTA.5V [][3] G 0 (V line,rms ) LL R load,min L V out,nom (eq. ) G 0 tan m C f c R load,min C bulk R 0 C G 0 f c R 0 C R R load,min C bulk C (V in,rms ) LL (90 V)RMS G 0 ((V line,rms ) LL ) m () f c R load,min R load,min V out,nom P out,max 60 PFC f p.4 R load,min C bulk Hz 45~70 5 Hz 60(/3) G 0 C tan nf lets choose 0 nf C R C.9 F lets choose. F k (eq. ) 6

7 AND906/D 4 NCP6 X ()Figure Figure 5 R X R X R X V pin R bo (R bo R bo ) R X V R bo R bo R X (R bo R bo ) R line (t) X V pin (eq. 3) R bo R X R bo R bo V line (t) (eq. 4) V SENSE 50 ms(v bol = 0.9 V) staticovp V SENSE (V boh =.0 V) (V line,rms ) boh RMS (V line,rms ) bol (V line,rms ) boh R X R bo R bo V boh (eq. 5) Rbo (V line,rms ) bol R X R bo R bo V bol (eq. 6) Rbo V boh.0 V V bol 0.9 V AC Line EMI Filter PFC Boost Converter R X R X BONOK R bo V SENCE Pin 50-ms Blanking Time R bo.0 V If BONOK High 0.9 V If BONOK Low LLine 5-ms Blanking Time. V If LLine High.7 V If LLine Low I ramp *I ramp FFcontrol Pin Current Information Generation DRV Figure 5. Brown-Out and Line Range Detection Block 7

8 AND906/D R X R X (R X R X = R X )X EMIs M(R X = R X = R X = M) X.8 s (X R bo R bo ) R X R X R bo R bo (R bo = 0 k R X R X R bo (V line,rms ) boh 5R bo R bo R bo (V line,rms ) boh VboH R X (eq. 7) (V line,rms ) boh 8 V (R X =R x =R X =M)(R bo = 0 k) 0 k 8 R bo 000 k 0 k 653 k (eq. 8).0 V 3,800 k560 k 5,960 k R bo ((V line,rms ) boh 77.5 V)((V line,rms ) bol 69.8 V) Cbo 50 T line f line 50 Hz50 s R bo R bo C bo C bo 00 f line.4 nf 00 R bo f line 00 0 k 60 5 R CS R FF =>R CS 0.5 V R CS 0.5 (I L,pk ) max (eq. 9) 3 R CS (V line,rms ) LL 4 (eq. 30) (P in,avg ) max R CS (eq. 3) 80 m R CS MOSFET R CS R DS(on) (P RCS ) max 4 3 R CS (eq. 3) (P in,avg ) max (V line,rms ) LL 8 (V line,rms ) LL 3 V out,nom 80 m 75 mw R SENSE (Figure R OCP )CS/ZCD 3.9 k 5 k CS/ZCD Figure R ZCD CS/ZCD5 ma n aux n p V out,nom n aux n p 8

9 AND906/D R ZCD n aux n V out,nom p V CL(pos) 5mA V CL(pos) R OCP (eq. 33) V CL(pos) CS/ZCD 9V CS/ZCD V ZCD R OCP R ZCD R OCP n aux n P (V out,nom V line ) (eq. 34) NCP6750 mv R OCP n aux R ZCD R OCP n P 0 (R OCP = R ZCD )(n aux /n p )0. n aux n V out,nom P VCL(pos) R ZCD R OCP. 5mA (R OCP = R ZCD > 4. k) (R OCP =R ZCD = 4.7 k)(r OCP > 3.9 k)( ) NCP6CS/ZCD ZCD ZCD pf =>R FF R FF FFcontrol I FF V pin V control V control,min (eq. 35) V control,max V control,min (V line = (V line,rms ) BOH )(V pin = V) V V pin V line. (Vline,rms ) BOH V control V control,min t on V control,max V control,min t on,max t on,max 5 s I line V line t on L, 35 I FF 56 L I line 5 (eq. 36) (V line,rms ) BOH FFcontrol V FF 56 R FF L I line 5 (eq. 37) (V line,rms ) BOH V FF.5 V PFC () (I line ) th 5 (V line,rms ) BOH R FF L (eq. 38) 450 ma RFF R FF 5 (V line,rms ) BOH L (eq. 39) k I line,max (P in,avg ) max.67 A (eq. 40) (V in,rms ) LL 7%70 k FFcontrol 0.75 V()0 khz (7% 0.75/.5) 5% 3 CFF 50 T line f line 50 Hz50 s 9

10 AND906/D 3R FF R FF C FF C FF 50 f line (eq. 4) 4 pf 50 R FF f line k 60 NCP6 (R sense ) 00 nf0 nf V CC GND ( ) 3 (V SENSE ) FFcontrol Table. SUMMARY OF THE MAIN EQUATIONS Steps Components Formulae Comments f line : Line frequency. It is often specified in a range of Hz for 50 Hz/60 Hz applications. (V line,rms ) LL : Lowest Level of the line voltage, e.g., 90 V. (V line,rms ) HL : Highest Level for the line voltage (e.g., 64 V in many countries). Step Key Specifications (V line,rms ) boh : Brown-Output Line Upper Threshold. The circuit prevents operation until the line rms voltage exceeds this level. V out,nom : Nominal Output Voltage. (V out ) pk pk : Peak-to-Peak output voltage low-frequency ripple. t HOLD UP : Hold-up Time that is the amount of time the output will remain valid during line drop-out. (V out,min ): Minimum output voltage allowing for operation of the downstream converter. P out,max : Maximum output power consumed by the PFC load, that is, 60 W in our application. (P in,avg ) max : Maximum power absorbed from the mains in normal operation. Generally obtained at full load, low line, it depends on the efficiency that, as a rule of a thumb, can be set to 95%. 0

11 AND906/D Table. SUMMARY OF THE MAIN EQUATIONS (continued) Steps Components Formulae Input Diodes Bridge Losses P bridge V f P out.8 V f P out V line,rms V line,rms Comments V f is the forward voltage of any diode of the bridge. It is generally in the range of V or less. Inductor L (V line,rms ) LL (P in,avg ) max T on,max (I L,pk ) max (P in,avg ) max (V line,rms ) LL In our application: L H 70 (I L,pk ) max A 90 (I L,rms ) max (I L,pk ) max 6 (I L,rms ) max A Step Power Components MOSFET Conduction Losses (P on ) max 4 3 R DS(on) P out,max (V line,rms ) LL 8 (V line,rms ) LL 3 V out,nom R DS(on) is the drain-source on-state resistance of the MOSFET Bulk Capacitor Constraints P out,max C bulk (V out ) pk pk V out,nom C bulk P out,max t HOLDUP V out,nom V out,min (I c,rms ) max 3 (P in,avg ) max 9 (V line,rms ) LL V out,nom P out,max V out,nom These 3 equations quantify the constraints resulting from the low-frequency ripple ((V out ) pk pk that must be kept below 8%), the hold-up time requirement and the rms current to be sustained. Step3 Feedback Arrangement Resistor Divider Compensation R fb R fb V out,nom V REF C fb R fb.5 I FB 50 Rfb R fb fline G 0 (V line,rms ) LL R load,min L V out,nom G 0 tan m C f c R load,min C bulk R 0 I FB is the bias current that is targeted within the resistor divider. Values in the range of 50 A to 00 A generally give a good trade-off between losses and noise immunity. C FB is the filtering capacitor that can be placed between the FB pin and ground to increase the noise immunity of this pin. C G 0 f c R 0 C R R load,min C bulk C Step4 Input Voltage Sensing Input Voltage Sensing Resistors R bo R bo C bo (V line,rms ) boh VboH R X 50 R bo f line R X is the resistance of the X capacitors discharge resistors R X and R X according to Figure 5. (V line,rms ) boh line rms level above which the circuit starts operating. V boh is an internal -V reference.

12 AND906/D Table. SUMMARY OF THE MAIN EQUATIONS (continued) Steps Components Formulae Comments Step5 Current Sense Network Current Sense Resistor Zero Current Detection R CS (P RCS ) max 4 3 R CS (P in,avg ) max (V line,rms ) LL R ZCD (V line,rms ) LL 4 (P in,avg ) max 8 (V line,rms ) LL 3 V out,nom n aux n V out,nom p V CL(pos) V CL(pos) 5mA R OCP (V line,rms ) LL is the line rms voltage lowest level in normal condition (e.g., 90 V). V out,nom is the output nominal level (e.g., 390 V). (P in,avg ) max is the maximum input power of your application. Placed between R CS and the CS/ZCD pin, resistor R OCP must be greater than 3.9 k but not too high for noise immunity. Generally, resistors in the range of 5 k give good results. Current Controlled Frequency Fold-back R FF 5 (V line,rms ) BOH L (I line ) th C FF 50 f line R FF (I line ) th is the line current level below which the NCP6 starts to reduce the frequency.

13 AND906/D Detailed Schematic for our 60-W, Universal Mains Application C4, 0 nf Type = X R, 000 k IN U GBU606 C5 470 nf/400 V D N5406 L, 00 H (np/ns = 0) D MUR550 Rth B5753S50M V in V aux V line R, 000 k C nf Type = Y D3 N448 R5. Q IPA50R50 DRV V bulk CM L F C nf Type = Y C3 680 nf Type = X R6 D4 N448 R4 0 k R3 80 m, 3W C7 F/50 V C6a 68 F/450 V DZ 33 V C6b 68 F/450 V I sense GND V CC L N Earth Vrms Socket for External VCC Power Source Figure 6. Application Schematic Power Section V line R 560 k R3,800 k R4,800 k R5,800 k R6 0 k C6 00 pf R 7 k C8 nf C0 0 nf R k C9. F R8 560 k R9,800 k R0,800 k R4 70 k R6 0 k R7 0 k C 470 pf R3 0 R5 0 k C5 0 nf D6 N448 C NC C3 0 nf ZD V R8 7 R0, 4.7 k D5 N448 C4 NC R9 NC R7 0 R 4.7 k V bulk V in V CC V aux DRV I sense GND Figure 7. Application Schematic Control Section 3

14 AND906/D NCP6PFC Excel Spreadsheet [5] 60 W NCP6 [4](BOMGERBER ) [6] [7] [] Joel Turchi, Safety tests on a NCP6-driven PFC stage, Application note AND9064/D, D.PDF. [] Joel Turchi, Compensation of a PFC stage driven by the NCP654, Application note AND83/D, D.PDF. [3] Joel Turchi, Compensating a PFC stage, Tutorial TND38 D available at: D.PDF. [4] EVBUM49/D, NCP6 Evaluation Board User s Manual, D.PDF [5] NCP6 design worksheet, [6] NCP6 evaluation board documents, [7] NCP6 data sheet, D.PDF. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 807 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative AND906JP/D

LB IC Semiconductor Components Industries, LLC, 2013 August, 2013

LB IC Semiconductor Components Industries, LLC, 2013 August, 2013 http://onsemi.jp IC Semiconductor Components Industries, LLC, 2013 August, 2013 Δ Δ Δ μ μ μ Δ μ Δ μ μ μ μ μ μ μ μ μ Δ Δ μ μ μ μ μ μ μ μ μ μ μ 36 19 0.5 5.6 7.6 1 0.3 18 0.2 15.0 1.5 1.7max (0.7) 0.8 0.1