DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter (jp)

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1 DAC121S101 DAC121S101/DAC121S101Q 12-Bit Micro Power, RRO Digital-to-Analog Converter Literature Number: JAJSA89

2 DAC121S D/A DAC121S D/A (DAC) 2.7V 5.5V 3.6V 177 A 30MHz 3 SPI TM QSPI MICROWIRE DSP 2.7V 3.6V 20MHz DAC121S101 DAC 0V W DAC121S101 DAC121S101 AD5320 DAC DAC121S DAC101S101 DAC DAC121S ( ) 0V SYNC ( 2.7V 5.5V) ds DNL LSB (typ) 8 s (typ) 4mV (typ) 0.06%FS (typ) 0.64mW (3.6V) / 1.43mW (5.5V) typ 0.14 W (3.6V) / 0.39 W (5.5V) typ DAC121S101 DAC121S D/A SPI Motorola, Inc National Semiconductor Corporation DS JP 1

3 DAC121S101 TSOT (SOT-23) MSOP 1 4 V OUT DAC 2 8 GND 3 1 V A GND SYNC Low SCLK 4 7 D IN SCLK 6 5 SYNC Low SCLK 16 SCLK SYNC High SYNC DAC DAC 16 2, 3 NC 2

4 (Note 1 2) (V A ) 6.5V 0.3V (V A 0.3V) (Note 3) 10mA (Note 3) 20 ma (T A 25 ) Note 4 ESD (Note 5) 10 (Note 6) 2500V 250V (Note 1 2) 40 T A 105 (V A ) 2.7V 5.5V (Note 7) 0.1V (V A 0.1V) pF SCLK 30MHz DAC121S101 V A 2.7V 5.5V R L 2k GND C L GND 200pF f SCLK 30MHz T MIN T A T MAX T A 25 3

5 DAC121S101 ( ) V A 2.7V 5.5V R L 2k GND C L GND 200pF f SCLK 30MHz T MIN T A T MAX T A 25 4

6 AC V A 2.7V 5.5V R L 2k GND C L GND 200pF f SCLK 30MHz T MIN T A T MAX T A 25 DAC121S101 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: IC GND 0 (V IN ) ( V IN GND V IN V A ) 10mA (20mA)10mA2 T J max ( : T J max 150 ) JA ( ) T A ( ) P D MAX (T J max T A )/ JA ( ) 100pF 1.5k 220pF 1986 National Semiconductor Linear Data Book "Surface Mount" 1 V A 300mV GND 300mV V A 100mV GND 100mV V A 2.7V DC 100mV 2.8V DC Note 8: Note 9: V A (Typical) T J 25 AOQL Note 10: 5

7 DAC121S101 (DIFFERENTIAL NON-LINEARITY: DNL) 1LSB 1LSB V REF /4096 V A /4096 (DIGITAL FEEDTHROUGH) DAC DAC (FULL-SCALE ERROR) DAC (FFh) V A 4095/4096 (GAIN ERROR) GE ZE FSE GE FSE ZE (GLITCH IMPULSE) DAC nv-s ( ) (INTEGRAL NON-LINEARITY: INL) INL LSB (LEAST SIGNIFICANT BIT) LSB LSB V REF /2 n V REF "n" DAC DAC121S (MAXIMUM LOAD CAPACITANCE) DAC (MONOTONICITY) DAC (MSB) MSB V A 1/2 (POWER EFFICIENCY) (SETTLING TIME) 1/2LSB (WAKE-UP TIME) 1/2LSB (ZERO CODE ERROR) 00h DAC 6

8 DAC121S101 FIGURE 1. Input / Output Transfer Characteristic FIGURE 2. DAC121S101 Timing 7

9 DAC121S101 f SCLK 30MHz T A DNL at V A = 3.0V DNL at V A = 5.0V INL at V A = 3.0V INL at V A = 5.0V TUE at V A = 3.0V TUE at V A = 5.0V 8

10 ( ) f SCLK 30MHz T A DNL vs. V A INL vs. V A DAC121S101 3V DNL vs. f SCLK 5V DNL vs. f SCLK 3V DNL vs. Clock Duty Cycle 5V DNL vs. Clock Duty Cycle 9

11 DAC121S101 ( ) f SCLK 30MHz T A V DNL vs. Temperature 5V DNL vs. Temperature 3V INL vs. f SCLK 5V INL vs. f SCLK 3V INL vs. Clock Duty Cycle 5V INL vs. Clock Duty Cycle 10

12 ( ) f SCLK 30MHz T A V INL vs. Temperature 5V INL vs. Temperature DAC121S101 Zero Code Error vs. f SCLK Zero Code Error vs. Clock Duty Cycle Zero Code Error vs. Temperature Full-Scale Error vs. f SCLK 11

13 DAC121S101 ( ) f SCLK 30MHz T A Full-Scale Error vs. Clock Duty Cycle Full-Scale Error vs. Temperature Supply Current vs. V A Supply Current vs. Temperature 5V Glitch Response Power-On Reset 12

14 ( ) f SCLK 30MHz T A V Wake-Up Time 5V Wake-Up Time DAC121S101 13

15 DAC121S DAC DAC121S101 CMOS V OUT = V A (D / 4096) D DAC Figure DAC DAC ( ) Low SYNC High SYNC SYNC D IN High Low 1.5 Figure ( 3 1 ) SCLK 16 DAC Figure FIGURE 3. DAC Resistor String 0V V A ( 0V V A ) DAC SPI QSPI MICROWIRE DSP SYNC Low SYNC Low D IN SCLK ( DAC ) SYNC Low High FIGURE 4. Input Register Contents SYNC SCLK 16 Low DAC SYNC High DAC 1.6 DAC 0 0V DAC 1.7 DAC121S (DB13 DB12) TABLE 1. Modes of Operation DB13 DB12 0 Table 1 1k 100k DAC SYNC D IN Low 14

16 2.0 DAC121S101 (Power Supply Rejection Ratio: PSRR 2.1 DSP/ DAC121S101 DSP 68HC11 CPOL CPHA 1 MOSI SCLK PC7 LowDAC 68HC MSB PC7 1 8 Low 2 DAC 2 PC7 High DAC121S ADSP-2101/ADSP2103 Figure 5 DAC121S101 ADSP-2101/ADSP2103 DSP SPORT Transmit Alternate Framing Mode SPORT Internal Clock Operation Active Low Framing 16-bit Word Length SPORT Tx FIGURE 7. 68HC11 Interface Microwire Figure 8 Microwire DAC121S101 SCLK FIGURE 5. ADSP-2101/2103 Interface C51/80L51 DAC121S101 80C51/80L51 Figure 6 SYNC P3.3 DAC121S101 Low 80C51/80L DAC 1 8 P3.3 Low 2 2 P3.3 High 80C51/80L51 LSB DAC121S101 MSB80C51/ 80L51 FIGURE 8. Microwire Interface 2.2 DAC121S101 DAC121S101 DAC121S LM % LM4130 DAC121S101 3V 5V 0V 4.095V 4.096V LM4130 VIN 0.1 F VOUT 2.2 F LM SOT23 FIGURE 6. 80C51/80L51 Interface HC11 DAC121S101 68HC11 Figure 7 DAC121S101 SYNC 80C51/80L51 ( PC7) 15

17 DAC121S ( ) LP3985 LP3985 3% DAC121S V 3.3V 5V 30 V LP SOT23 5 micro SMD FIGURE 9. The LM4130 as a power supply LM % LM4050 DAC121S101 3V 4.096V 5V LM SOT23 FIGURE 11. Using the LP3985 regulator 1.0 F LP3985 ESR 5m 500m ESR 1.0 F LP2980 LP % 1.0% 3.0V 3.3V 5V FIGURE 10. The LM4050 as a power supply Figure 10 R LM mA LM4050 DAC121S101 R LM4050 DAC121S101 LM4050 DAC121S101 R(min) ( V IN (max) V Z (min)) / (I A (min) I Z (max)) R(max) ( V IN (min) V Z (max) ) / (I DAC (max) I Z (min) ) V Z (min) V Z (max) LM4050 LM4050 I Z (max) LM4050 I Z (min) LM4050 I A (max) DAC121S101 I A (min) DAC121S101 FIGURE 12. Using the LP2980 regulator LP F 2.2 F ESR LP2980 ESR LP2980 ESR ESR 16

18 2.0 ( ) 2.3 DAC121S101 Figure 13 5V 5V FIGURE 13. Bipolar Operation V O (V A (D / 4096)) ((R1 R2) / R1) (V A R2 / R1) D 10 VA = 5V R1 = R2 V O (10 D / 4096) 5V Table 2 TABLE 2. Some Rail-to-Rail Amplifiers 2.4 DAC121S101 DAC121S101 DAC121S F 0.1 F 0.1 F 10 F 0.1 F ESL ESR DAC121S101 DAC121S101 17

19 DAC121S101 inches (millimeters) 8-Lead MSOP Order Numbers DAC121S101CIMM NS Package Number MUA08A 6-Lead TSOT Order Numbers DAC121S101CIMK NS Package Number MK06A 18

21 IMPORTANT NOTICE

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp)

ADC121S Bit, ksps, Diff Input, Micro Pwr Sampling ADC (jp) ADC121S625 ADC121S625 12-Bit, 50 ksps to 200 ksps, Differential Input, Micro Power Sampling A/D Converter Literature Number: JAJSAB8 ADC121S625 12 50kSPS 200kSPS A/D ADC121S625 50kSPS 200kSPS 12 A/D 500mV