MAX15023 DS_J

Transcription

1 EVALUATION KIT AVAILABLE 9-429; Rev 2; 3/ MAX5023 ± ± ± PART TEMP RANGE PIN-PACKAGE MAX5023ETG+ -40 C to +85 C 24 TQFN-EP* MAX5023ETG/V+ -40 C to +85 C 24 TQFN-EP* * TOP VIEW RT SGND IN LIM2 LIM COMP COMP2 FB FB2 2 EN EN2 VCC PGOOD2 PGOOD TQFN *EXPOSED PAD (CONNECT TO GROUND). DL2 *EP DL PGND LX MAX PGND BST DH2 DH BST LX

2 ABSOLUTE MAXIMUM RATINGS IN to SGND V to +30V BST_ to V CC V to +30V LX_ to SGND...-V to +30V EN_ to SGND V to +6V PGOOD_ to SGND V to +30V BST_ to LX_ V to +6V DH_ to LX_ V to (V BST_ + 0.3V) DL_ to PGND_ V to (V CC + 0.3V) SGND to PGND_ V to +0.3V V CC to SGND V to the lower of +6V or (V IN + 0.3V) All Other Pins to SGND V to (V CC + 0.3V) Note : These power limits are due to the thermal characteristics of the package, absolute maximum junction temperature (50 C), and the JEDEC 5-7 defined setup. Maximum power dissipation could be lower, limited by the thermal shutdown protection included in this IC. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 2) 24 TQFN-EP Junction-to-Ambient Thermal Resistance (θ JA ) C/W Junction-to-Case Thermal Resistance (θ JC )...+8 C/W Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD5-7, using a four-layer board. For detailed information on package thermal considerations, refer to japan.maximintegrated.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS V CC Short Circuit to SGND...Continuous V CC Input Current (IN V CC, internal LDO not used)...600ma PGOOD_ Sink Current...20mA Continuous Power Dissipation (T A +70 C)(Note ) 24-Pin TQFN-EP (derate 27.8mW/ C above +70 C) mW Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C Soldering Temperature (reflow) C (V IN 2V, R T 33kΩ, C VCC 4.7μF, C IN μf, T A -40 C to +85 C, unless otherwise noted. Typical values are at T A +25 C.) (Note 3) GENERAL PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Voltage Range V IN V IN V CC Quiescent Supply Current I IN V FB V FB2 0.9V, no switching ma Standby Supply Current I IN_SBY V EN V EN2 V SGND ma V CC REGULATOR 6V < V IN < 28V, I LOAD 5mA Output Voltage V CC V IN 6V, ma < I LOAD < 00mA V V CC Regulator Dropout I LOAD 00mA 0.07 V V CC Short-Circuit Output Current V IN 5V ma V CC Undervoltage Lockout V CC_UVLO V CC falling V V CC Undervoltage Lockout Hysteresis ERROR AMPLIFIER (FB_, COMP_) V 430 mv FB_ Input Voltage Set-Point V FB_ mv FB_ Input Bias Current I FB_ V FB_ 0.6V na 2 Maxim Integrated

3 ELECTRICAL CHARACTERISTICS (continued) MAX5023 (V IN 2V, R T 33kΩ, C VCC 4.7μF, C IN μf, T A -40 C to +85 C, unless otherwise noted. Typical values are at T A +25 C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS FB_ to COMP_ Transconductance g m I COMP ±40µA µs Amplifier Open-Loop Gain No load 80 db Amplifier Unity-Gain Bandwidth 0 MHz COMP_ Swing (High) 2.4 V COMP_ Swing (Low) No load at COMP_ 0.6 V COMP_ Source/Sink Current I COMP_ I COMP_, V COMP_.5V µa ENABLE (EN_) EN_ Input High V EN_H EN_ rising V EN_ Input Hysteresis V EN_HYS 50 mv EN_ Input Leakage Current I LEAK_EN_ na OSCILLATOR Switching Frequency f SW Each converter khz Switching Frequency Adjustment Range (Note 4) khz PWM Ramp Peak-to-Peak Amplitude V RAMP.42 V PWM Ramp Valley V VALLEY 0.72 V Phase Shift Between Channels From DH to DH2 rising edges 80 Degrees Minimum Controllable On-Time ns Maximum Duty Cycle % OUTPUT DRIVERS DH_ On-Resistance Low, sinking 00mA, V BST_ - V LX_ 5V H i g h, sour ci ng 00m A, V B S T _ - V L X _ 5V.2 Ω DL_ On-Resistance Low, sinking 00mA, V CC 5.2V 0.75 High, sourcing 00mA, V CC 5.2V.4 Ω DH_ Peak Current C LOAD 0nF Sinking 3 Sourcing 2 A DL_ Peak Current C LOAD 0nF Sinking 3 Sourcing 2 A DH_, DL_ Break-Before-Make Time (Dead Time) 5 ns SOFT-START Soft-Start Duration 2048 Switching cycles Reference Voltage Steps 64 Steps Maxim Integrated 3

4 ELECTRICAL CHARACTERISTICS (continued) (V IN 2V, R T 33kΩ, C VCC 4.7μF, C IN μf, T A -40 C to +85 C, unless otherwise noted. Typical values are at T A +25 C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CURRENT LIMIT/HICCUP Cycle-by-Cycle, Low-Side, Source Peak Current-Limit Threshold Adjustment Range Source peak limit V LIM_ / mv LIM_ Reference Current I LIM_ V LIM_ 0.3V to 3V, T A +25 C µa LIM_ Reference Current TC V LIM_ 0.3V 2400 ppm/ C Number of Consecutive Current- Limit Events to Hiccup 7 Events Hiccup Timeout Out of soft-start 7936 Cycle-by-Cycle, Low-Side, Sink Peak Current-Limit Sense Voltage BOOST V L IM _ / 20 Switching cycles Boost Switch Resistance V IN V CC 5.2V, I BST_ 0mA Ω POWER-GOOD OUTPUTS PGOOD_ Threshold V FB_ rising % V FB_ falling V FB( N OM IN A L) PGOOD_ Output Leakage I LEAK_PGD V PGOOD_ 28V, V EN_ 5V, V FB_ 0.8V µa PGOOD_ Output Low Voltage V PGOOD_L I PGOOD_ 2mA, EN_ SGND 0.4 V THERMAL SHUTDOWN Thermal Shutdown Threshold +50 C Thermal Shutdown Hysteresis Temperature falling 20 C Note 3: All Electrical Characteristics limits over temperature are 00% tested at room temperature and guaranteed by design over the specified temperature range Note 4: Select R T as RT ( kω ) ( fsw ( khz)) ( has a farad unit). V 4 Maxim Integrated

5 (Supply IN 2V, unless otherwise noted. See Typical Application Circuit of Figure 6.) EFFICIENCY (%) EFFICIENCY vs. LOAD CURRENT V OUT 3.3V V 70 OUT.2V V IN 2V LOAD CURRENT (A) MAX5023 toc0 EFFICIENCY (%) EFFICIENCY vs. LOAD CURRENT V OUT 3.3V V OUT.2V V IN V CC 5V LOAD CURRENT (A) MAX5023 toc02 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE CHANGE vs. LOAD CURRENT OUT LOAD CURRENT (A) MAX5023 toc03 SUPPLY VOLTAGE (V) V CC VOLTAGE vs. LOAD CURRENT MAX5023 toc04 VCC VOLTAGE (V) V CC VOLTAGE vs. IN VOLTAGE I LOAD 5mA I LOAD 50mA MAX5023 toc05 SUPPLY VOLTAGE (V) I LOAD 5mA V CC VOLTAGE vs. TEMPERATURE MAX5023 toc LOAD CURRENT (ma) IN VOLTAGE (V) TEMPERATURE ( C) SWITCHING FREQUENCY (khz) SWITCHING FREQUENCY vs. R T R T (kω) MAX5023 toc07 SWITCHING FREQUENCY (khz) R T 66.5kΩ SWITCHING FREQUENCY vs. TEMPERATURE R T 33.2kΩ R T 22.kΩ TEMPERATURE ( C) MAX5023 toc08 IIN CURRENT (ma) V IN 2V I IN CURRENT vs. SWITCHING FREQUENCY C DL C DH 0nF C DL C DH 0nF C DL C DH 4.7nF C DL C DH nf SWITCHING FREQUENCY (khz) MAX5023 toc09 Maxim Integrated 5

6 (Supply IN 2V, unless otherwise noted. See Typical Application Circuit of Figure 6.) IIN + IVCC CURRENT (ma) I IN + I VCC CURRENT vs. SWITCHING FREQUENCY V IN V CC 5V C DL_ C DH_ 0nF C DL C DH 0nF C DL_ C DH_ 4.7nF C DL_ C DH_ nf SWITCHING FREQUENCY (khz) MAX5023 toc0 EN_ TURN-ON AND TURN-OFF THRESHOLDS EN_ TURN-ON AND TURN-OFF THRESHOLD vs. TEMPERATURE EN_ RISING EN_ FALLING TEMPERATURE ( C) MAX5023 toc LIM_ CURRENT (μa) LIM_ CURRENT vs. TEMPERATURE I LIM2 I LIM TEMPERATURE ( C) MAX5023 toc2 SHUTDOWN CURRENT (μa) SHUTDOWN CURRENT vs. TEMPERATURE TEMPERATURE ( C) MAX5023 toc3 CURRENT-LIMIT THRESHOLD (mv) CURRENT-LIMIT THRESHOLD vs. R LIM SOURCE CURRENT LIMIT R LIM (kω) SINK CURRENT LIMIT MAX5023 toc4 LOAD TRANSIENT ON OUT MAX5023 toc5 LOAD TRANSIENT ON OUT2 MAX5023 toc6 V OUT (AC-COUPLED) 00mV/div V OUT2 (AC-COUPLED) 200mV/div V OUT2 (AC-COUPLED) 50mV/div V OUT (AC-COUPLED) 00mV/div I OUT 5A/div I OUT2 2A/div 0μs/div 0μs/div 6 Maxim Integrated

7 (Supply IN 2V, unless otherwise noted. See Typical Application Circuit of Figure 6.) LINE-TRANSIENT RESPONSE MAX5023 toc7 STARTUP AND DISABLE FROM EN MAX5023 toc8 IOUT.2A V IN 5V/div V EN 5V/div V IN 0V/div V OUT (AC-COUPLED) 50mV/div V OUT 500mV/div V OUT2 (AC-COUPLED) 00mV/div V PGOOD 5V/div 2ms/div 2ms/div STARTUP AND DISABLE FROM EN MAX5023 toc9 IOUT2 500mA V EN2 5V/div STARTUP AND TURN-OFF FROM IN EN EN2 VCC IOUT.2A MAX5023 toc20 V IN 0V/div V IN 0V/div V OUT2 2V/div V OUT V/div V PGOOD2 5V/div V PGOOD 5V/div 2ms/div 4ms/div STARTUP AND TURN-OFF FROM IN MAX5023 toc2 STARTUP INTO PREBIASED OUTPUT (0.5V PREBIASED) MAX5023 toc22 IOUT2 500mA V IN 0V/div V OUT2 2V/div 0V V OUT 500mV/div V PGOOD2 5V/div 4ms/div 2ms/div Maxim Integrated 7

8 (Supply IN 2V, unless otherwise noted. See Typical Application Circuit of Figure 6.) STARTUP INTO PREBIASED OUTPUT (V PREBIASED) MAX5023 toc23 STARTUP INTO PREBIASED OUTPUT (.5V PREBIASED) MAX5023 toc24 V OUT 500mV/div V OUT 500mV/div 0V 0V 2ms/div 2ms/div IOUT 5A DH_ AND DL_ DISOVERLAP MAX5023 toc25 DH_ AND DL_ DISOVERLAP MAX5023 toc26 IOUT 5A V DH 0V/div V DL 5V/div V DH 0V/div V DL 5V/div V LX 0V/div V LX 0V/div 20ns/div 20ns/div OUT-OF-PHASE SWITCHING FORMS MAX5023 toc27 SINK CURRENT-LIMIT WAVEFORMS.5V PREBIASED MAX5023 toc28 IOUT 5A IOUT2 2.5A V LX 0V/div I LX 5A/div V LX2 0V/div I LX2 2A/div V OUT 200mV/div V LX 20V/div I LX 2A/div μs/div 00μs/div 8 Maxim Integrated

9 FB 2 EN 3 EN2 4 PGOOD 5 DL 6 PGND 7 LX 8 BST 9 DH 0 DH2 BST2 2 LX2 Maxim Integrated 9

10 3 PGND2 4 DL2 5 PGOOD2 6 V CC μ μ 7 FB2 8 COMP2 9 RT 20 SGND 2 IN 22 LIM2 23 LIM μ ± 24 COMP EP 0 Maxim Integrated

11 RT EN EN2 SGND IN VCC LIM2 LIM VREF OSCILLATOR ENABLE COMPARATOR VREF ENABLE2 COMPARATOR VREF THERMAL SHUTDOWN STARTUP BIAS ENABLE LOGIC IN UVLO VREF INTERNAL VOLTAGE REGULATOR VCC UVLO VREF 0.6V BANDGAP REFERENCE LIM CURRENT GENERATOR MAX5023 GEN MAX5023 CK2 COMP2 BST2 DH2 PGND2 CK ENABLE ENABLE2 CK2 ENABLE2 VREF LIM2 CK VREF DC-DC CONVERTER 2 SGND LIM PGOOD2 FB2 DL2 LX2 ENABLE VREF HICCUP SOFT-START/ STOP LOGIC AND HICCUP LOGIC CK RAMP GENERATOR BOOST DRIVER HICCUP TIMEOUT PWM CONTROL LOGIC HICCUP LIM/20 SINK CURRENT-LIMIT COMPARATOR SOURCE CURRENT-LIMIT COMPARATOR LIM/0 DC-DC CONVERTER FB DAC_VREF gm HICCUP TIMEOUT PWM RAMP PWM COMPARATOR GATEP HIGH- SIDE DRIVER VCC LOW-SIDE DRIVER ENABLE x VREF PGOOD COMPARATOR COMP BST DH LX DL PGND FB PGOOD Maxim Integrated

12 2 Maxim Integrated ± ±

13 ± ± µ µ (00 (4 x ) 6)mA 50mA Maxim Integrated 3

14 UVLO A B C D E F G H I V CC EN_ V OUT_ 2048 CLK CYCLES 2048 CLK CYCLES DAC_VREF_ DH_ DL_ SYMBOL DEFINITION SYMBOL DEFINITION UVLO V CC EN_ V OUT_ DAC_VREF_ DH_ DL_ A Undervoltage threshold value is provided in the Electrical Characteristics table. Internal 5.2V linear regulator output. Active-high enable input. Regulator output voltage. Regulator internal soft-start and soft-stop signal. Regulator high-side gate-driver output. Regulator low-side gate-driver output. V CC rising while below the UVLO threshold. EN_ is low. B C D E F G H I V CC is higher than the UVLO threshold. EN_ is low. EN is pulled high. DH_ and DL_ start switching. Normal operation. V CC drops below UVLO. V CC goes above UVLO threshold. DH_ and DL_ start switching. Normal operation. EN_ is pulled low. V OUT_ enters soft-stop. EN_ is pulled high. DH_ and DL_ start switching. Normal operation. V CC drops below UVLO. 4 Maxim Integrated

15 5 Maxim Integrated

16 VOUT VIN < Dmax Dmax V DROP2 + ( D max) VDROP VIN V R R MON 2 V EN_ H_ V MON MA5023 EN_ R R 2 VOUT VI N > ton(min) fsw 6 Maxim Integrated

17 VOUT _ R R2 V FB_ RT 0663 ( fsw ). OUT_ V V V L OUT( IN OUT) VINfSWIOUTLIR R R DS(ON,MAX) LIR ISAT > + ILOAD(MAX) RDS(ON,TYP) 2 MA5023 FB_ R 2 Maxim Integrated 7

18 LIR VITH > RDS ONMAX ILOAD MAX (, ) ( ) 2 IRMS ILOAD( MAX) 0 VITH_ RLIM_ 50μA VOUT( VIN VOUT) VIN Δ Δ ΔV ESRIN ESR ΔI I L OUT + 2 ( V V V ΔI IN OUT) OUT L VIN fsw L I D D C OUT ( ) IN ΔVQ fsw D V OUT VIN ΔVRIPPLE ΔVESR + ΔVQ 8 Maxim Integrated

19 ΔVESR ΔIL ESR ΔI ΔVQ L 8 COUT fsw ( V V V ΔI IN OUT) OUT L VIN fsw L Δ Δ ΔV ESR ESR ISTEP I t C STEP OUT RESPONSE ΔVQ ΔV t ESL ESL STEP ISTEP tresponse 3 fo fpo 2π LOUT COUT fzo 2π ESR COUT f f SW O 0 Maxim Integrated 9

20 GainMOD V ESR IN VOSC 2π fo LOUT ( ) VFB VOUT VIN ESR V FB gm RF VOSC ( 2π fo LOUT) VOUT VOSC ( 2π fo LOUT) VOUT RF VFB VIN gm ESR GainMOD GainEA fz 2π RF CF 075. fpo CF 2π RF fpo V OUT R CCF π RF fsw CF R 2 V REF g m R F COMP C F C CF GainEA gm RF 20 Maxim Integrated

21 fz 2π RF CF fz2 2π CI ( R + RI) f P 0 µ fp 2 2π RI CI fp 3 C C R F 2π CF F CF + CCF fz 2π RF CF 05. fpo CF 2π RF 0. 5 fpo V Gain IN MOD V 2 OSC ( 2π fo ) LOUT COUT VIN V 2 OSC ( 2π fo ) COUT LOUT GainEA 2π fo CI RF GainMOD GainEA ( ) VOSC 2π fo LOUT COUT CI VIN RF f P2 f ZO f P2 5 x f O RI 2π fp2 CI 2π fo CI RF Maxim Integrated 2

22 R f C R I 2π Z2 I CCF CF 2π 0. 5 fsw RF CF ( ) V R 2 FB R VOUT VFB R I C I R R 2 V OUT V REF R F g m C CF C F COMP PDRIVE VIN QG _ TOTAL fsw P T V IN x I IN P T V CC x (I IN + I VCC ) 22 Maxim Integrated

23 T J T A + (P T x θ JA ) θ θ T J T C + (P T x θ JC ) θ θ Qg CBST _ Δ VBST _ Δ Δ Δ Maxim Integrated 23

24 V OUT 2.kΩ 6.2kΩ 2.kΩ 22pF 3300pF 30.kΩ V IN 9V TO 6V μf 22.kΩ V OUT kΩ 45.3kΩ EN PGOOD2 200kΩ V CC 47kΩ 2 EN FB COMP LIM IN SGND MAX PGOOD2 LIM2 RT COMP2 9 8 R T 33kΩ 3300pF 20kΩ 390pF 33pF 0kΩ EN2 200kΩ 3 EN2 FB2 7 PGOOD V CC 47kΩ 4 PGOOD V CC 6 4.7μF V CC V IN V IN 0μF 25V 0μF 25V Q FDS DH 8 BST DH2 BST2 0 Q4 FDS6982AS-Q 0μF 25V V OUT 0.8μH C BST 0.22μF LX DL PGND PGND2 DL2 LX2 C BST2 0.22μF 3.3μH V OUT2 22μF 6.3V 500μF 2.5V 2200pF.5Ω Q3 FDS pF.5Ω 22μF 6.3V 22μF 6.3V 22μF 6.3V DL Q2 FDS8880 Q5 FDS6982AS-Q2 24 Maxim Integrated

25 V IN 4.5V TO 5.5V R8 C8 R5 C5 C6 R6 R0 R9 R T R PU PGOOD C IN V IN EN EN2 R7 24 LX COMP 23 BST LIM 22 DH LIM2 DH2 IN BST2 SGND 3 EN2 V CC 6 MAX PGOOD PGOOD LX2 RT FB COMP2 8 2 EN FB2 7 5 DL DL2 4 6 PGND PGND2 3 C2 R4 C5 R2 C4 C3 R3 R R PU2 PGOOD2 V IN C IN L Q C BST C BST2 Q3 L2 V OUT V OUT2 C OUT Q2 Q4 C OUT2 ± Maxim Integrated 25

26 V IN 3.3V R8 C8 V AUX 4.5V TO 5.5V R5 C5 C6 R6 R0 R9 R T PGOOD R PU C IN EN EN2 R7 24 LX COMP 23 BST LIM 22 DH LIM2 DH2 IN BST2 SGND 3 EN2 V CC 6 MAX PGOOD PGOOD LX2 RT FB COMP2 8 2 EN FB2 7 5 DL DL2 4 6 PGND PGND2 3 C2 R4 C5 C4 V IN 3.3V C IN2 C3 R R2 R PU2 R3 PGOOD L Q C BST C BST2 Q3 L2 V OUT V OUT2 C OUT Q2 Q4 C OUT2 26 Maxim Integrated

27 PROCESS: BiCMOS japan.maximintegrated.com/packages 24 TQFN-EP T Maxim Integrated 27

28 0 7/08 2/09 4, 5, 6 2 3/, 2, 3, Maxim Integrated 60 Rio Robles, San Jose, CA 9534 USA