ADC78H90 8-Channel, 500 kSPS, 12-Bit A/D Converter (jp)

Transcription

1 8-Channel, 500 ksps, 12-Bit A/D Converter Literature Number: JAJSA63

2 8 500kSPS 12 A/D 8 12 CMOS A/D 500kSPS / AIN1 AIN8 8 SPI QSPI MICROWIRE DSP (AV DD ) 2.7V 5.25V (DV DD ) 2.7V AV DD 3V 1.5mW 5V 8.3mW 3V 0.3 W 5V 0.5 W 16 TSSOP Channel, 500 KSPS, 12-Bit A/D Converter ds Updated electrical table parameters. Add Eval Board to Ordering Info, add min CLK freq, modify Note 5, resize some figures, modify some figures, clarify some app info text. Not released. NG Minor formatting changes. Awaiting art changes. NG New data sheet for Nick Gray, copied and renamed from ds and sent to RRD for art and sgml edits. CN Completely revised sections 1.0 and 2.0. Released to web. NG Clarified conditions for, changed typ Conv Time spec and Conversion Time definition from 12 to 13 clock cycles. Not released to web. NG 8 SPI /QSPI /MICROWIRE /DSP 16 TSSOP Modified Sect 7 to include Pwr Supply Noise Considerations. Released to web. NG Removed AGND-DGND spec from Op.Ratings. Released to web. NG Removed AGND DGND from table. Not yet released to web. NG 500 ksps DNL 1LSB ( ) INL 1LSB ( ) 3V 1.5mW ( ) 5V 8.3mW ( ) 8 500kSPS 12 A/D QSPI SPI ( ) National Semiconductor Corporation DS JP 1

3 I/O 4-11 AIN1 to AIN8 0V AV DD I/O 16 SCLK 15 DOUT 14 DIN 1 CS 50kHz 8MHz 8MHz SCLK SCLK CS CS Low 2 V DD 1cm 1 F 0.1 F 2.7V 5.25V 13 V DD 1cm 0.1 F 2.7V AV DD 3 AGND 12 DGND 2

4 (Note 1) AV DD 0.3V 6.5V DV DD 0.3V AV DD 0.3V 6.5V GND 0.3V AV DD 0.3V (Note 3) 10mA (Note 3) 20mA T A 25 (Note 4 ) ESD (Note 5) 2500V 250V ( ) 10 (Note 6) (Note 1 2) 40 T A 85 AV DD 2.7V 5.25V DV DD 2.7V AV DD 0.3V AV DD 50 khz 8 MHz 0V AV DD (Note 8) AV DD DV DD 2.7V 5.25V AGND DGND 0V f SCLK 8MHz f SAMPLE 500kSPS T A T MIN T MAX T A

5 (Note 8)( ) AV DD DV DD 2.7V 5.25V AGND DGND 0V f SCLK 8MHz f SAMPLE 500kSPS T A T MIN T MAX T A

6 AV DD DV DD 2.7V 5.25V f SCLK 8MHz f SAMPLE 500kSPS T A T MIN T MAX T A 25 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: GND 0V (V IN AGND V IN V A V D ) 10mA (20mA) 10mA 2 T J max ( : T J max 150 ) JA ( ) T A ( ) P D MAX (T J max T A )/ JA JA 16 TSSOP 96 /W P D MAX 1200mW mW 12mW ( ) 100pF 1.5 k 220pF AN-450 (SO) AOQL ( ) min/max t 1a t 1b CS (High Low) 5

7 Timing Test Circuit FIGURE 1. Timing Diagram Serial Timing Diagram 6

8 ( ) SCLK and CS Timing Parameters 7

9 (ACQUISITION TIME) (APERTURE DELAY) 4 SCLK (CONVERSION TIME) ADC (CROSSTALK) (DIFFERENTIAL NON-LINEARITY: DNL) 1 LSB (DUTY CYCLE) High SCLK (EFFECTIVE NUMBER OF BITS: ENOB) /( ) SINAD ENOB (SINAD 1.76)/6.02 A/D (FULL POWER BANDWIDTH) 3dB (GAIN ERROR) (V REF 1.5LSB) ( ) ( ) (INTEGRAL NON-LINEARITY : INL) ( 1/2LSB ) ( 1/2LSB ) (INTERMODULATION DISTORTION: IMD) A/D 2 2 IMD db (MISSING CODES) ADC (OFFSET ERROR) (GND 0.5LSB) ( ) ( ) / (SIGNAL TO NOISE RATIO : SNR) 1/2 DC db /( ) (SIGNAL TO NOISE PLUS DISTORTION RATIO : (S/N D) or SINAD) 1/2 DC db (SPURIOUS FREE DYNAMIC RANGE : SFDR) db DC (TOTAL HARMONIC DISTORTION) 2 6 db dbc THD A f1 (RMS ) A f2 A f6 2 6 (THROUGHPUT TIME) 16SCLK 8

10 T A 25 f SAMPLE 500kSPS f SCLK 8MHz f IN 40.2kHz DNL DNL INL INL DNL vs. Supply INL vs. Supply 9

11 ( ) T A 25 f SAMPLE 500kSPS f SCLK 8MHz f IN 40.2kHz SNR vs. Supply THD vs. Supply ENOB vs. Supply SNR vs. Input Frequency THD vs. Input Frequency ENOB vs. Input Frequency 10

12 ( ) T A 25 f SAMPLE 500kSPS f SCLK 8MHz f IN 40.2kHz Spectral Response Spectral Response Power Consumption vs. Throughput 11

13 1.0 D/A A/D Figure 2 3 Figure 2 SW1 8 1 SW2 CS Low 3 SCLK ADC 1 (AIN1) Figure 3 SW1 SW2 ( ) DAC DAC CS Low 13 SCLK FIGURE 2. in Track Mode FIGURE 3. in Hold Mode CS Low 16 DOUT DIN 2.0 CS SCLK ( ) DOUT MSB DIN DIN 12

14 ( ) CS CS 16 SCLK ADC (DOUT) CS High CS Low CS CS High SCLK 3 ADC 13SCLK MSB CS Low 1 3 SCLK ADC 4 16 SCLK 1 2 N 16 SCLK SCLK ADC N 16 4 SCLK / "N" CS High SCLK SCLK LOW CS HIGH CS SCLK ADC ADC SCLK SCLK HIGH CS HIGH ADC CS SCLK 8 SCLK DIN Table CS SCLK Low SCLK DIN TABLE 1. Control Register Bits TABLE 2. Control Register Bit Descriptions 7, 6, 2, 1, 0 DONTC Don't care 5 ADD2 3 CS 4 ADD1 Table 3 3 ADD0 13

15 ( ) TABLE 3. Input Channel Selection 3.0 LSB LSB LSB AV DD /4096 Figure /2 LSB AV DD / LSB 4.0 Figure 5 LP2950 (AV DD ) AV DD 4 DSP FIGURE 4. Ideal Transfer Characteristic FIGURE 5. Typical Application Circuit 14

16 ( ) 5.0 Figure 6 D1 D2 ESD ESD (AV DD 300mV) (GND 300mV) Figure 6 C1 3pF R1 / 500 C2 30pF AC CS Low CS High 16 SCLK 1 SCLK (Figure 1 ) 16 SCLK CS Low "Power Consumption vs. Throughput" ( AV DD DV DD 3.6V 8.3mW) (AV DD DV DD 3.6V 0.3mW) FIGURE 6. Equivalent Input Circuit 6.0 (SCLK CS DIN) AV DD DV DD SCLK CS DIN ESD ESD (DV DD ) (AV DD ) 300mV ( ) 7.2 DV DD ADC SN SINAD High Low 25pF ADC

17 8 500kSPS 12 A/D millimeters 16-Lead TSSOP Order Number CIMT, CIMTX NS Package Number MTC16 (CEO) (GENERAL COUNSEL) a (b) National Semiconductor Copyright 2007 National Semiconductor Corporation / TEL.(03)

18 IMPORTANT NOTICE