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1 Fundamentals

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8 DDR S IC

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11 UDIMM UDIMM UDIMM UDIMM

12 RDIMM RDIMM RDIMM RDIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM 0 DDR2 FB-DIMM 1 DDR2 FB-DIMM 7 DDR2

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14 FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM FB-DIMM

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19 AMBAdvanced Memory Buffer Amplitude Analog Signal ADCAnalog-to-Digital Converter Asynchronous Attenuation BGABall Grid Array Bandwidth Bit Byte CE#Chip Enable Cursor CRCCyclic Redundancy Code dbdecibel DUTDevice Under Test Digital Oscilloscope DPODigital Phosphor Oscilloscope Digital Sampling Oscilloscope Digital Signal CS#Chip Select Clock Rate CAS#Column Address Select

20 DSODigital Storage Oscilloscope Digitize DDRDouble Data Rate DIMMDual Inline Memory Module Dynamic Random Access Memory ECCError Correction Code FETField Effect Transistor FBGAFine-pitch Ball Grid Array Frequency FB-DIMMFully Buffered Dual Inline Memory Module GbGigabit GBGigabyte GHzGigahertz GT/sGigatransfers per Second HzHertz icapture MultiplexingiCapture ilink Toolset ilink I/OInput/Output ICIntegrated Circuit Interleave iverify AnalysisiVerify iview DisplayiView JEDEC Joint Electron Device Engineering Council khzkilohertz Latency Loading Logic Analyzer Glitch

21 MagniVu AcquisitionMagniVu MbMegabit MBMegabyte MHzMegahertz MS/sMegasamples per second MT/sMegatransfers per second Memory Cycle Time smicrosecond msmillisecond Mini-DIMM Miniature Dual Inline Memory Module Motherboard Nanosecondns Noise Oscilloscope OE#Output Enable Period Pre-trigger Viewing Precharge Probe Pluse Pluse Train Pluse Width Ramps RAMRandom Access Memory ReadCycle

22 Record Length Refresh RDIMMRegistered Dual Inline Memory Module Rise Time RAS#Row Address Select Sample Point Sample Rate Sampling SPDSerial Presence Detect Signal Integrity Signal Source SO-DIMMSmall Outline Dual Inline Memory Module Synchronous SSynchronous Dynamic Random Access Memory SUTSystem Under Test TDRTime Domain Reflectometry Trigger Trigger Holdoff Trigger Level

23 UDIMMUnregistered Dual Inline Memory Module VLP-DIMMVery Low Profile Dual Inline Memory Module VVolt Voltage Wave WE#Write Enable

24 Tektronix : (65) (11) (800) (0) (221) (852) (91) (02) (3) (0) (55) (10) (2) (+34) (2) (0) (800) (503) Updated 5 January Copyright 2005, Tektronix. All rights reserved. Tektronix TEKTRONIXTEK Tektronix, Inc. 11/05 FLG/W0W 52Z TEL FAX

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