1 FabScalar FabCache FabBus FabHetero FabCache FabCache FabCache FabCache FabCache ns 0.1
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- さゆり ひきぎ
- 5 years ago
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1 2015 (413M505)
2 1 FabScalar FabCache FabBus FabHetero FabCache FabCache FabCache FabCache FabCache ns 0.1
3 Abstract Single-ISA heterogeneous multi-core architecture which consists of diverse superscalar cores is increasing importance in the processor architecture. Using a proper superscalar core for characteristic in a program contributes to reduce energy consumption and improve performance. However, designing a heterogeneous multi-core processor requires a large design and verification effort. Therefore, FabHetero has been proposed which generates diverse heterogeneous multi-core processors automatically using FabScalar, FabCache, and FabBus which generate various designs of superscalar core, cache system, and flexible shared bus system, respectively. This paper presents the detail of FabCache and shows that the caches generated by FabCache with arbitrary parameter values such as cache capacity, line size, associativity, access latency, and line transmission width between cache hierarchies work correctly. This paper also focuses on performance estimation and the physical design of the caches. According to the estimation results, FabCache generates cache systems which have almost the same area and power consumption as hand-tuned cache because the ratio of L1 instruction and data cache controller including extra circuits is only 3.5% and the increased power consumption by comparing with hand-tuned cache is less than 0.1% although having the overhead of automatic generation.
4 FabHetero FPGA LEON FabCache L L L FabCache i
5 39 40 A 46 B 46 ii
6 2.1 Homogeneous and Heterogeneous multi-core Example of Cache System FabHetero Implementation of interleaved L1 instruction cache L1 Data Cache L2 cache design Fetch image of superscalar Interleaved memory Interleaved memory Interleaved memory Miss status holding register Cache hit rate L1Icache Power Consumption L1Dcache Power Consumption Chip image of L1 instruction cache Chip image of L1 data cache iii
7 5.1 Available designs in FabCache EDA environment Delay iv
8 1 [1, 2, 3, 4] RTL(Register Transfer Level) FabScalar [5, 6, 7, 8, 9, 10, 11] FabScalar FabScalar 1
9 FabHetero [12] FabHetero 3 FabScalar FabCache [13] FabBus [14, 15] 3 FabHetero 4 5 FabCache 6 7 FabCache 2
10 2 2.1 Homogeneous Heterogeneous 2.1: Homogeneous and Heterogeneous multi-core CPU 1 ( 2.1 ) ( 2.1 ) 3
11 2.2 50% 2.2 L1 L
12 CPU L1 L2 2.2: Example of Cache System
13 6
14 FabScalar Core0 Core1 Core2 FabCache L1 Inst Cache L1 Data Cache L1-I L1-D L1-I L1-D L2 Cache L2-I L2-D FabBus Inter Connect Last level cache or main memory 3.3: FabHetero 3 FabHetero FabCache FabHetero FabHetero FabHetero 7
15 FabScalar FabCache FabBus FabHetero 3 (Core 0, Core 1, Core 3) Core 0 L1 L1 Core 1 L1 L2 Core 2 L1 L2 L1 L2 FabHetero FabScalar, FabCache, FabBus FabScalar, FabBus 8
16 FabCache 3.1 FabScalar N.K.Choudhary RTL [16] FabScalar ILP 1 8 Load store unit (LSU) load store queue (LSQ) FabScalar 3.2 FabBus 9
17 FabBus FabBus ARM AMBA 3.3 [1, 2, 3, 5, 17] B. de Abreu Silva [17] 10
18 FabCache 11
19 4 [18, 19, 20, 21] 4.1 FPGA FPGA P. Yiannacouras [18]
20 4.2 LEON Leon4 [19] 2 n [20, 21] 13
21 5 5.1 FabCache L1 3.3 L1 L2 3.3 L1L2 L2 L2 FabCache 1 FabScalar 14
22 FabCache FabCache ASIC FabCache n 3 15
23 5.1: Available designs in FabCache Memory hierarchy Dimensions( L = line size, Specific microarchitectures S = set size, W = associativity) L1 instruction cache L = (fetch width to 2 n ) 4(byte) two banks interleaved vs. non-interleaved S = 1 to 2 n 1 to 8 fetch width W = 1, 2 n -way, full Interface with L2 cache line size transmission vs. burst transmission enable vs. disable L1 data cache L = (1 to 2 n ) 4(byte) Miss handling S = 1 to 2 n blocking vs. non-blocking W = 1, 2 n -way, full Writing approach MSHR = 1 to 8 entry write-through vs. write-back Interface with L2 cache line size transmission vs. burst transmission enable vs. disable L2 cache L = wider than higher hierarchy dedicated instruction and data vs. unified S = 1 to 2 n Cache coherency W = 1, 2 n -way, full MOESI vs. MOSI vs. MEI vs. dedicated for each processor core. interface with shared memory processor num to/from one vs. processor num to/from multi-ported memory cache replacement policy LRU vs. Pseudo-LRU enable vs. disable
24 I/O I/O FabCache LRU 100 % 17
25 6 L1 L2 6.1 FabCache SystemVerilog 1 RTL P. Yiannacouras [18] RTL RTL 18
26 FabCache RTL FabCache 19
27 6.2 L1 PC Tag Index Bank select bit Line select bit byte offset {Tag, Index} {Tag, Index} + 1 Bank select bit {Tag, Index} Bank select bit Line select bit Fetch width Even Bank line size set size way size are defined in parameter file swap Odd Bank line size set size way size are defined in parameter file (a, b, c, d) (e, f, g, h) (a, b, c, d, e, f, g, h) or (e, f, g, h, a, b, c, d) squeeze N (Fetch width) instructions 6.4: Implementation of interleaved L1 instruction cache 6.4 L1 L1 2 swap squeeze 20
28 L2 cache Store Ack Store request Replay request Miss status holding register Filled data Missed address Stage 1 Stall Stage 2 Store buffer Load buffer Memory buffer Request from cpu Tag memory controller Tag address Tag Hit/Miss signal Tag SRAM memory Data memory controller CPU Requested data Data SRAM memory Data address 6.5: L1 Data Cache bank select bit Line select bit 2 ( ) squeeze 6.3 L1 6.5 L1 L1 2 miss status holding register (MSHR) 21
29 2 LRU Holding register 2 MSHR MSHR 1 MSHR L2 22
30 L1 inst. L1 data dedicated design Superset interface design L2 inst. or L2 bank0 L2 data or L2 bank1 bank select bit == 0 unified design arbiter0 arbiter1 bank select bit == 1 6.6: L2 cache design 6.4 L2 L L2 L2 2 L2 1 L2 L2 L2 2 L2 L
31 L2 L1-L2 L2 L1 L2 L2 2 (2 ) SRAM L2 24
32 Core Cache 1 FETCH_WIDTH : Fetch image of superscalar Line0 Line1 Line2 Line3 Line4 Line5 Line6 Line7 a b c d e f g h i j k l m n o p Line0 Line2 c d a b c d i j k l c d e f e f Line1 e f g h Line3 m n o p Normal Memory Even Bank Odd Bank 6.8: Interleaved memory FabScalar
33 Even Bank a b c d i j k l q r s t Odd Bank e f g h m n o p u v w x (a, b, c, d) (e, f, g, h) swap (a, b, c, d, e, f, g, h) squeeze (b,c,d,e) 6.9: Interleaved memory FabScalar 4 a p ( a b c d )
34 Even Bank a b c d i j k l q r s t Odd Bank e f g h m n o p u v w x (i, j, k, l) (e, f, g, h) swap (e, f, g, h, i, j, k, l) squeeze (f,g,h,i) 6.10: Interleaved memory c d e f L1 2 27
35 c d e f 4 c, d e f squeeze 1 swap f, g, h, i i f, g, h swap [22] FabCache CPU L1 AMBA4 16 MSHR 28
36 L2 Cache Filled data with ID Fill buffer Missed request address Filled data or Invalidate signal Stall signal Fill signal with ID Missed request address MHSR is full stage 2 stage 1 Missed request packet Status Miss status holding registar Comparator and status collection Replay signal Stall signal 6.11: Miss status holding register AMBA4 4 ID 16 MSHR 16 29
37 MSHR 6.11 MSHR MSHR MSHR 2 1 MSHR ID fill buffer Fill buffer L2 fill buffer 1 fill buffer MSHR ID fill fill MSHR ID replay 30
38 1 6.6 FabCache FabCache FabHetero AMBA AMBA System on Chip (SOC) FabCache AMBA AMBA FabCache 1 31
39 7.2: EDA environment. Phase EDA tool functional verification Cadence NC-Verilog S038 synthesis Synopsys Design Compiler SP2 place & route Synopsys IC Compiler G power estimation Synopsys XA G SP RTL SPEC2000INT EDA FabCache SPEC2000INT
40 1 gap Hit rate 0.9 Direct 2-way 4-way 8-way 16-way Hit rate Cache capacity (KB) mcf Direct 2-way 4-way 8-way 16-way Cache capacity (KB) 7.12: Cache hit rate 16 FabCache 33
41 1 FabCache design Hand design gzip gcc bzip mcf Benchmarks 7.13: L1Icache Power Consumption. 1 FabCache design Hand design gzip gcc bzip mcf Benchmarks 7.14: L1Dcache Power Consumption. 7.3: Delay. Design L1 instruction cache L1 data cache FabCache 2.39ns 2.45ns Hand-tuned 2.27ns 2.32ns 7.2 L1 L1 RTL L1 LRU L1 34
42 MSHR SPEC2000 INT 5000 EDA Synopsys XA G SP2 7.13, 7.14 L1 FabCache design 7.13, 7.14 FabCache design FabCache 7.3 FabCache 0.1% 0.1ns RTL 35
43 Cache Control Logic RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO 7.15: Chip image of L1 instruction cache ,7.16 L1 L1 8KB 4 1 LRU L1 1 MSHR FabCache Rohm 180nm [23] 7.15,7.16 Cache control logic 36
44 Cache Control Logic RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO RAM MACRO 7.16: Chip image of L1 data cache. RAM MACRO SRAM 58,496.25µm 2 60,232.16µm 2 SRAM 1,668, µm 2 1,669, µm 2 3.5% 3.6% RTL 37
45 8 FabCache FabCache L1 FabCache L1 3.5% 0.1ns 1% FabCache 38
46 . Synopsys CAD VDEC Rohm VDEC 39
47 [1] R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, K. I. Farkas. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. 31st International Symposium on Computer Architecture (ISCA31), pp , June [2] H. H. Najaf-abadi, E. Rotenberg. Configurational Workload Characterization. International Symposium on Performance Analysis of Systems and Software 2008 (ISPASS-2008), pp , April [3] P. Greenhalgh. Big.LITTLE Processing with ARM Cortex-A15 & Cortex-A7. ARM WHITE PAPER: Final.pdf. [4] P. Greenhalgh. Big.LITTLE Processing with ARM Cortex-A15 & Cortex-A7. ARM WHITE PAPER: big.little Final.pdf. [5] N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi and E. Roten- 40
48 berg. FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. 38th IEEE/ACM International Symposium on Computer Architecture (ISCA-38), pp , June Rationale for a 3D Heterogeneous Multi-core Processor. Proceedings of the 31st IEEE International Conference on Computer Design (ICCD-31), pp , Oct [6] N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. FabScalar: Automating Superscalar Core Design. Micro, IEEE (Volume:32, Issue: 3 ), pp , June [7] R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan and D. M. Tullsen. Single-ISA Heterogeneous Multi-core Architectures: The Potential for Processor Power Reduction. Int l Symposium on Microarchitecture, Dec [8] H. H. Najaf-abadi, N. K. Choudhary and E. Rotenberg. Core- Selectability in Chip Multiprocessors. 18th Int l Conference on Parallel Architectures and Compilation Techniques, Sep
49 [9],, Eric Rotenberg,,, FabScalar Alpha 21264, SACSIS2012. [10] E. Rotenberg, B. H. Dwiel, E. Forbes, Z. Zhang, R. Widialaksono, R. Basu Roy Chowdhury, N. Tshibangu, S. Lipa, W. R. Davis, and P. D. Franzon. [11] N. K. Choudhary, B. H. Dwiel, E. Rotenberg. A physical design study of fabscalar-generated superscalar cores. VLSI and System-on-Chip (VLSI-SoC), 2012 IEEE/IFIP 20th International Conference on, pp , Oct [12] T. Nakabayashi, T. Sasaki, E. Rotenberg, K. Ohno and T. Kondo. Research for Transporting Alpha ISA and Adopting Multi-processor to FabScalar. Symposium on Advanced Computing Systems and Infrastructures 2012 (SACSIS2012), pp , May (in Japanese) [13] T. Okamoto, T. Nakabayashi, T. Sasaki, T. Kondo. FabCache: Cache Design Automation for Heterogeneous Multi-core Processors. 42
50 Proceedins of the 1st International Symposium on Computing and Networking, pp , Dec [14], AMBA,SWOPP2012. [15] Y. Seto, T. Nakabayashi, T. Sasaki, and T. Kondo. FabBus: A Bus Framework for Heterogeneous Multi-core processor. 28th International Technical Conferench on Circuits/Systems, Computers and Communications (ITC-CSCC2013), pp , July [16] N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi and E. Rotenberg. FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. Proceeding of the 38th IEEE/ACM Int l Symposium on Computer Architecture (ISCA-38), pp , June [17] B. de Abreu Silva, L.A. Cuminato and V. Bonato. Reducing the overall cache miss rate using different cache sizes for Heterogeneous 43
51 Multi-core Processors. Reconfigurable Computing and FPGAs (Re- ConFig), pp. 1-6, Dec [18] P. Yiannacouras and J. Rose. A Parameterized Automatic Cache Generator for FPGAs Field-Programmable Technology (FPT), pp , Dec [19] Leon 4 and GRLIB. [20] Thomas D. Tessier, Designing, Verifying and Building an Advanced L2 Cache Sub-System using SystemC. ISCUG, April [21] Akgul, B.E.S., Mooney, V.J,PARLAK: Parametrized Lock Cache Generator Design, Automation and Test in Europe Conference and Exhibition, pp , April [22] D. Kroft., Lockup-free instruction fetch/prefetch cache organization. International Symposium on Computer Architecture Proceedings of the 8th annual symposium on Computer Architecture, pp , May [23] H. Onodera, A. Hirata, A. Kitamura, K. Kobayashi, and K. Tamaru, P2Lib:Process Portable Library and Its Generation System, Journal 44
52 of Information Processing, vol.40, no. 4, pp , April, 1999, (In Japanese). 45
53 A B 46
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