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1 rank GPU ERATO / 26
2 GPU rank/select wavelet tree balanced parenthesis GPU rank 2 / 26
3 GPU rank/select wavelet tree balanced parenthesis GPU rank 2 / 26
4 GPU rank/select wavelet tree balanced parenthesis GPU rank 2 / 26
5 1 2 3 CUDA / 26
6 1 2 3 CUDA / 26
7 x {0, 1} n b {0, 1} rank b (x, i) := x[1i] b rank 1 (x 1, 4) = 2 rank 0 (x 2, 7) = x 1 = x 2 = / 26
8 x {0, 1} n b {0, 1} rank b (x, i) := x[1i] b rank 1 (x 1, 4) = 2 rank 0 (x 2, 7) = x 1 = x 2 = / 26
9 x {0, 1} n b {0, 1} rank b (x, i) := x[1i] b x {0, 1} n rank b (x, i) O(1) o(n) GPU 6 / 26
10 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
11 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
12 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
13 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
14 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
15 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
16 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
17 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
18 Jacobson 89 rank 0 (B, i) = i rank 1 (B, i) rank 1 (B, i) B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST rank 1 (B, i) = LT[i/L] + ST[i/S] + rank 7 / 26
19 1 2 3 CUDA / 26
20 CUDA GPU NVIDIA GPU C / C++ Single Instruction Multiple Thread SIMT 32 9 / 26
21 10 / 26
22 4GB 1 49kB 11 / 26
23 CUDA = = / 26
24 1 2 3 CUDA / 26
25 1 Population count (Popcount) 32bit / 64bit 1 GPU 2 Prefix sum (x ( 1, x 2,, x k,, x n ) x 1, x 1 + x 2,, k i=1 x k,, ) n i=1 x i O(log n) 14 / 26
26 Prefix Sum 1 1 i 2 i / 26
27 Prefix Sum 1 1 i 2 i / 26
28 Prefix Sum 1 1 i 2 i / 26
29 Prefix Sum 1 1 i 2 i / 26
30 Prefix Sum 1 1 i 2 i / 26
31 Prefix Sum 1 1 i 2 i / 26
32 B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST / 26
33 B LT ST B L L = log 2 n LT 2 B S S = log n/2 ST / 26
34 B Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
35 B Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
36 B (Prefix sum) Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
37 B (Prefix sum) ST Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
38 B (Prefix sum) ST LT Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
39 B (Prefix sum) ST LT (Prefix sum) Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
40 B ST LT Popcount 2 Prefix Sum 3 1 ST 4 1 LT 5 LT Prefix Sum 17 / 26
41 LT n = MB GPU CPU Prefix sum 18 / 26
42 LT n = MB GPU CPU Prefix sum 18 / 26
43 Prefix Sum 1 2 Prefix Sum Prefix Sum 6 Prefix Sum 19 / 26
44 1 2 3 CUDA / 26
45 CPU AMD Phenom X (25GHz) GPU Tesla C GHz 4 GB 49 kb Sux: Implementing Succinct Data Structures Broadword Implementation of Rank / Select Queries S Vigna WEA 2008: 7th International Workshop on Experimental Algorithms (pp ) 21 / 26
46 (1) 2 log n ,194, Mbit 1Gbit 3Gbit Sux(CPU) s s s GPU s s s CPU/GPU = 04 s n = 3G 22 / 26
47 (1) 2 log n ,194, Mbit 1Gbit 3Gbit Sux(CPU) s s s GPU s s s CPU/GPU = 04 s n = 3G 22 / 26
48 (1) 2 log n ,194, Mbit 1Gbit 3Gbit Sux(CPU) s s s GPU s s s CPU/GPU = 04 s n = 3G 22 / 26
49 (1) 2 log n ,194, Mbit 1Gbit 3Gbit Sux(CPU) s s s GPU s s s CPU/GPU = 04 s n = 3G 22 / 26
50 (1) 2 log n ,194, Mbit 1Gbit 3Gbit Sux(CPU) s s s GPU s s s CPU/GPU = 04 s n = 3G 22 / 26
51 (2) n = 3G 2 log n 64 m / 26
52 (2) n = 3G 2 log n 64 m / 26
53 (3) n = 3G k 2 log n 64k m / 26
54 (3) n = 3G k 2 log n 64k m / 26
55 1 2 3 CUDA / 26
56 GPU 28 GPU 26 / 26
57 GPU 28 GPU 26 / 26
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A = QΛQ T A n n Λ Q A = XΛX 1 A n n Λ X GPGPU A 3 T Q T AQ = T (Q: ) T u i = λ i u i T {λ i } {u i } QR MR 3 v i = Q u i A {v i } A n = 9000 Quad Core Xeon 2 LAPACK (4/3) n 3 O(n 2 ) O(n 3 ) A {v i }
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A = QΛQ T A n n Λ Q A = XΛX 1 A n n Λ X GPGPU A 3 T Q T AQ = T (Q: ) T u i = λ i u i T {λ i } {u i } QR MR 3 v i = Q u i A {v i } A n = 9000 Quad Core Xeon 2 LAPACK (4/3) n 3 O(n 2 ) O(n 3 ) A {v i }
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