FabHetero FabHetero FabHetero FabCache FabCache SPEC2000INT IPC FabCache 0.076%
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1 2013 (409812)
2 FabHetero FabHetero FabHetero FabCache FabCache SPEC2000INT IPC FabCache 0.076%
3 Abstract Single-ISA heterogeneous multi-core processors are increasing importance in the processor architecture. However, designing a single-isa heterogeneous multi-core requires design and verification effort which is multipliedby the number of different cores. processor. Therefore, FabHetero is proposed to solve this problem. FabHetero generates diverse heterogeneous multi-core processors automatically using FabScalar, FabCache, and FabBus. This paper proposes and implements FabCache which can automatically generate diverse cache systems of FabHetero. To indicate that the cache generated by FabCache works correctly, we execute 10 million instructions on SPEC2000INT benchmarks. we compared the area of auto-generated cache by FabCache with the area of hand designed cache. According to the evaluation results, caches generated by FabCache work correctly and occupy almost the same area compared with hand-designed cache.
4 FabScalar FabHetero FabBus FabCache A 23 B 23 i
5 FabHetero Instruction Per Cycle Instruction Per Cycle Instruction Per Cycle Instruction Per Cycle ii
6 5.1 L iii
7 1 RTL(Register Transfer Level) FabScalar[1] FabScalar FabScalar FabHetero[2] FabHetero 1
8 FabHetero FabCache 3 4 FabScalar 5 FabHetero 6 FabCache 7 2
9 2 Homogeneous Heterogeneous 2.1: CPU 1 ( 2.1) ( 2.1) 3
10 4
11 3 3.1 FabScalar FabScalar[2] FabScalar FabScalar FabScalar FabHetero 5
12 F D E M W
13 SinglePipeline 1 F D 2 3 SuperScalar 1 F D 2 F D F D F D F D E M W F D E M W E M W E M W F D F D E M W E M W E M W E M W E M W 3.2: 2 7
14 4 FabHetero FabScalar FabCache L1 Inst Cache PU0 PU1 PU2 Implemented L1 Data Cache L1-I L1-D L1-I L1-D L2 L2-I L2-D FabBus Shared Memory 4.3: FabHetero FabHetero 4.3 FabHetero FabScalar FabCache FabBus FabScalar FabCache FabBus 8
15 FabHetero FabCache 4.1 FabBus FabBus 9
16 5 FabCache L1 4.3 L1 L2 4.3 L1L2 L2 L2 FabCache FabCache L1 L1 5.1 Fetch Width 1 Cache Size Way Size Line Size 1 Word Size between L1 and L2 L1 L2 SRAM Access Latency SRAM 10
17 5.1 1 FabScalar FabCache 5.1: L1 PARAMETER RANGE Fetch Width 1 8 Cache Size 2 n Way Size 1 32 Line Size 1 8 Word Size between L1 and L2 1 LineSize SRAM Access Latency depend on SRAM module 11
18 5.1 Core Cache 1 FETCH_WIDTH : FabScalar FabScalar 4 12
19 a p ( a b c d ) c d e f c d e f c d e f 1 13
20 Line0 Line1 Line2 Line3 Line4 Line5 Line6 Line7 1 c d e f a b c d e f g h i j k l m n o p Line0 Line2 c d e f a b c d i j k l Line1 Line3 e f g h m n o p Normal Memory Even Bank Odd Bank 5.5: 5.2 L1 System Verilog d e f 14
21 4 c d e f d e f 2 15
22 6 FabCache SPEC2000INT bzip gzip gap mcf parser voretx IPC) IPC 128KB IPC 100% IPC FabCache IPC FabCache FabCache % FabCache 1 16
23 Line0 Line1 Line2 Line3 Line4 Line5 Line6 Line7 a b c d e f g h i j k l m n o p Line0 Line2 a b c d i j k l c d e c d e f Line1 Line3 e f g h m n o p Normal Memory Even Bank Odd Bank 6.6: 2 6.2: FabCache m ns m ns 7 FabCache 0 076%
24 1.4 1 FETCH WIDTH IPC bzip gzip gap 0.2 mcf parser vortex Cache Size(KB) Perfect : Instruction Per Cycle1 2 FETCH WIDTH IPC bzip 0.4 gzip gap mcf 0.2 parser vortex Cache Size(KB) Perfect 6.8: Instruction Per Cycle2 18
25 1.4 4 FETCH WIDTH IPC bzip gzip gap 0.2 mcf parser vortex Cache Size(KB) Perfect : Instruction Per Cycle4 8 FETCH WIDTH IPC bzip gzip gap 0.2 mcf parser vortex Cache Size(KB) Perfect 6.10: Instruction Per Cycle8 19
26 L1 L2 20
27 21
28 [1] N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi and E. Rotenberg. FabScalar: Composing Synthesizable RTL Designs of Arbitrary Cores within a Canonical Superscalar Template. Proceeding of the 38th IEEE/ACM Int l Symposium on Computer Architecture (ISCA-38), pp , June [2],, Eric Rotenberg,,, FabScalar Alpha 21264, SACSIS2012. [3], AMBA,SWOPP
29 A B PARAMETER RANGE FabCache SIZE ICACHE SIZE ICACHE WAY 1 SIZE DCACHE 8192 SIZE DCACHE WAY 1 L2LATENCY 1 FabScalar FETCH WIDTH : 23
Core1 FabScalar VerilogHDL Cache Cache FabScalar 1 CoreConnect[2] Wishbone[3] AMBA[4] AMBA 1 AMBA ARM L2 AMBA2.0 AMBA2.0 FabScalar AHB APB AHB AMBA2.0
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Kochi University of Technology Aca Title 省 電 力 セルフタイム 回 路 に 関 する 研 究 Author(s) 岩 田, 誠, 宮 城, 桂, 三 宮, 秀 次, 西 川, 博 昭 Citation 高 知 工 科 大 学 紀 要, 10(1): 95-102 Date of 2013-07-20 issue URL http://hdl.handle.net/10173/1082
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