LSI LSI
|
|
- ゆうりゅう つねざき
- 5 years ago
- Views:
Transcription
1 EDA EDA Electric Design Automation LSI LSI FPGA Field Programmable Gate Array Verilog HDL FPGA Verilog HDL EDA 2 10 BCD: Binary Coded Decimal 3 1 BCD LSI 2 Verilog HDL 3 EDA EDA
2 LSI LSI FPGA Verilog HDL Verilog HDL always EDA FPGA EDA Verilog-XL Design Compiler FPGA Altera DE Altera QuartusII EDA Verilog HDL FPGA
3 5 EDA FPGA Altera DE Verilog HDL : :
4 1 1.1 LSI LSI CPU LSI LSI LSI LSI LSI LSI LSI CAD Computer Aided Design HDL: Hardware Description Language 1.2 HDL RTL: Register Transfer Level HDL HDL VHDL, Verilog HDL 1
5 1: LSI VHDL VHSIC Very High Speed Integrated Circuit VHDL: VHSIC Hardware Description Language HDL VHDL Ada Verilog HDL Cadence Verilog XL Verilog HDL C VHDL IEEE Std-1076 VHDL87 Std-1164 VHDL93 Verilog HDL IEEE Std-1364 NTT SFL LSI PARTHENON PARTHENON SFL LSI LSI HDL UDL/I C, C++, Java 1.3 LSI 1 LSI 2
6 1.3.1 RTL: Register Transfer Level AND OR NOT LSI
7 1.3.5 LSI FPGA LSI LSI FPGA Field Programmable Gate Array FPGA FPGA FPGA LSI FPGA FPGA FPGA LSI 4
8 2 Verilog HDL 2.1 Verilog HDL Verilog HDL C Verilog HDL S1 0 1 D0 D1 Y Verilog HDL /* */ // Verilog HDL module, module mux21 ( ) ( ) C ANSI K&R S1, D0, D1 Y Y ~, &, Verilog HDL *.v 2.2 Verilog HDL reg, wire reg wire reg /* * * mux21.v * * 2-1 * * (2-1 ) * * */ module mux21 (S1, D0, D1, Y); // input S1, D0, D1; // S1, D0, D1 output Y; // Y // Multiplexer body // Y = ((not S1) and D0) or (S1 and D1) assign Y = (~S1 & D0) // ( S1 & D1); // assign module 2: 2-1 5
9 &, bitwise AND, OR a & b ~ bitwise NOT ~a ^ bitwise XOR a ^ b { } {a, b} &,, ^ AND, OR, XOR &a a[n] & a[n-1] &... & a[0] ~&, ~ NAND, NOR ~& a ~(a[n] & a[n-1] &... & a[0]) +,-,*,/,% a + b ==,!=, === a == b >, >=, <, <=, = a > b? : (a>=b)? a : b <<, >> a << 2 [n:m] / a[3:2] {a[3], a[2]} 10 0, 1, 29 n bxx n 2 2 b01 n hxx n ha5a 3: Verilog HDL input, output, inout, reg, wire Verilog HDL 1 0, 1, x, z 4 x z [3:0] C 3 C {a, b} & a, a [0:255] wire, reg wire assign?: always if, case, casex 2.3 always Verilog HDL always always if 2 Y always or D0 or D1) begin Y = (~S1 & D0) ( S1 & D1); ) ( ) posedge negedge or always reg always = <= 6
10 begin - reg 1 always Y <= X; Z <= Y; Z Y X Y reg always reg always always always wire always assign always assign always 1 always assign Z = X & Y; t X X(t) Z(t + ) = X(t) & Y (t) 2.5 always reg clock) / 7
11 /* * * counter2.v * * 2-bit * * */ /* reset == 0, * * i0 == 1, clk */ module counter2 (reset, clk, i0, y0, y1); // input reset, clk, i0; // output y0, y1; // // flip-flop reg r0, r1; // flip-flop (1-bit ) // Counter body /* * * */ assign y0 = r0; // assign y1 = r1; // assign /* or * * * * flip-flop */ clk or negedge reset) begin if (reset == 1 b0) begin // reset == 0 (binary, 1), r0 <= 1 b0; r1 <= 1 b0; // r0r1 = 00 else begin if (i0 == 1 b1) begin /* i0 == 1 (binary, 1), * * r1r0 = */ r0 <= ~r0; // r0 = not t0 // r1 = ((not r0) and r1) or (r0 and (not r1)) r1 <= ((~r0) & r1) (r0 & (~r1)); module 4: 2 Verilog HDL FPGA r0, r1 clk, reset, i0 y0, y1 y0, y1 Verilog HDL 8
12 st0, st1, st2, st3 2 st case?: st always assign 1 always assign Verilog HDL module counter2 counter2a, counter2b 2 counter2a "11" counter2b include counter2a, counter2b 2.8 HDL HDL 7 2 counter2 counter2 reset, clk, i0 "#" always initial 1 clk 10ns 20ns # 9
13 /* * * counter2st.v * * * * 2-bit * * */ /* reset == 0, * * i0 == 1, clk */ // define define st0 2 b00 define st1 2 b01 define st2 2 b10 define st3 2 b11 module counter2st (reset, clk, i0, y0, y1); input reset, clk, i0; // output y0, y1; // // 2-bit reg [1:0] st; // 2-bit // // Counter body /* or * * * * flip-flop */ clk or negedge reset) begin if (reset == 1 b0) begin // reset == 0 (binary, 1), // st <= st0; else begin if (i0 == 1 b1) begin /* i0 == 1 (binary, 1), * * st = st0 st1 st2 st3 st0... */ case (st) st0: begin st <= st1; st1: begin st <= st2; st2: begin st <= st3; st3: begin st <= st0; case // clk or negedge reset) begin /* * * */ // assign assign {y1, y0} = (st == st0)? 2 b00 : ( (st == st1)? 2 b01 : ( (st == st2)? 2 b10 : 2 b11)); module 5: 10
14 /* * * counter4.v * * counter2.v * * 4-bit * * */ include "counter2.v" // counter2.v module counter4 (reset, clk, i0, y); // input reset, clk, i0; // output [3:0] y; // 4-bit wire counter2b_in; // 1-bit // module counter2 (reset, clk, i0, y0, y1) counter2 counter2a(reset, clk, i0, y[0], y[1]); counter2 counter2b(reset, clk, counter2b_in, y[2], y[3]); // Counter body // wire assign assign counter2b_in = y[0] & y[1]; module /* * * test_counter2.v * * 2-bit * * */ timescale 1ns / 1ns include "counter2.v" 6: 4 // / // 1 ns = 1/ sec // counter2.v module test ; //, // counter2 flip-flop(1-bit ) reg reset, clk, i0; // flip-flop // counter2 wire( ) wire y0, y1; // 1-bit // module counter2 (reset, clk, i0, y0, y1) counter2 counter2a(reset, clk, i0, y0, y1); // 20 always begin // 10 #10 clk = ~clk; initial begin // reset, clk, i0 reset = 1; clk = 0; i0 = 0; #20 reset = 0; i0 = 0; // 20 (20 ns) #20 reset = 1; i0 = 1; // 20 (20 ns) #80 $finish; // 80 (80 ns), module 7: 2 11
15 3 EDA FPGA 3.1 EDA ICE Linux Synopsys : VHDL VSS Verilog HDL VCS VHDL/Verilog HDL DC Cadence : HDL IUS SPR SOC / IC MentorGraphics : LSI Calibre Altera : FPGA 4 3 VLSI Design and Education Center, VDEC Altera Altera University Program VDEC GB CD-ROM VDEC LSI 1 LSI Altera University Program FPGA FPGA LSI LSI Synopsys Cadence Altera EDA ICE Linux EDA /pub1/jikken/eda2 /pub1/jikken/eda/cadsetup.csh.vdec 1. ln -s /pub1/jikken/eda/cadsetup.csh.vdec ~/ 2. source ~/cadsetup.csh.vdec source 12
16 3.1.2 Synopsys Design Compiler.synopsys dc.setup Design Compiler 8.synopsys dc.setup.synopsys dc.setup 1, AND OR set designer "nakamura" set company "Nagoya-U" set target_library [list lsi_10k.db] set link_library [list lsi_10k.db] set symbol_library [list generic.sdb lsi_10k.sdb] 8:.synopsys dc.setup 3.2 Verilog-XL Verilog HDL Cadence Verilog-XL 1. verilog -c Verilog HDL Verilog HDL 2. GUI verilog +gui Verilog HDL GUI SimVision Design Browser 1 - SimVision Console - SimVision 3. (a) Design Browser 1 - SimVision Design Browser Waveform 1 - SimVision 4. (a) Console - SimVision Simulation Reinvoke Simulator... reinvoke Arguments Yes 13
17 (b) Console - SimVision Simulation Set Breakpoint Time... SimVision: Set Breakpoint Stop at exact time: OK Verilog HDL timescale (c) Console - SimVision Simulation Run 5. 4.(a), 4.(b), 4.(c) 6. Design Browser 1 - SimVision File Exit SimVision killall verilog 3.3 Design Compiler Synopsys Design Compiler 1. design vision Design Compiler GUI Design Compiler design vision Tcl(Tool Command Language) CLI(Command Line Interface) design vision CLI design vision CLI 2. File Read... read file -f verilog Verilog HDL 3. 5 EDA 4. Design Compile Design... compile 5 EDA 5. File Save as... write -hierarchy -f verilog -o sold Japanese- Language Documents 14
18 3.4 FPGA 100% FPGA Altera DE Altera DE2 9 FPGA Altera Cyclone II Altera DE2 FPGA LED 8 7 LED 1 high 0 low LED 1 0 Cyclone II PS/2 XSGA Cyclone II USB USB Device USB Host Audio CODEC Mic In, Line In, Line Out TV Video In RS-232 SD IrDA LCD 8MB SDRAM 512KB SRAM 4MB PS/2 PS/2 6-pin mini-din 5, 2 pin VCC, GND 1, 3 pin MOUSE CLK, MOUSE DATA FLEX10K MOUSE CLK MOUSE DATA DE2 XSGA XVGA 15-pin D-sub 1, 2, 3 pin RED, GREEN, BLUE 13, 14 pin HORIZ SYNC, VERT SYNC 4, 5, 9, 15 pin No Connect 6, 7, 8, 10, 11 pin GND DE2 Linux USB DE2 AC DE Altera QuartusII Altera QuartusII Altera FPGA QuartusII DE2 0. Verilog HDL DE2 FPGA.qsf PC DE2 USB PC DE2 FPGA.cdf 15
19 図 9: Altera DE2 ボード 1. コンパイル 端末上で quartus sh --flow compile プロジェクト名 とし 論理合成 FPGA マッピングを行う コンパイルにより ストリーム アウト ファイル プロ ジェクト名.sof が得られる 2. ダウンロード DE2 ボードの電源を On にした後 端末上で quartus pgm プロジェク ト名.cdf とし FPGA へのダウンロードを行う ダウンロードは quartus pgm を 実行したマシンに接続されている DE2 ボードに対して行われる quartus pgm を実 行する前に DE2 ボードが接続されていること DE2 ボードが他の人により使用中で ないことを確認すること 上記手順の 1 は DE2 ボードが接続されていないマシンで も行える FPGA 用の開発ソフトウェアに関して何か変更が生じた時は下記の URL にその情報を掲 載するので その時はここを参照すること 16
20 4 EDA 1 FPGA FPGA EDA LSI : D0, D1 1 S1 1 : Y 1 S1 0 1 D0, D1 Y Verilog HDL 4.1 Verilog HDL mux21.v test mux21.v FPGA 4.4 DE2 FPGA DE2 sw0 S1 key0, key1 D0, D1 DE2 LED Y D1 S1 D0 Y S1 D0 D Y : Verilog HDL Verilog HDL Emacs, vi 17
21 Verilog HDL Verilog HDL Verilog HDL mux21 mux21.v test mux21.v /* * * test_mux21.v * * 2-1 * * */ timescale 1ns / 1ns include "mux21.v" // / // 1 ns = 1/ sec // mux21.v module test ; //, // mux21 flip-flop(1-bit ) reg S1, D0, D1; // flip-flop // mux wire( ) wire Y; // 1-bit // module mux21 (S1, D0, D1, Y) mux21 mux21a(s1, D0, D1, Y); initial begin // S1, D0, D1 S1 = 0; D0 = 0; D1 = 0; // 20 (20 ns) #20 S1 = 0; D0 = 1; D1 = 0; // 20 (20 ns) #20 S1 = 1; D0 = 1; D1 = 0; // 20 (20 ns) #20 S1 = 0; D0 = 0; D1 = 0; // 80 (80 ns), #80 $finish; module 11: verilog +gui test mux21.v GUI 18
22 (a) Design Browser 1 - SimVision Console - SimVision (b) Design Browser 1 - SimVision Design Browser Waveform 1 - SimVision (c) Console - SimVision Simulation Reinvoke Simulator... reinvoke Arguments Yes (d) Console - SimVision Simulation Set Breakpoint Time... SimVision: Set Breakpoint Stop at exact time: OK Verilog HDL timescale (e) Console - SimVision Simulation Run Waveform 1 - SimVision (f) Design Browser 1 - SimVision File Exit SimVision killall verilog design vision 12 Design Compiler GUI design vision 12: 19
23 Tcl(Tool Command Language) CLI(Command Line Interface) 12 design vision-t> CLI design vision CLI 2. File Read... read file -f verilog mux21.v mux21.v OK 13 design vision-t> 13: mux21.v compilation completed successfully. 3. Verilog HDL (a) Select Cells Top Design Schematic New Symbol View 14 20
24 14: mux21 (b) Schematic New Design Schematic View 15 mux21 15: mux21 4. LSI 21
25 (a) Design Compile Design... compile OK OK 16: (b) 17 17: mux21 5. (a) Design Report Area... report area OK 18 (b) Timing Report Timing... report timing OK 19 22
26 18: 19: 5 EDA 23
27 File Save as... write -hierarchy -f verilog -o.v 4.4 FPGA 3.4 DE2 FPGA 1. FPGA S1, D0, D1, Y FPGA IO DE2 FPGA mux21.v mux21.qsf URL 2. quartus sh --flow compile mux21 FPGA mux21.sof 3. mux21.sof FPGA mux21.cdf URL mux21.sof 4. quartus pgm mux21.cdf FPGA 5. LED 1 0 KEY0,1 0 1 SW0 1 0 FPGA URL 24
28 5 EDA EDA : x, y 16 cin 1 : sum 16 cout 1 x + y 1. Verilog HDL Verilog HDL always 16 Verilog HDL adder16.v test adder16.v (a) 4.3 design vision adder16.v (b) report timing, report area (c) Select Paths From/Throgh/To... report timing (d) set max delay 5 -to [all outputs] 5ns (e) set max area 5 5 (f)
29 /* * * adder16.v * * 16 * * */ module adder16 (x, y, cin, sum, cout); input [15:0] x, y; input cin; output [15:0] sum; output cout; assign {cout, sum} = x + y + cin; module 20: 16 /* * * test_adder16.v * * 16 * * */ timescale 1ns / 1ns include "adder16.v" module test; reg [15:0] x, y; reg cin; wire [15:0] sum; wire cout; // / // 1 ns = 1/ sec // adder16.v adder16 adder16a(x, y, cin, sum, cout); always begin #10 x = x + 100; always begin #5 y = y + 300; initial begin x = 0 ; y = 0 ; cin = 0; module 21: 16 26
30 5.2 = : clk 1 reset 1 x, y 16 cin 1 : sum 16 cout 1 x + y Verilog HDL Verilog HDL 16 Verilog HDL adder16s.v test adder16s.v (a) 4.3 adder16s.v (b) create clock -period 5 -name clk [get ports clk] set max delay 5 -to [all outputs] set max delay 5 -to [all registers -data pins] 5ns (c) set max area 5 5 (d) 100ns create clock set max delay
31 /* * * adder16s.v * * 16 * * */ module adder16s (clk, reset, x, y, cin, sum, cout); input [15:0] x, y; input clk, reset, cin; output [15:0] sum; output cout; reg [15:0] r0, r1; assign {cout, sum} = r0 + r1 + cin; clk or negedge reset) begin if (reset == 1 b0) begin r0 <= 0 ; r1 <= 0; else begin r0 <= x; r1 <= y; module 22: 16 /* * * test_adder16s.v * * 16 * * */ timescale 1ns / 1ns include "adder16s.v" module test ; reg reset,clk, cin; reg [15:0] x, y; wire [15:0] sum; wire cout; adder16s always begin #5 clk = ~clk; always begin #8 x = x + 100; y = y + 200; // / // 1 ns = 1/ sec // adder16.v adder16sa(clk, reset, x, y, cin,sum, cout); initial begin reset = 1; clk = 0; x = 0; y = 0; cin = 0 ; #20 reset = 0; #20 reset = 1; module 23: 16 28
32 Verilog HDL 1. 1 BCD 4 BCD , BCD : clk 1 reset 1 x 1 : bcd1 out clk BCD 8 BCD , BCD : clk 1 reset 1 x 1 : bcd2 out clk URL 29
33 2 1 Verilog HDL : clk 1 reset 1 x 1 : y : URL 30
34 Verilog HDL FPGA FPGA mux21.qsf set_location_assignment PIN_N25 -to S1 set_location_assignment PIN_G26 -to D0 set_location_assignment PIN_N23 -to D1 set_location_assignment PIN_AD12 -to Y key0, key1 D0, D1 0 S1 Y LED DE2 8.2 Altera DE2 DE2.qsf set location assignment PIN N2 -to clk 50MHz Verilog HDL module divider (clk, sysreset, clkin); input clk, sysreset; output clkin; reg [23:0] cnt; clk or negedge sysreset) begin if(sysreset == 1 b0) cnt <= 0; else cnt <= cnt + 1; assign clkin = ~cnt[22]; module 31
35 assign cnt 2 n 8.3 Verilog HDL Verilog HDL /********************/ /* shifter32_8_l2.v */ /********************/ // // sh_a[31:0]-> ->sh_y[7:0] // module shifter32_8_l2 (sh_a, sh_y); // input [31:0] sh_a; // 32-bit output [7:0] sh_y; // 8-bit //Body //2-bit assign sh_y = {sh_a[5:0], 2 b00}; module /**************/ /* mux32_32_32.v */ /**************/ // // d0[31:0]-> // d1[31:0]-> ->y[31:0] // s-> // module mux32_32_32 (d0, d1, s, y); // input [31:0] d0; // 32-bit d0 input [31:0] d1; // 32-bit d1 input s; // 1-bit s output [31:0] y; // 32-bit y // Multiplexer body // if (s == 0) y = d0; else y = d1; // assign assign y = (s == 1 b0)? d0 : d1; module 32
36 CPU /******************/ /* signext16_32.v */ /******************/ // // a16[15:0]-> ->y32[31:0] // module signext16_32 (a16, y32); // input [15:0] a16; // 16-bit output [31:0] y32; // 32-bit //Body // assign y32 = {a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15], a16[15:0]}; module CPU 32 ALU /*********/ /* alu.v */ /*********/ // // alu_a[31:0]-> // alu_b[31:0]-> ->alu_y[31:0] // alu_ctrl[2:0]-> ->alu_iszero // // // lw(load word) // sw(store word) // add // sub // and // or // slt(set on less than) // beq(blanch on equal) // alu_ctrl[2:0], // 010, add // 110, sub // 000, and // 001, or // 111, slt define ADD 3 b010 33
37 define SUB 3 b110 define AND 3 b000 define OR 3 b001 define SLT 3 b111 module alu (alu_a, alu_b, alu_ctrl, alu_y, alu_iszero); // input [31:0] alu_a; // 32-bit a input [31:0] alu_b; // 32-bit b input [2:0] alu_ctrl; // 3-bit ALU output [31:0] alu_y; // 32-bit y output alu_iszero; // 1-bit iszero (y==0? 1:0) reg reg [31:0] result; iszero; or alu_b or alu_ctrl) begin case (alu_ctrl) ADD: begin result = alu_a + alu_b; SUB: begin result = alu_a - alu_b; AND: begin result = alu_a & alu_b; OR: begin result = alu_a alu_b; SLT: begin result = (alu_a < alu_b)? 32 h : 32 h ; default: begin result = 0; case or alu_b or alu_ctrl or result) begin if (result == 0) begin iszero = 1; else begin iszero = 0; assign alu_y = result; assign alu_iszero = iszero; module 34
38 CPU PC 4 /***********/ /* plus4.v */ /***********/ // // inc_a[7:0]-> ->inc_y[7:0] // module plus4 (inc_a, inc_y); // input [7:0] inc_a; // 8-bit output [7:0] inc_y; // 8-bit assign inc_y = inc_a + 4; module CPU PC /********/ /* pc.v */ /********/ // // clock-> // reset-> // pc_next[7:0]-> ->pc[7:0] // module pc (clock, reset, pc_next, pc); // input clock, reset; //, input [7:0] pc_next; // 8-bit PC output [7:0] pc; // 8-bit PC reg [7:0] pc_reg; // PC // Always : // : clock, reset, pc_next // : pc_reg // : pc_reg clock or negedge reset) begin if (reset == 1 b0) begin pc_reg <= 8 b ; else begin pc_reg <= pc_next; assign pc = pc_reg; module 35
39 CPU /***************/ /* registers.v */ /***************/ // // clock-> // reset-> // reg_read_idx1[3:0]-> // reg_read_idx2[3:0]-> ->reg_read_data1[31:0] // reg_write_idx[3:0]-> ->reg_read_data2[31:0] // reg_write_enable-> // reg_write_data[31:0]-> // module registers (clock, reset, reg_read_idx1, reg_read_idx2, reg_write_idx, reg_write_enable, reg_write_data, reg_read_data1, reg_read_data2); input clock, reset; //, input [3:0] reg_read_idx1; // 1 input [3:0] reg_read_idx2; // 2 input [3:0] reg_write_idx; // input reg_write_enable; // (1)/ (0) input [31:0] reg_write_data; // output [31:0] reg_read_data1; // 1 output [31:0] reg_read_data2; // 2 // Registers (regs_0 = 0) reg [31:0] regs_1; reg [31:0] regs_2; reg [31:0] regs_3; reg [31:0] regs_4; reg [31:0] regs_5; reg [31:0] regs_6; reg [31:0] regs_7; reg [31:0] regs_8; reg [31:0] regs_9; reg [31:0] regs_10; reg [31:0] regs_11; reg [31:0] regs_12; reg [31:0] regs_13; reg [31:0] regs_14; reg [31:0] regs_15; // // 1 regs[0] 0 // assign reg_read_data1 = regs[1 15]; // assign reg_read_data1 = (reg_read_idx1 == 4 b0000)? 0 : ( (reg_read_idx1 == 4 b0001)? regs_1 : ( (reg_read_idx1 == 4 b0010)? regs_2 : ( (reg_read_idx1 == 4 b0011)? regs_3 : ( (reg_read_idx1 == 4 b0100)? regs_4 : ( (reg_read_idx1 == 4 b0101)? regs_5 : ( (reg_read_idx1 == 4 b0110)? regs_6 : ( (reg_read_idx1 == 4 b0111)? regs_7 : ( (reg_read_idx1 == 4 b1000)? regs_8 : ( (reg_read_idx1 == 4 b1001)? regs_9 : ( 36
40 (reg_read_idx1 == 4 b1010)? regs_10 : ( (reg_read_idx1 == 4 b1011)? regs_11 : ( (reg_read_idx1 == 4 b1100)? regs_12 : ( (reg_read_idx1 == 4 b1101)? regs_13 : ( (reg_read_idx1 == 4 b1110)? regs_14 : (regs_15))))))))))))))); // // 2 regs[0] 0 // assign reg_read_data2 = regs[1 15]; // assign reg_read_data2 = (reg_read_idx2 == 5 b00000)? 0 : ( (reg_read_idx2 == 5 b00001)? regs_1 : ( (reg_read_idx2 == 5 b00010)? regs_2 : ( (reg_read_idx2 == 5 b00011)? regs_3 : ( (reg_read_idx2 == 5 b00100)? regs_4 : ( (reg_read_idx2 == 5 b00101)? regs_5 : ( (reg_read_idx2 == 5 b00110)? regs_6 : ( (reg_read_idx2 == 5 b00111)? regs_7 : ( (reg_read_idx2 == 5 b01000)? regs_8 : ( (reg_read_idx2 == 5 b01001)? regs_9 : ( (reg_read_idx2 == 5 b01010)? regs_10 : ( (reg_read_idx2 == 5 b01011)? regs_11 : ( (reg_read_idx2 == 5 b01100)? regs_12 : ( (reg_read_idx2 == 5 b01101)? regs_13 : ( (reg_read_idx2 == 5 b01110)? regs_14 : (regs_15))))))))))))))); // Always : // : clock, reset, reg_write_idx, reg_write_enable, reg_write_data // : regs_1 regs_15 // : regs_1 regs_15 clock or negedge reset) begin if (reset == 1 b0) begin regs_1 <= 0; regs_2 <= 0; regs_3 <= 0; regs_4 <= 0; regs_5 <= 0; regs_6 <= 0; regs_7 <= 0; regs_8 <= 0; regs_9 <= 0; regs_10 <= 0; regs_11 <= 0; regs_12 <= 0; regs_13 <= 0; regs_14 <= 0; regs_15 <= 0; else begin if (reg_write_enable == 1 b1) begin // // regs[0] 0 // regs[1 15] = reg_write_data; // if (reg_write_idx == 4 b0001) begin regs_1 <= reg_write_data; if (reg_write_idx == 4 b0010) begin regs_2 <= reg_write_data; if (reg_write_idx == 4 b0011) begin regs_3 <= reg_write_data; if (reg_write_idx == 4 b0100) begin regs_4 <= reg_write_data; if (reg_write_idx == 4 b0101) begin regs_5 <= reg_write_data; if (reg_write_idx == 4 b0110) begin 37
41 regs_6 <= reg_write_data; if (reg_write_idx == 4 b0111) begin regs_7 <= reg_write_data; if (reg_write_idx == 4 b1000) begin regs_8 <= reg_write_data; if (reg_write_idx == 4 b1001) begin regs_9 <= reg_write_data; if (reg_write_idx == 4 b1010) begin regs_10 <= reg_write_data; if (reg_write_idx == 4 b1011) begin regs_11 <= reg_write_data; if (reg_write_idx == 4 b1100) begin regs_12 <= reg_write_data; if (reg_write_idx == 4 b1101) begin regs_13 <= reg_write_data; if (reg_write_idx == 4 b1110) begin regs_14 <= reg_write_data; if (reg_write_idx == 4 b1111) begin regs_15 <= reg_write_data; // End: if (reg_write_enable == 1 b1) begin // End: clock or negedge reset) begin module [1] VDEC. [2] VDEC,.., [3],,,. HDL VLSI Verilog-HDL VHDL CPU., [4]. LSI., [5]. HDL., [6] James O. Hamblen and Michael D. Furman. Rapid Prototyping of Digital Systems. Kluwer Academic Publishers, [7] &,.. BP,
Verilog HDL による回路設計記述
Verilog HDL 3 2019 4 1 / 24 ( ) (RTL) (HDL) RTL HDL アルゴリズム 動作合成 論理合成 論理回路 配置 配線 ハードウェア記述言語 シミュレーション レイアウト 2 / 24 HDL VHDL: IEEE Std 1076-1987 Ada IEEE Std 1164-1991 Verilog HDL: 1984 IEEE Std 1364-1995
More informationmain.dvi
CAD 2001 12 1 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape ref0177/html/index.html.,, View Encoding Japanese
More informationVLD Kazutoshi Kobayashi
VLD Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2005 8 26-29 1, Verilog-HDL, Verilog-HDL. Verilog-HDL,, FPGA,, HDL,. 1.1, 1. (a) (b) (c) FPGA (d). 2. 10,, Verilog-HDL, FPGA,. 1.2,,,, html. % netscape
More information2.5. Verilog 19 Z= X + Y - Z A+B LD ADD SUB ST (X<<1)+(Y<<1) X 1 2 LD SL ST 2 10
2.5. Verilog 19 Z= X + Y - Z A+B LD 0 0001 0000 ADD 1 0110 0001 SUB 2 0111 0010 ST 2 1000 0010 (X
More informationuntitled
Verilog HDL Verilog HDL VerilogHDL veriloghdl / CPLD , 1bit 2 MUX 5 D,E) always) module MUX(out, a, b, sel); output out; input a, b, sel; A) IF module MUX(out, a, b, sel); output out; input a, b, sel;
More informationVHDL
VHDL 1030192 15 2 10 1 1 2 2 2.1 2 2.2 5 2.3 11 2.3.1 12 2.3.2 12 2.4 12 2.4.1 12 2.4.2 13 2.5 13 2.5.1 13 2.5.2 14 2.6 15 2.6.1 15 2.6.2 16 3 IC 17 3.1 IC 17 3.2 T T L 17 3.3 C M O S 20 3.4 21 i 3.5 21
More informationKazutoshi Kobayashi (kobayasi kit.ac.jp)
Kazutoshi Kobayashi (kobayasi kit.ac.jp) 2009 11 24-25 1 1 1.1.................................. 1 1.2,............................ 1 2 2 2.1 FPGA.................... 2 2.2 Verilog-HDL........................
More information, FPGA Verilog-HDL
Kazutoshi Kobayashi (kobayasi@kuee.kyoto-u.ac.jp) 2007 12 19-20 1 1 1.1...................................... 1 1.2,................................. 1 2 2 2.1 FPGA......................... 2 2.2 Verilog-HDL.............................
More information? FPGA FPGA FPGA : : : ? ( ) (FFT) ( ) (Localization) ? : 0. 1 2 3 0. 4 5 6 7 3 8 6 1 5 4 9 2 0. 0 5 6 0 8 8 ( ) ? : LU Ax = b LU : Ax = 211 410 221 x 1 x 2 x 3 = 1 0 0 21 1 2 1 0 0 1 2 x = LUx = b 1 31
More informationuntitled
13 Verilog HDL 16 CPU CPU IP 16 1023 2 reg[ msb: lsb] [ ]; reg [15:0] MEM [0:1023]; //16 1024 16 1 16 2 FF 1 address 8 64 `resetall `timescale 1ns/10ps module mem8(address, readdata,writedata, write, read);
More information1, Verilog-HDL, Verilog-HDL Verilog-HDL,, FPGA,, HDL, 11, 1 (a) (b) (c) FPGA (d) 2 10,, Verilog-HDL, FPGA, 12,,,, html % netscape file://home/users11/
1 Kazutoshi Kobayashi kobayasi@ieeeorg 2002 12 10-11 1, Verilog-HDL, Verilog-HDL Verilog-HDL,, FPGA,, HDL, 11, 1 (a) (b) (c) FPGA (d) 2 10,, Verilog-HDL, FPGA, 12,,,, html % netscape file://home/users11/kobayasi/kobayasi/refresh/indexhtml,,
More information論理設計の基礎
. ( ) IC (Programmable Logic Device, PLD) VHDL 2. IC PLD 2.. PLD PLD PLD SIC PLD PLD CPLD(Complex PLD) FPG(Field Programmable Gate rray) 2.2. PLD PLD PLD I/O I/O : PLD D PLD Cp D / Q 3. VHDL 3.. HDL (Hardware
More informationNios II 簡易チュートリアル
Nios II Ver. 7.1 2007 10 1. Nios II Nios II JTAG UART LED 8 PIO LED < > Quartus II SOPC Builder Nios II Quartus II.sof Nios II IDE Stratix II 2S60 RoHS Nios II Quartus II http://www.altera.com/literature/lit-nio2.jsp
More informationDesign at a higher level
Meropa FAST 97 98 10 HLS, Mapping, Timing, HDL, GUI, Chip design Cadence, Synopsys, Sente, Triquest Ericsson, LSI Logic 1980 RTL RTL gates Applicability of design methodologies given constant size of
More informationPLDとFPGA
PLDFPGA 2002/12 PLDFPGA PLD:Programmable Logic Device FPGA:Field Programmable Gate Array Field: Gate Array: LSI MPGA:Mask Programmable Gate Array» FPGA:»» 2 FPGA FPGALSI FPGA FPGA Altera, Xilinx FPGA DVD
More information計数工学実験/システム情報工学実験第一 「ディジタル回路の基礎」
計数工学実験 / システム情報工学実験第一 ディジタル回路の基礎 ( 全 3 回 ) システム 8 研 三輪忍 参考資料 五島正裕 : ディジタル回路 ( 科目コード 400060) 講義資料 ( ググれば出てくる ) 高木直史 : 論理回路, 昭晃堂 Altera: Cyclone II FPGA スターター開発ボードリファレンス マニュアル Altera: Introduction to Quartus
More information1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i
1030195 15 2 10 1 1 2 2 2-1 2 2-2 4 2-3 11 2-4 12 2-5 14 3 16 3-1 16 3-2 18 3-3 22 4 35 4-1 VHDL 35 4-2 VHDL 37 4-3 VHDL 37 4-3-1 37 4-3-2 42 i 4-3-3 47 5 52 53 54 55 ii 1 VHDL IC VHDL 5 2 3 IC 4 5 1 2
More informationNios II ハードウェア・チュートリアル
Nios II ver. 7.1 2007 8 1. Nios II FPGA Nios II Quaruts II 7.1 Nios II 7.1 Nios II Cyclone II count_binary 2. 2-1. http://www.altera.com/literature/lit-nio2.jsp 2-2. Nios II Quartus II FEATURE Nios II
More informationスライド 1
isplever CLASIC 1.2 Startup Manual for MACH4000 Rev.1.0 isplever_ CLASIC Startup_for_MACH4000_Rev01.ppt Page: 1 1. Page 3 2. Lattice isplever Design Flow Page 4 3. Page 5 3-1 Page 6 3-2 Page 7 3-3 Page
More information「FPGAを用いたプロセッサ検証システムの製作」
FPGA 2210010149-5 2005 2 21 RISC Verilog-HDL FPGA (celoxica RC100 ) LSI LSI HDL CAD HDL 3 HDL FPGA MPU i 1. 1 2. 3 2.1 HDL FPGA 3 2.2 5 2.3 6 2.3.1 FPGA 6 2.3.2 Flash Memory 6 2.3.3 Flash Memory 7 2.3.4
More informationスライド 1
1 1. 2 2. 3 isplever 4 5 6 7 8 9 VHDL 10 VHDL 4 Decode cnt = "1010" High Low DOUT CLK 25MHz 50MHz clk_inst Cnt[3:0] RST 2 4 1010 11 library ieee; library xp; use xp.components.all; use ieee.std_logic_1164.all;
More informationDELPHINUS EQUULEUS 2019 NASA SLS FPGA ( ) DELPHINUS 2
30 1631158 1 29 () 1 DELPHINUS EQUULEUS 2019 NASA SLS FPGA ( 0.010.1 ) DELPHINUS 2 1 4 1.1............................................ 4 1.2 (Lunar Impact Flush)............................. 4 1.3..............................................
More informationif clear = 1 then Q <= " "; elsif we = 1 then Q <= D; end rtl; regs.vhdl clk 0 1 rst clear we Write Enable we 1 we 0 if clk 1 Q if rst =
VHDL 2 1 VHDL 1 VHDL FPGA VHDL 2 HDL VHDL 2.1 D 1 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; regs.vhdl entity regs is clk, rst : in std_logic; clear : in std_logic; we
More informationTULを用いたVisual ScalerとTDCの開発
TUL を用いた Visual Scaler と TDC の開発 2009/3/23 原子核物理 4 年 永尾翔 目次 目的と内容 開発環境 J-Lab におけるハイパー核分光 Visual Scaler TDC まとめ & 今後 目的と内容 目的 TUL, QuartusⅡ を用いて実験におけるトリガーを組めるようになる Digital Logic を組んでみる 内容 特徴 TUL,QuartusⅡ
More informationHardCopy IIデバイスのタイミング制約
7. HardCopy II H51028-2.1 Stratix II FPGA FPGA ASIC HardCopy II ASIC NRE Quartus II HardCopy Design Center HCDC Quartus II TimeQuest HardCopy II 2 DR2 TimeQuest TimeQuest FPGA ASIC FPGA ASIC Quartus II
More informationディジタル電子回路 設計演習課題
Arch 研究室スキルアップ講座 NEXYS4 による 24 時間時計 仕様書および設計例 1 実験ボード (NEXYS4) 外観 ダウンロード (USB) ケーブル接続端子 FPGA:Xilinx 社製 Artix7 XC7A100T-CSG324 7 セグメント LED8 個 LED16 個 リセット SW スライドスイッチ (16 個 ) 押しボタンスイッチ (5 個 ) 2 実験ボードブロック図
More informationMicrosoft PowerPoint - Lec pptx
Course number: CSC.T34 コンピュータ論理設計 Computer Logic Design 5. リコンフィギャラブルシステム Reconfigurable Systems 吉瀬謙二情報工学系 Kenji Kise, Department of Computer Science kise _at_ c.titech.ac.jp www.arch.cs.titech.ac.jp/lecture/cld/
More informationstarc_verilog_hdl pptx
!!!!!!! ! 2.10.6.! RTL : 1! 1 2! 3.2.5.! : ! 1.7. FPGA 1 FPGA FPGA 1.5.2! 3.1.2.! 3! 3.3.1. DFT! LSI :! 2 : ! ON FPGA!!! FPGA! FPGA! !!!!! ! Verilog HDL 6 9 4! Xilinx ISE!!! RTL! CPU !! 20!! C! VHDL! Xilinx
More informationVelilogHDL 回路を「言語」で記述する
2. ソースを書く 数値表現 数値表現形式 : ss'fnn...n ss は, 定数のビット幅を 10 進数で表します f は, 基数を表します b が 2 進,o が 8 進,d が 10 進,h が 16 進 nn...n は, 定数値を表します 各基数で許される値を書くこ Verilog ビット幅 基数 2 進表現 1'b0 1 2 進 0 4'b0100 4 2 進 0100 4'd4 4
More information1. 3 1.1.....3 1.2... 3 1.3... 5 2. 6 3. 8 4. Beryll 9 4.1... 9 4.2... 9 4.3... 10 4.4... 10 5. Beryll 14 5.1 Cyclone V GX FPGA... 14 5.2 FPGA ROM...
Mpression Beryll Board Revision 1.0 2014/2 2014/2 Mpression by Macnica Group http://www.m-pression.com 1. 3 1.1.....3 1.2... 3 1.3... 5 2. 6 3. 8 4. Beryll 9 4.1... 9 4.2... 9 4.3... 10 4.4... 10 5. Beryll
More informationCyclone IIIデバイスのI/O機能
7. Cyclone III I/O CIII51003-1.0 2 Cyclone III I/O 1 I/O 1 I/O Cyclone III I/O FPGA I/O I/O On-Chip Termination OCT Quartus II I/O Cyclone III I/O Cyclone III LAB I/O IOE I/O I/O IOE I/O 5 Cyclone III
More informationQuartus II はじめてガイド - EDA ツールの設定方法
ALTIMA Corp. Quartus II はじめてガイド EDA ツールの設定方法 ver.14 2015 年 4 月 Rev.1.1 ELSENA,Inc. Quartus II はじめてガイド EDA ツールの設定方法 目次 1. 2. 3. はじめに...3 サポート環境...4 操作方法...5 3-1. 3-2. 論理合成ツールとのインタフェース設定... 5 シミュレーション ツールとのインタフェース設定...
More information26 FPGA 11 05340 1 FPGA (Field Programmable Gate Array) ASIC (Application Specific Integrated Circuit) FPGA FPGA FPGA FPGA Linux FreeDOS skewed way L1
FPGA 272 11 05340 26 FPGA 11 05340 1 FPGA (Field Programmable Gate Array) ASIC (Application Specific Integrated Circuit) FPGA FPGA FPGA FPGA Linux FreeDOS skewed way L1 FPGA skewed L2 FPGA skewed Linux
More informationネットリストおよびフィジカル・シンセシスの最適化
11. QII52007-7.1.0 Quartus II Quartus II atom atom Electronic Design Interchange Format (.edf) Verilog Quartus (.vqm) Quartus II Quartus II Quartus II Quartus II 1 Quartus II Quartus II 11 3 11 12 Altera
More information2014.3.10 @stu.hirosaki-u.ac.jp 1 1 1.1 2 3 ( 1) x ( ) 0 1 ( 2)NOT 0 NOT 1 1 NOT 0 ( 3)AND 1 AND 1 3 AND 0 ( 4)OR 0 OR 0 3 OR 1 0 1 x NOT x x AND x x OR x + 1 1 0 x x 1 x 0 x 0 x 1 1.2 n ( ) 1 ( ) n x
More informationLab GPIO_35 GPIO
6,GPIO, PSoC 3/5 GPIO HW Polling and Interrupt PSoC Experiment Lab PSoC 3/5 GPIO Experiment Course Material 6 V2.02 October 15th. 2012 GPIO_35.PPT (65 Slides) Renji Mikami Renji_Mikami@nifty.com Lab GPIO_35
More information(Making the electronic circuit with use of micro-processor)
(Making the electronic circuit with use of micro-processor) 1055083 1 1 2 3 4 2L T = Vs T = 1 34000 2 = 58.824 5 4069 9V R1 1k Q1 NPN R2 1k
More informationCleaner XL 1.5 クイックインストールガイド
Autodesk Cleaner XL 1.5 Contents Cleaner XL 1.5 2 1. Cleaner XL 3 2. Cleaner XL 9 3. Cleaner XL 12 4. Cleaner XL 16 5. 32 2 1. Cleaner XL 1. Cleaner XL Cleaner XL Administrators Cleaner XL Windows Media
More informationシステムオンチップ技術
(SoC) 2004/6/11 Yukihiro Nakamura e-mail: nakamura@kuee.kyoto-u.ac.jp u.ac.jp (VLSI) () VLSI DIPS IBM370 CPU MH MB GB DIPS-11201975 VAIO LSI Sony VAIO CPU MH MB GB Pentium () () V,S.,B Sun Micro
More informationPeakVHDL Max+Plus VGA VG
2001 PC 9720002 14 2 7 4 1 5 1.1... 5 1.2... 5 1.3... 6 1.4... 6 2 7 2.1... 7 2.2... 8 2.2.1... 8 2.3... 9 2.3.1 PeakVHDL... 9 2.3.2 Max+Plus2... 9 3 VGA 10 3.1... 10 3.2 VGA... 10 3.3 VGA... 11 3.4 VGA...
More informationquattro.PDF
Quattro USB Audio Interface 2 M-AUDIO 3 Windows Windows 98 SE/ Windows ME/ Windows 2000/ Windows XP Platinum III 500MHz/ 96kHz Platinum II 400MKz/ 48kHz 128MB RAM / 96kHz 64MB RAM/ 48kHz Macintosh USB
More informationIntroduction Purpose This training course demonstrates the use of the High-performance Embedded Workshop (HEW), a key tool for developing software for
Introduction Purpose This training course demonstrates the use of the High-performance Embedded Workshop (HEW), a key tool for developing software for embedded systems that use microcontrollers (MCUs)
More informationArduino UNO IS Report No. Report Medical Information System Laboratory
Arduino UNO 2015 2 25 IS Report No. Report Medical Information System Laboratory Abstract ( ) Arduino / Arduino Bluetooth Bluetooth : Arduino Arduino UNO Arduino IDE micro computer LED 1............................
More informationFPGAメモリおよび定数のインシステム・アップデート
QII53012-7.2.0 15. FPGA FPGA Quartus II Joint Test Action Group JTAG FPGA FPGA FPGA Quartus II In-System Memory Content Editor FPGA 15 2 15 3 15 3 15 4 In-System Memory Content Editor Quartus II In-System
More information1: ITT-2 DDR2 1.8V,.V(F) Config. Mem. JTAG XCFPV048 LEDs SWs Clock (VariClock) DDR2 DDR2 DDR2 FPGA XC5VFX0T General-Purpose LEDs SWs XTAL (2.68kHz) MC
2009 ZEAL-C01 1 ZEAL ZEAL-C01 2 ITT-2 2 [1] 2 ITT-2 Bluetooth ZEAL-C01 ZEAL-S01 ITT-2 ZEAL IC FPGA (Field Programmable Gate Array) MCU (Microcontroller Unit) FPGA Xilinx Virtex-5 (XC5VFX0T) MCU Texas Instruments
More informationmain.dvi
20 II 7. 1 409, 3255 e-mail: namba@faculty.chiba-u.jp 2 1 1 1 4 2 203 2 1 1 1 5 503 1 3 1 2 2 Web http://www.icsd2.tj.chiba-u.jp/~namba/lecture/ 1 2 1 5 501 1,, \,", 2000 7. : 1 1 CPU CPU 1 Intel Pentium
More information( ) : 1997
( ) 2008 2 17 : 1997 CMOS FET AD-DA All Rights Reserved (c) Yoichi OKABE 2000-present. [ HTML ] [ PDF ] [ ] [ Web ] [ ] [ HTML ] [ PDF ] 1 1 4 1.1..................................... 4 1.2..................................
More informationQuartus II はじめてガイド - EDA ツールの設定方法
ALTIMA Corp. Quartus II はじめてガイド EDA ツールの設定方法 ver.10.0 2010 年 12 月 ELSENA,Inc. Quartus II はじめてガイド EDA ツールの設定方法 目次 1. はじめに... 3 2. サポート環境... 3 3. 操作方法... 4 3-1. 論理合成ツールとのインタフェース設定... 4 3-2. シミュレータ ツールとのインタフェース設定...
More informationデザインパフォーマンス向上のためのHDLコーディング法
WP231 (1.1) 2006 1 6 HDL FPGA TL TL 100MHz 400MHz HDL FPGA FPGA 2005 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
More informationプロセッサ・アーキテクチャ
2. NII51002-8.0.0 Nios II Nios II Nios II 2-3 2-4 2-4 2-6 2-7 2-9 I/O 2-18 JTAG Nios II ISA ISA Nios II Nios II Nios II 2 1 Nios II Altera Corporation 2 1 2 1. Nios II Nios II Processor Core JTAG interface
More informationMicrosoft PowerPoint - FPGA
PLD と FPGA VLD 講習会 京都大学小林和淑 1 PLD FPGA って何 PLD: Programmable Logic Device プログラム可能な論理素子 FPGA: Field Programmable Gate Array 野外でプログラム可能な門の隊列? Field: 設計現場 Gate Array: 論理ゲートをアレイ上に敷き詰めたLSI MPGA: Mask Programmable
More information3 SIMPLE ver 3.2: SIMPLE (SIxteen-bit MicroProcessor for Laboratory Experiment) 1 16 SIMPLE SIMPLE 2 SIMPLE 2.1 SIMPLE (main memo
3 SIMPLE ver 3.2: 20190404 1 3 SIMPLE (SIxteen-bit MicroProcessor for Laboratory Experiment) 1 16 SIMPLE SIMPLE 2 SIMPLE 2.1 SIMPLE 1 16 16 (main memory) 16 64KW a (C )*(a) (register) 8 r[0], r[1],...,
More informationChip PlannerによるECO
13. Chip Planner ECO QII52017-8.0.0 ECO Engineering Change Orders Chip Planner ECO Chip Planner FPGA LAB LE ALM ECO ECO ECO ECO Chip Planner Chip Planner ECO LogicLock Chip Planner Quartus II Volume 2
More information電卓の設計 1
電卓の設計 1 FPGA Express と MAXPLUS2 に よる FPGA 設計 FPGA EXPRESS RTL circuit.edf circuit.acf RTL MAXPLUS2 FPGA circuit.acf circuit.sof, ttf, pof SRAM 2 どうして電卓なの? その場で 10 キーを使って動かせる プロセッサだと プログラムを考えたり メモリとのインタフェースが必要
More informationModelSim-Altera - RTL シミュレーションの方法
ALTIMA Corp. ModelSim-Altera RTL シミュレーションの方法 ver.15.1 2016 年 5 月 Rev.1 ELSENA,Inc. 目次 1. 2. 3. はじめに...3 RTL シミュレーションの手順...4 RTL シミュレーションの実施...5 3-1. 3-2. 新規プロジェクトの作成... 5 ファイルの作成と登録... 7 3-2-1. 新規ファイルの作成...
More informationR1EV5801MBシリーズ データシート
1M EEPROM (128-kword 8-bit) Ready/Busy and function R10DS0209JJ0100 Rev.1.00 131072 8 EEPROM ROM MONOS CMOS 128 2.7V 5.5V 150ns (max) @ Vcc=4.5V 5.5V 250ns(max) @ Vcc=2.7V 5.5V 20mW/MHz (typ) 110µW (max)
More informationMicrosoft Word - TY_WLAN_WBSBMVGXB-1_EVBManual_V1.3J_ doc
ワイヤレス LAN & Bluetooth モジュール評価ボード ( for WYSBMVGX4 / WYSBMVGX4-I / WYSBMVGXB ) この評価ボードは 実験検証用であり 品質を保証するものではありません また 評価ボードに使用している回路や部品 ソフトウェアは最新の物ではないことがあります 1/16 注意 : このモジュールは 日本の輸出管理下にあるデバイスドライバが必要です お客様の国やアプリケーション
More informationXC9500 ISP CPLD JTAG Port 3 JTAG Controller In-System Programming Controller 8 36 Function Block Macrocells to 8 /GCK /GSR /GTS 3 2 or 4 Blocks FastCO
- 5ns - f CNT 25MHz - 800~6,400 36~288 5V ISP - 0,000 / - / 36V8-90 8 - IEEE 49. JTAG 24mA 3.3V 5V PCI -5-7 -0 CMOS 5V FastFLASH XC9500 XC9500CPLD 0,000 / IEEE49. JTAG XC9500 36 288 800 6,400 2 XC9500
More informationUnconventional HDL Programming ( version) 1
Unconventional HDL Programming (20090425 version) 1 1 Introduction HDL HDL Hadware Description Language printf printf (C ) HDL 1 HDL HDL HDL HDL HDL HDL 1 2 2 2.1 VHDL 1 library ieee; 2 use ieee.std_logic_1164.all;
More information.,. 0. (MSB). =2, =1/2.,. MSB LSB, LSB MSB. MSB 0 LSB 0 0 P
, 0 (MSB) =2, =1/2, MSB LSB, LSB MSB MSB 0 LSB 0 0 P61 231 1 (100, 100 3 ) 2 10 0 1 1 0 0 1 0 0 100 (64+32+4) 2 10 100 2 5, ( ), & 3 (hardware), (software) (firmware), hardware, software 4 wired logic
More informationStratix IIIデバイスの外部メモリ・インタフェース
8. Stratix III SIII51008-1.1 Stratix III I/O R3 SRAM R2 SRAM R SRAM RII+ SRAM RII SRAM RLRAM II 400 MHz R Stratix III I/O On-Chip Termination OCT / HR 4 36 R ouble ata RateStratix III FPGA Stratix III
More information1
Ver.1.04 Reference Document For LCD Module Product No Documenet No 1B3GB02 SPC1B3GB02V104 Version Ver.1.04 REPRO ELECTRONICS CORPORATION Maruwa Building 2F,2-2-19 Sotokanda,Chiyoda-ku,Tokyo 1001-0021 Japan
More informationHN58V256Aシリーズ/HN58V257Aシリーズ データシート
HN58V256A HN58V257A 256k EEPROM (32-kword 8-bit) Ready/Busy and RES function (HN58V257A) RJJ03C0132-0600 Rev. 6.00 2007. 05. 24 HN58V256A HN58V257A 32768 8 EEPROM ROM MNOS CMOS 64 3V 2.7 5.5V 120ns (max)
More informationLSI LSI 2
LSI LSI 2 P=CV 2 F 3 4 5 EDA Electric Design Automation) LSI CAD Computer Aided Design) Verilog Verify Logic VHDL VHSIC Description Language) SystemC C SFL Structured Functional description Language) NTT
More informationHN58C256A シリーズ/HN58C257A シリーズ データシート
HN58C256A HN58C257A 256k EEPROM (32-kword 8-bit) Ready/Busy and RES function (HN58C257A) RJJ03C0133-0600Z Rev. 6.00 2006. 10. 26 HN58C256A HN58C257A 32768 8 EEPROM ROM MNOS CMOS 64 5V±10% 85ns/100ns (max)
More information1
DVC512/DVC512GOLD 日本語取扱説明書 1 3 3 3 USB/DMX 4 6 6 SETUP 7 8 9 9 10 11 11 12 12 12 13 13 14 15 AUTO/LTP/HTP 16 17 17 18 19 19 Scene Audio BPM Sync 20 Audio BPM Sync21 21 22 22 23 24 Tricks & Tips25 3 XLR
More information組込みシステムシンポジウム2011 Embedded Systems Symposium 2011 ESS /10/20 FPGA Android Android Java FPGA Java FPGA Dalvik VM Intel Atom FPGA PCI Express DM
Android Android Java Java Dalvik VM Intel Atom PCI Express DMA 1.25 Gbps Atom Android Java Acceleration with an Accelerator in an Android Mobile Terminal Keisuke Koike, Atsushi Ohta, Kohta Ohshima, Kaori
More information1 osana@eee.u-ryukyu.ac.jp : FPGA : HDL, Xilinx Vivado + Digilent Nexys4 (Artix-7 100T) LSI / PC clock accurate / Artix-7 XC7A100T Kintex-7 XC7K325T : CAD Hands-on: HDL (Verilog) CAD (Vivado HLx) : 28y4
More informationQuartus IIネットリスト・ビューワによるデザインの解析
12. Quartus II QII51013-6.0.0 FPGA Quartus II RTL Viewer State Machine Viewer Technology Map Viewer : Quartus II Quartus II 12 46 State Machine Viewer HDL : Quartus II RTL Viewer State Machine Viewer Technology
More informationHardCopy IIIデバイスの外部メモリ・インタフェース
7. HardCopy III HIII51007-1.0 Stratix III I/O HardCopy III I/O R3 R2 R SRAM RII+ RII SRAM RLRAM II R HardCopy III Stratix III LL elay- Locked Loop PLL Phase-Locked Loop On-Chip Termination HR 4 36 HardCopy
More informationmatrox0
Image processing products Hardware/Software Software Hardware INDEX 4 3 2 12 13 15 18 14 11 10 21 26 20 9 8 7 6 5 Hardware 2 MatroxRadient 3 MatroxSolios MatroxMorphis MatroxVio 10 MatroxOrionHD 11 MatroxConcord
More informationMicrosoft PowerPoint - Chap1 [Compatibility Mode]
ディジタル設計 (A1) (Chap. 1) @ F301 http://www.ngc.is.ritsumei.ac.jp/~ger/lectures/digital2012/index.html 情報システム学科次世代コンピューティング研究室山下茂 ger@cs.ritsumei.ac.jp 0 目次 1. デジタル回路設計に関する概要の確認 基本的な用語 LSI 設計の流れ LSIの種類 現代用語の基礎知識ともいえます!
More informationNios® II HAL API を使用したソフトウェア・サンプル集 「Modular Scatter-Gather DMA Core」
ALTIMA Company, MACNICA, Inc Nios II HAL API Modular Scatter-Gather DMA Core Ver.17.1 2018 8 Rev.1 Nios II HAL API Modular Scatter-Gather DMA Core...3...3...4... 4... 5 3-2-1. msgdma... 6 3-2-2. On-Chip
More informationMicrosoft PowerPoint - Lec pptx
Course number: CSC.T341 コンピュータ論理設計 Computer Logic Design 10. シングルサイクルプロセッサのデータパス Datapath for Single Cycle Processor 吉瀬謙二情報工学系 Kenji Kise, Department of Computer Science kise _at_ c.titech.ac.jp www.arch.cs.titech.ac.jp/lecture/cld/
More informationIEEE (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices
4. Stratix II Stratix II GX IEEE 49. (JTAG) SII529-3. PCB PCB Bed-of-nails PCB 98 Joint Test Action Group (JTAG) IEEE Std. 49. (BST) PCB BST 4-4-. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin
More information2
WV-CW960 2 3 4 5 6 7 8 9 10 11 SW1 S TA RT RS485Setting SW2 DIP SW1 ON 1 2 3 4 5 6 7 8 ON 1 2 3 4 DIP SW2 12 13 q w q e 14 15 16 17 18 19 ** RS485 SETUP ** UNIT NUMBER SUB ADDRESS BAUD RATE DATA BIT PARITY
More informationMicrosoft PowerPoint - 01-VerilogSetup-2018.pptx
2018 年 4 月 13 日ハードウエア設計論 :2 ハードウエアにおける設計表現 ハードウエア設計記述言語 VerilogHDL ~ 状態遷移と順序機械 ~ TA2 名 : 古賀 杉山が担当します Ubuntu を起動し verilog が実行できる状態にしておいてください http://www.mos.t.u-tokyo.ac.jp/~ikeda/hwdesign/ 38 VerilogHDL
More informationVersion1.5
Version1.5 Version Date Version1.0 Version1.1 Version1.2 Version1.3 Version1.4 Version1.5 Test J/K/SE0_NAK USB-IF Test Procedure FS Upstream Signal Quality Test Receiver Sensitivity Test DG2040 Packet
More informationMAX IIデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト
3. MAX II IEEE 49. JTAG MII54-.6 PCB PCB Bed-of-nails PCB 98 Joint Test Action Group JTAG IEEE Std. 49. BST PCB BST 3 3. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin Signal Serial Data Out Core
More informationMINI2440マニュアル
ARM7TDMI/LPC2388 http://www.csun.co.jp info@csun.co.jp 2009/3/17 copyright@2009 http://www.csun.co.jp info@csun.co.jp 1 ARM7TDMI/LPC2388...4...5 2.1...5 2.2 USB...6 2.3 USB...7 2.4 USB OTG...7 2.5...8
More informationTK-S686_S686WP
TK-S686 TK-S686WP TK-S686 TK-S686WP LST0659-00B 2 ( ) T A 3 4 g g I _I I _I _ I_ I 5 A A B A B 6 7 A B C D E I H G F J K L N M A _ _ A B C J A K 8 D A B C D E A F O G A H S O R R P Q T I J A T A K A L
More information26102 (1/2) LSISoC: (1) (*) (*) GPU SIMD MIMD FPGA DES, AES (2/2) (2) FPGA(8bit) (ISS: Instruction Set Simulator) (3) (4) LSI ECU110100ECU1 ECU ECU ECU ECU FPGA ECU main() { int i, j, k for { } 1 GP-GPU
More informationArria GXデバイスのIEEE (JTAG)バウンダリ・スキャン・テスト
3. Arria GX IEEE 49. (JTAG) AGX523-. PCB PCB Bed-of-nails PCB 98 Joint Test Action Group (JTAG) IEEE Std. 49. (BST) PCB BST 3 3. IEEE Std. 49. Serial Data In Boundary-Scan Cell IC Pin Signal Serial Data
More informationDRAM SRAM SDRAM (Synchronous DRAM) DDR SDRAM (Double Data Rate SDRAM) DRAM 4 C Wikipedia 1.8 SRAM DRAM DRAM SRAM DRAM SRAM (256M 1G bit) (32 64M bit)
2016.4.1 II ( ) 1 1.1 DRAM RAM DRAM DRAM SRAM RAM SRAM SRAM SRAM SRAM DRAM SRAM SRAM DRAM SRAM 1.2 (DRAM, Dynamic RAM) (SRAM, Static RAM) (RAM Random Access Memory ) DRAM 1 1 1 1 SRAM 4 1 2 DRAM 4 DRAM
More informationXilinx XAPP485 Spartan-3E FPGA における最大レート 666Mbps でのデシリアライズ、アプリケーション ノート
XAPP485 (v1.1) 2006 11 10 R : Spartan-3E FPGA Spartan-3E FPGA 666Mbps 1:7 : Nick Sawyer (v1.1) Spartan -3E 666 / (Mbps) 1:7 Spartan-3E 4 5 666Mbps 1/7 Spartan-3E FPGA DCM ( ) DFS ( ) 3.5 DDR ( ) 1:7 DDR
More informationディジタル回路 第1回 ガイダンス、CMOSの基本回路
POCO の 1 サイクルマイクロアーキテクチャ POCO は 作りながら学ぶコンピュータアーキテクチャ ( 倍風館 ) で使っている教育用の 16 ビット RISC である www.am.ics.keio.ac.jp/parthenon/pocobook/ も参照のこと POCO の構成 1 + + ext func[2:0] 2:0 THB ADD 00 01 10 comsel com S A
More informationunitech PA500 Enterprise PDA Rev. A
unitech PA500 Enterprise PDA Rev. A PA500 Enterprise PDA Unitech Copyright 2007 unitech Electronics Co., Ltd. Web : http:\\www.unitech-japan.co.jp Bluetooth Bluetooth SIG Microsoft Windows ActiveSync
More informationSystemC言語概論
SystemC CPU S/W 2004/01/29 4 SystemC 1 SystemC 2.0.1 CPU S/W 3 ISS SystemC Co-Simulation 2004/01/29 4 SystemC 2 ISS SystemC Co-Simulation GenericCPU_Base ( ) GenericCPU_ISS GenericCPU_Prog GenericCPU_CoSim
More informationVLSI工学
2008//5/ () 2008//5/ () 2 () http://ssc.pe.titech.ac.jp 2008//5/ () 3!! A (WCDMA/GSM) DD DoCoMo 905iP905i 2008//5/ () 4 minisd P900i SemiConsult SDRAM, MPEG4 UIMIrDA LCD/ AF ADC/DAC IC CCD C-CPUA-CPU DSPSRAM
More informationテストコスト抑制のための技術課題-DFTとATEの観点から
2 -at -talk -talk -drop 3 4 5 6 7 Year of Production 2003 2004 2005 2006 2007 2008 Embedded Cores Standardization of core Standard format Standard format Standard format Extension to Extension to test
More informationi
i ii 2 1 JIS 2 [] NC [] 3 [] 4 5 [] 6 7 8 1900 9 10 11 12 13 14 () 15 16 17 () 18 8 19 20 A A.1 A.2 1 A.4 3 A.3 2 A.5 4 21 A.6 5 A.9 8 A.7 6 A.10 9 A.8 7 A.11 10 22 A 氏 の 手 のひらの 表 面 温 度 温 度 ( ) 37 36 35
More informationMicrosoft PowerPoint - 集積回路工学_ ppt[読み取り専用]
2007.11.12 集積回路工学 Matsuzawa Lab 1 集積回路工学 東京工業大学 大学院理工学研究科 電子物理工学専攻 2007.11.12 集積回路工学 Matsuzawa Lab 2 1. 1. ハードウェア記述言語 (VHDL で回路を設計 ) HDL 設計の手順や基本用語を学ぶ RTL とは? Register Transfer Level レジスタ間の転送関係を表現したレベル慣例的に以下のことを行う
More information2 (4)-7
2 (4)-7 (4)-7 3 4 p r f > 5 6 7 8 9 10 11 r q!1 o!0!2!3!4!5 w e t y u i!6!7 q w e r t y 12 u i o!0!1!7!2!3!4!5 p r f >!6!7 13 !8!8!9!9 @0 @0 14 @1 @2 @3 @4 @5 @6 @7 @8 @9 @1 @2 @3 @5 @6 @7 @8 @9 @4 15
More information2
WV-CW970 2 3 4 5 6 7 8 9 10 11 12 DIP SW1 ON 1 2 3 4 5 6 7 8 ON 1 2 3 4 DIP SW2 SW1 S TA RT RS485Setting SW2 13 14 q w q e 15 16 17 18 19 20 ** RS485 SETUP ** UNIT NUMBER SUB ADDRESS BAUD RATE DATA BIT
More informationRT300/140/105シリーズ 取扱説明書
REMOTE & BROADBAND ROUTER RT300i/RT140p/RT140f/RT140i RT140e/RT105p/RT105i/RT105e 2 3 4 5 6 7 8 9 10 Bold face Enter Ctrl Tab BS Del Console RT105i RT300i RT140p RT140f RT140i RT140e RT105p RT105i RT105e
More informationユーザーズマニュアル(SVCEシリーズ)
SV-NET CONTROLLER SVCE SV-NET Controller SVCE SV-NET Controller Ether SV-NET SVCE Ethernet EtherCAT EtherCAT SVCE SVCE SVC SVD SVCC SVCE TMasM TMc TMoS OS C SV-NET SV-NET AC SV-NET Controller Compact
More informationB1 Ver ( ), SPICE.,,,,. * : student : jikken. [ ] ( TarouOsaka). (, ) 1 SPICE ( SPICE. *1 OrCAD
B1 er. 3.05 (2019.03.27), SPICE.,,,,. * 1 1. 1. 1 1.. 2. : student : jikken. [ ] ( TarouOsaka). (, ) 1 SPICE ( SPICE. *1 OrCAD https://www.orcad.com/jp/resources/orcad-downloads.. 1 2. SPICE 1. SPICE Windows
More information2
WV-CS570 2 3 4 5 6 7 8 9 10 11 12 13 q w q e 14 1 2 15 3 4 5 16 6 7 8 9 17 1 2 3 18 19 1 2 * RS485 SET UP * UNIT NUMBER SUB ADDRESS BAUD RATE DATA BIT PARITY CHECK STOP BIT X/X WAIT TIME ALARM DATA DELAY
More informationA Responsive Processor for Parallel/Distributed Real-time Processing
E-mail: yamasaki@{ics.keio.ac.jp, etl.go.jp} http://www.ny.ics.keio.ac.jp etc. CPU) I/O I/O or Home Automation, Factory Automation, (SPARC) (SDRAM I/F, DMAC, PCI, USB, Timers/Counters, SIO, PIO, )
More informationMicrosoft Word - 実験4_FPGA実験2_2015
FPGA の実験 Ⅱ 1. 目的 (1)FPGA を用いて組合せ回路や順序回路を設計する方法を理解する (2) スイッチや表示器の動作を理解し 入出力信号を正しく扱う 2. スケジュール項目 FPGAの実験 Ⅱ( その1) FPGAの実験 Ⅱ( その2) FPGAの実験 Ⅱ( その3) FPGAの実験 Ⅱ( その4) FPGAの実験 Ⅱ( その5) FPGAの実験 Ⅱ( その6) FPGAの実験 Ⅱ(
More information