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1 LMS FPGA
2 MMSE( Minimum Mean Square Error) MMSE LMS( Least Mean Square), RLS( Recursive Least Mean) ( ) LMS, N-LMS( Normalized - LMS) FPGA( Field Programmable Gate Array) FPGA, 2 FPGA N-LMS 2 FPGA RLS LMS, N-LMS RLS i
3 MMSE LMS N-LMS RLS FPGA LMS, N-LMS LMS N-LMS FPGA FPGA LMS N-LMS ii
4 31 32 iii
5 1 1.1 ) ) [1] 1.1: MMSE(Minimum Mean Square Error) 1
6 MMSE LMS (Least Mean Square) 2 RLS (Recursive Least-Squares) LMS N-LMS(Normalized - LMS) RLS 1.2 LMS, N-LMS, RLS FPGA 1.2: MMSE LMS, N-LMS FPGA (Field Programmable Gate Array) FPGA 2 FPGA 2
7 N-LMS 2 FPGA 2 (LMS, N-LMS), (RLS) 3
8 1.2 K (). () θ. E 0 (t) k. E k (t) = E 0 (t τ k ) (k =1, 2,..., K) (1.1) τ k = d k sin θ (1.2) c c d k k. d K d 1 f 2π f d K d 1 c 1 (1.3) f E 0 (t τ k ) = E 0 (t) exp( j2πfτ k ). (1.1) k. λ = c/f. E k (t) = E 0 (t) exp( j2πfτ k ) (1.4) = E 0 (t) exp( j2πf d k sin θ) c (1.5) = E 0 (t) exp( j 2π λ d k sin θ) (1.6) 4
9 (c: ) dksin = c k dk dk #K #k #1 d1 AK Ak A1 K k 1.3: K 1.3 () E sum (t) E sum (t) = K E 0 (t) A k exp( j2πf d k k=1 c sin θ + jδ k) (1.7) = E 0 (t)d(θ, f) (1.8) D(θ, f) = K k=1 A k exp{ j(2πf d k c sin θ δ k)} (1.9). A k δ k k ( ). δ k θ 0 ( ) δ k =2πf d k c sin θ 0 = 2π λ d k sin θ 0 (1.10).. 5
10 .. d k 2πf d k c sin θ gm δ k =2mπ (m = ±1, ±2,...) (1.11) θ gm ( θ 0 ). (grating lobe). (1.9) D(θ, f) θ (main lobe). (side lobe). (null). (1.7) A k δ k... (1.4). (adaptive beamforming) (adaptive null-steering)..... ( ).. 1) 2 (Minimum Mean Square Error : MMSE) 2) SNR (Maximum Signal-to-Noise ratio : MSN) 3) (Constrained Minimization of Power : CMP) 6
11 4) (Constant Modulus Algorithm : CMA) (). MMSE. w1 w2 wm 1.4: 7
12 1.3 MMSE MMSE ( ) ( 1.5) ( ) e(t) ( )r(t) y(t) e(t) =r(t) y(t) =r(t) w H x(t) (1.12) 2 ( 2 ). E[ e(t) 2 ] = E[ r(t) y(t) 2 ]=E[ r(t) w H x(t) 2 ] = E[ r(t) 2 ] w T r xr wh r xr + w H R xx w (1.13) R xx = E{x(t)x H (t)} (1.14) r xr = E[x(t)r (t)] (1.15) R xx r xr MMSE w (1.13) 2 8
13 x1(t) x2(t) w1 w2 y(t) xm(t) wm e(t) r(t) 1.5: MMSE (1.13) w 2 R xx 2 w ( ) (1.13) w E[ e(t) 2 ] = 0 (1.16) w E[ e(t) 2 ] 2 w opt w E[ e(t) 2 ]= 2r rx +2R xx w (1.17) w opt = R 1 xx r xr (1.18) R xx (1.18) (1.13) 2 E[ e(t) 2 min ] = E[ r(t) 2 ] w T opt r xr wh opt r xr + w H opt R xxw opt (1.19) = E[ r(t) 2 ] r H xr R 1 xx r xr (1.20) 9
14 (1.18) MMSE. (1.14) (1.15) LMS (Least Mean Square) SMI (Sample Matrix Inversion) 2 RLS (Recursive Least-Squares)... () [2]. SMI.SMI. SMI RLS.RLS SMI LMS W(m +1)=W(m)+ µ 2 WE[ e(m) 2 ] (1.21) µ (1.17) W E[ e(m) 2 ] W E[ e(m) 2 ] = 2r xd +2R xx W(m) = 2E[X(m)r (m)] + 2E[X(m)X H (m)]w(m) = 2E[X(m){r (m) X H (m)w(m)}] = 2E[X(m){r (m) y (m)}] = 2E[X(m)e (m)] (1.22) (1.21) W(m +1)=W(m)+µE[Xe (m)] (1.23) 10
15 W(m +1)=W(m)+µE[X(m)e (m)] (1.24) µ 0 <µ< 1 λ max (1.25) λ max R xx N-LMS Normalized LMS(N-LMS) LMS (1.26) [3] LMS NLMS [4]. µ = µ 0 x(m) 2 (1.26) RLS RLS SMI RLS n E(n) = α n i e(i) 2 (1.27) i=1 e(i) =r(i) y(i) =r(i) w H (n)x(i) (1.28) α 0 <α 1 (1.27) W R xx (n) = m α m i x(i)x H (i) (1.29) i=1 11
16 r xr (n) = m α m i x(i)y (i) (1.30) i=1 SMI RLS W(m +1) = W(m)+ γr xx (m) 1 X(m +1)e (m +1), (1.31) R xx (m) = αr xx (m 1) + X(m)X H (m), (1.32) γ = 1 α + X H (m +1)R xx (m) 1 X(m +1), (1.33) R 1 (0) = I/δ(δ ) RLS 12
17 1.4 FPGA FPGA( Feild Programmable Gate Array) FPGA : FPGA 13
18 2 LMS, N-LMS FPGA LMS, N-LMS 2.1 LMS RF( Radio Frequency) DBF IF IF A/D IF FPGA ( DDC) I, Q( in-phase,quadrature-phase) CPU( Central Processing unit) LMS x r 2.1 A/D
19 12r 12 A/D AGC( Automatic Gain Control) w #1 A/D DDC / Decimation RAM #2 #3 #4 Receiver A/D A/D DDC / Decimation DDC / Decimation DDC / A/D Decimation RF IF BB RAM RAM RAM Y(t) A/D BOARD LMS, N-LMS Ethernet CPU BOARD SH4 CPU 2.1: W X b [bit] b 1 Xe W r y e b [ bit] 2 2.2: LMS SNR 5,10,20 LMS 15
20 (MSE) MSE 2.1: 4 (λ/2) 2 30, 60 D/U 0[dB] SNR 5,10,20[dB] µ=0.125, 0.250, 0.500(= 1 2, 1 1 2, ) SNR SNR 5dB 20dB SNR 20dB MSE SNR 20[dB] µ=0.125, 0.250, 0.500(= 1, 1, 1 ) MSE LMS
21 stedt-state MSE [db] SNR[dB] fixed floating wor d length [bit] 2.3: (SNR) stedt-state MSE [db] - 21 µ fixed floating wor d length [bit] 2.4: ( ) 17
22 2.1.2 X, W, r (1.23) (1.23) w x e x m[bit] n[bit] =m n[bit] (2.1) y, xe b 1,b LMS MSE MSE b 1 b 1 b 2 b 1, b 2 16,5 y x e Mean Square Error[dB] b 2 [bit] b [bit] : 18
23 2.2 N-LMS N-LMS 2.6 (1.26) X 2 2 n (2 n 1 X 2 < 2 n +2 n 1 ) 2 n+1 (2 n +2 n 1 X 2 < 2 n+1 ). (2.2) n n< N-LMS 2.7 W X y e 2 Xe W S 2.6: NLMS ( ) W X y e Shift operation Xe W 2 S 2.7: NLMS ( ) 19
24 2.2.2 LMS X r 12 w 3.2 SNR =20dB µ 0 =0.25(= 1 ) 2 2 µ 0 =0.25(= 1 ) 2 2 µ 0 =0.25(= 1 ) µ 0 =0.25(= 1 ) w x e x x 3 wx, xe, x 2 b 1, b 2, b MSE x 2 x 2 b 3 11 x 2 x 2 (2.2) b 3 11bit LMS b 1, b 2 16, 4 20
25 stedt-state MSE [db] floating point fixed point(division) fixed point(bit-shift) wor d length [bit] 2.8: (N-LMS) stedt-state MSE [db] b1 [bit] b2 [bit] b3 [bit] floating divide bit-shift wor d length [bit] 2.9: (N-LMS) 21
26 3 FPGA 2 VHDL FPGA FPGA LMS 2 x s 12 w b 1 b 2 16, : LE [%] DSP Block [%] [MHz] [clk/iteration]
27 3.2: AD converter Resolution 12bit Sampling Rates 32MHz DA converter Resolution 14bit Sampling Rates 40MHz FPGA Altera Stratix EP1S25 600,000 Gates CPU Hitachi SH4 200MHz Operating System NetBSD Interface TCP/IP Ethrenet 100 BaseT N-LMS N-LMS 2.6, LMS : NLMS LE [%] DSP Block [%] [MHz] [clk/iteration] % 21.3% N-LMS FPGA RLS 3.4 [5] 23
28 3.4: LMS NLMS() NLMS() RLS LE [%] DSP Block( [%] [MHz] [clk/iterarion] [µs/iteration] LMS,NLMS,RLS LMS, N-LMS µ, µ 0 RLS λ LMS [µs] [6] 24
29 0 Mean Square Error[dB] Mean Square Error[dB] Time[µs] 3.1: 5[µs] Time[µs] 3.2: 25
30 3.2.2 M(Misadjustment) [6] 3.3 (3.1) W opt W opt = R xx r xr (3.1) R xr, r xr MSE MMSE (Excess MSE) ExcessMSE stedystate ExcessMSE stedy-state MSE MSE MMSE RLS λ = % LMS, N-LMS [7] M = average(mse MMSE) MMSE (3.2) Excess MSE 3.3: MMSE MSE 26
31 50 misadjustment [%] SNR [db] step size µ 3.4: (LMS) 50 misadjustment [%] SNR [db] : 5 : 10 : 20 divide bit-shift step size µ 3.5: (NLMS) 27
32 misadjustment[ % ] SNR [db] SIR [db] forgetting factor λ 3.6: (RLS) D/U=0[dB]SNR=5,10,20[dB] SINR 3.7, 3.8 SINR SNR LMS, N-LMS RLS 3.5 RLS SNR LMS SNR RLS [5] RLS 3.5: SNR LMS NLMS RLS 5 [db] [dB] [dB] [µs] 28
33 Mean Square Error [db] Output SINR [db] SNR=5dB LMS NLMS RLS SNR=10dB -25 SNR=20dB Time[ µ s] : SNR MSE SNR=10dB SNR=20dB 10 5 SNR=5dB LMS NLMS RLS Time[ s] 3.8: SNR SINR 29
34 4 MMSE LMS, N-LMS, RLS LMS, N-LMS FPGA N-LMS 1. LMS N-LMS LMS, N-LMS RLS LMS, N-LMS RLS 30
35 .. 31
36 [1] 1999 [2] N. Kikuma and K.Takao Effect of Initial Values od Adaptive Arrays, IEEE, Trans. Aerosp. Electron. Syst., vol. AES-22, no. 6, pp , Nov [3] M. Tarrab and A. Feuer, Convergence and Performance Analysis of the Normalized LMS Algorithm with Uncorrelated Gaussian Data, IEEE Trans. Signal Processing, Vol. 41, pp , [4] L. Godara Applications of Antenna Arrays to Mobile Communications, Part 2: Beam-Forming and Direction-of-Arraival Considerations, Proc. IEEE, vol. 85, no. 8, pp , Aug [5], RLS MMSE FPGA, IEICE Trans. Commun., Vol. J88-B, NO. 9, pp , Sep [6] W. A. Gardner and W. A. Brown, A new algorithm for adaptive arrays, IEEE Trans. Acoust. Speech, Signal Processing, Vol. ASSP-35, pp , [7] G. Manolakis, K. Ingle and M. Kogon, Statistical and Adaptive SIGNAL PROCESS- ING, Mc Graw Hill, [8] Dimitris G.Manolakis, Vinay K.Ingle, Stephen M.Kogon, Statistical and Adaptive SIGNAL PROCESSING, McGraw-Hill Higher Education pp [9] J. Winter, Smart Antennas for Wireless Systems, IEEE Personal Commun., vol. 5, no. 1, pp , Feb [10] L. Godara Applications of Antenna Arrays to Mobile Communications, Part 2: Beam-Forming and Direction-of-Arraival Considerations, Proc. IEEE, vol. 85, no. 8, pp , Aug
37 [11] C.Ward, P.Hargrave, J.G.McWhirter, A novel algorithm and architecture for adaptive digital beamforming, IEEE Trans. Antennas & Propag.,vol.AP-34, no.3, pp , 1986 [12] M.S.Kim, K.Ichige and H.Arai, Design of Jacobi EVD Processor Based on CORDIC for DOA Estimation with MUSIC Algorithm, IEICE Trans. Commun., vol.e85 B, no.12, pp , Dec, [13] M.Kim, A Study of Implementation of Digital Signal Processing for Adaptive Array Antenna, [14] [15] 15 2 [16] 16 2 [17] RLS FPGA [18] RLS FPGA
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+ From Tradeoffs of Receive and Transmit Equalization Architectures, ICC006,Bryan Casper, Intel Labs Transmitter Receiver 0 magnitude (db) 0 0 30 40 50 60 0 4 frequency (GHz). Receiver Transmitter FFE
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