ストリーミング SIMD 拡張命令2 (SSE2) を使用した SAXPY/DAXPY

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1 SIMD 2(SSE2) SAXPY/DAXPY : J /12/06 1

2 Fax: * Copyright Intel Corporation 1999, /12/06 2

3 SAXPY DAXPY SAXPY DAXPY SIMD C C/C C/C SSE2 C SSE A -... A-1... A-1... A-2 01/12/06 3

4 2.0 Pentium Lawson Hanson Kincaid Krogh Basic linear algebra subprograms for Fortran usage ACM Transactions on Mathematical Software Vol. 5 No Dongarra Moler Bunch Stewart LINPACK User's Guide SIAM 1979 C++ SIMD J 1999 C/C J /12/06 4

5 1 SIMD 2(SSE2 Streaming SIMD Extensions 2) SIMD(Single Instruction Multiple Data) SIMD IA-32 SIMD SIMD (SSE) SIMD 128 SIMD 64 SIMD 3D (3D) / SAXPY/DAXPY / SSE2 SSE Pentium 4 Pentium III SAXPY DAXPY SAXPY(DAXPY) SAXPY(DAXPY) ( ) (IA) SIMD SAXPY(DAXPY) SIMD C++ C/C SAXPY(DAXPY) C/C++ SIMD 2 SAXPY DAXPY SAXPY(DAXPY) Lawson Hanson Kincaid Krogh BLAS(Basic Linear Algebra Subprograms)[Lawson, 1979] SAXPY (SA) X Y DAXPY Y = a * X + Y X Y ( 1 n) a FORTRAN 01/12/06 5

6 CALL SAXPY (N, A, X, INCX, Y, INCY) N INCX INCY SAXPY X Y 2 INCX=INCY=1 LINPACK BLAS INCX=INCY=1 [Dongarra, 1979] LINPACK BLAS SAXPY DAXPY SIMD INCX=INCY=1 SAXPY DAXPY C SAXPY DAXPY SSE2 C/C++ C/C SIMD C++ SSE2 1 C/C SIMD C++ FVEC DVEC 16 float(double) F32vec4(F64vec2) x y F32vec4(F64vec2) y[i] = scalar * x[i] + y[i] 128 4(2) n 4(2) sa(da) 1 sa(da) 4(2) 1 16 float(double) F32vec4(F64vec2) x y 2 01/12/06 6

7 x y 1 C/C++ declspec ( C/C++ ) x y 2 if SAXPY(DAXPY) C/C++ 30 SAXPY(DAXPY) C/C++ /QxK /QxW SSE SSE2 /Qvec_verbose3 SAXPY(DAXPY) C/C++ SAXPY( DAXPY) C/C++ FORTRAN /Qvec_verbose3 2 ivdep pragma for pragma 4(2) vector aligned pragma C/C++ ivdep vector aligned 2 pragma SAXPY DAXPY pragma 1 C/C++ novector pragma 1 /QxW /QaxW /QxW SSE2( Pentium III ) Pentium 4 IA SSE2 /QaxW SSE2 2 1 /QxW 01/12/06 7

8 SSE2 1 /QxW SSE SSE2 FVEC(DVEC) SIMD C++ C/C++ FVEC(DVEC) ( ) C/C++ SSE SSE2 (SSE 4 SSE2 2 ) SAXPY SSE 4 Pentium 4 Pentium III 2 SSE DAXPY SSE2 4 SSE SSE2 SIMD 2 (1)SIMD C++ ( C/C++ ) (2) C/C++ pragma Itanium TM (2) 01/12/06 8

9 5 C/C++ * *Saxpy from BLAS, Lawson, Manson, Kincaid, and Krogh (1979) * *this compilation from _Linpack Users' Guide_, Dongarra, Moler, * Bunch, & Stewart, Siam 1979, appendix A. * *These versions are "unit" saxpy (daxpy), meaning they assume stride = 1. *(note that this is what BLAS requires, and is the most common form) * * Assume all vectors are aligned. * */ void usaxpy (int n, float sa, float *sx, float *sy) { if (sa == 0.0) return; } //The latest intel compilers can now vectorize this loop. //Use the novector pragma to prevent vectorization. #pragma novector for (int i = 0; i < n; i++) sy[i] = sa * sx[i] + sy[i]; void udaxpy (int n, double da, double *dx, double *dy) { if (da == 0.0) return; //The latest intel compilers can now vectorize this loop. //Use the novector pragma to prevent vectorization. #pragma novector for (int i = 0; i < n; i++) dy[i] = da * dx[i] + dy[i]; } 01/12/06 9

10 6 SSE2 C++ /* Assumes vectors are aligned, and that the vector length n is divisible * by 4 for saxpy and 2 for daxpy. */ #include <fvec.h> #include <dvec.h> void usaxpy_fvec (int n, float sa, float *sx, float *sy) { F32vec4 *x = (F32vec4 *)sx, *y = (F32vec4 *)sy; F32vec4 a(sa); if (sa == 0.0) return; n >>= 2; for (int i = 0; i < n; i++) y[i] = a * x[i] + y[i]; } void udaxpy_dvec (int n, double da, double *dx, double *dy) { F64vec2 *x = (F64vec2 *) dx, *y = (F64vec2 *) dy; F64vec2 a(da); if (da == 0.0) return; n >>= 1; for (int i = 0; i < n; i++) y[i] = a * x[i] + y[i]; } 01/12/06 10

11 7 SSE2 /* Assumes vectors are aligned */ void usaxpy_vec (int n, float sa, float *sx, float *sy) { if (sa == 0.0) return; #pragma ivdep #pragma vector aligned for (int i = 0; i < n; i++) sy[i] = sa * sx[i] + sy[i]; } void udaxpy_vec (int n, double da, double *dx, double *dy) { if (da == 0.0) return; #pragma ivdep #pragma vector aligned for (int i = 0; i < n; i++) dy[i] = da * dx[i] + dy[i]; } 01/12/06 11

12 A GHz Pentium :SAXPY/DAXPY ( MFLOPS) Pentium III (733 MHz) SAXPY: C SAXPY: FVEC SAXPY: DAXPY: C DAXPY: DVEC N/A 951 DAXPY: N/A 672 Pentium 4 (1.20 GHz) MHz Pentium III 1.20 GHz Pentium 4 A-2 2 ( ) FLOPS SAXPY SIMD (SSE) 4 Pentium III 2 Pentium SSE 1.9 GFLOPS DAXPY SSE MFLOPS DAXPY 1 SIMD 2 SAXPY 4 01/12/06 A-1

13 2: Pentium III Pentium III (733 MHz) Desktop Board VC820 BIOS VC82010A.86A.0028.P KB 128 MB RDRAM PC Ultra ATA IBM DJNA ATA-66 Creative Labs 3D Blaster Annihilator Pro AGP nvidia GeForce256 DDR 32MB Nvidia Reference Driver 5.22 Windows : Pentium 4 Pentium 4 (1.20 GHz) Desktop Board D850GB BIOS GB85010A.86A.0014.D KB 128 MB RDRAM PC Ultra ATA IBM DJNA ATA-66 / Creative Labs 3D Blaster Annihilator Pro AGP nvidia GeForce256 DDR 32MB NVidia Reference Driver 5.22 Windows /12/06 A-2

ストリーミング SIMD 拡張命令2 (SSE2) を使用した、倍精度浮動小数点ベクトルの最大/最小要素とそのインデックスの検出

ストリーミング SIMD 拡張命令2 (SSE2) を使用した、倍精度浮動小数点ベクトルの最大/最小要素とそのインデックスの検出 SIMD 2(SSE2) / 2.0 2000 7 : 248602J-001 01/10/30 1 305-8603 115 Fax: 0120-47-8832 * Copyright Intel Corporation 1999-2001 01/10/30 2 1...5 2...5 2.1...5 2.1.1...5 2.1.2...8 3...9 3.1...9 3.2...9 4...9