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1
2 ? FPGA FPGA FPGA : : :
3 ? ( ) (FFT) ( ) (Localization)
4 ? : ( )
5 ? : LU Ax = b LU : Ax = x 1 x 2 x 3 = x = LUx = b : y Ux Ly = b Ux = y (Matrix) Local ( )
6 ? : F = W W 2 W N 1 1 W 2 W 4 W 2N W N 1 W 2N 2 W (N 1)(N 1) O(n 2 ) O(n log n), W n = 1
7 ? : : CPU : L, C, R OP,.. :
8 ? Problem Structure Operation Algorithm Hardware Topology Dynamics : : CPU :
9 ? CPU Memory Instruction/Data Bus : : (Field Programmable Gate Array) ( )
10 FPGA? FPGA FPGA FPGA FPGA
11 FPGA : CMOS CMOS MOS A A A A NAND(A,B) B NOR(A,B) B Inverter NAND NOR
12 PLA X FPGA PLA (Programmable Logic Arrays) AND OR A B C D X=AB+ACD
13 FPGA FPGA LUT(Look Up Table) A B LUT (SRAM) NAND(A,B) AB 1 A B AB AB 1 1 OUT CMOS NAND AB 0 LUT
14 FPGA FPGA Logic Cell[LUT( ), FF( )] Matrix Logic Cell Logic Cell Logic Cell Logic Cell SW Logic Cell Logic Cell Logic Cell SW SW Logic Cell Logic Cell Logic Cell Logic Cell SW
15 FPGA 1. (Hardware Description Language) FPGA FPGA 5. FPGA
16 FPGA HDL (Hardware Description Language) HDL: Verilog-HDL, VHDL, SFL : 4 Verilog module count(out, ck); output [3:0] out; input ck; reg [3:0] q; ck) begin q <= q+1; end assign out = q; endmodule
17 FPGA HDL (VCS ) module testcount; wire [3:0] out; reg ck; initial begin ck <= 0; #200 $finish; end always #10 begin ck <= ck; end count inst0 (out, ck); endmodule ck out[3] out[2] out[1] out[0]
18 FPGA (FPGA Express ) FPGA FPGA JTAG ROM
19 FPGA PCI PCI FPGA CPU Memory PCI Bridge FPGA board
20 FPGA FPGA 1 1 ( )
21 FPGA 1 FPGA CPU FPGA CPU
22 FPGA Web
23 ? FPGA
24 integers binary codes Gray codes
25 1 1 2
26 x B= y =0.... B x G= y G= bit 3 bit 2 bit 1 bit 3 bit 2 bit bit 0 bit 0 0 1/4 1/2 3/4 1 Binary code 2 0 1/4 1/2 3/4 1 Gray code
27 ( )
28 a b G G Gray Code Adder.1000 c G 0.1 [0.1, 0.2]
29 2 1 2
30 Why Gray codes? 1/2 [ 1 X = 2 ε 1, 1 ] 2 + ε 2, ε 1,ε 2 > 0 X B=0. X G= bit 3 bit 2 bit 1 bit 3 bit 2 bit bit 0 bit 0 0 1/4 1/2 3/4 1 Binary code 1 0 1/4 1/2 3/4 1 Gray code 1
31 x G x G X = [X, X] = [x 1, x + 1] 2 n x x : (integer), n x : (integer) x = 0. G left 0 1/4 1/2 3/4 1 right center x G= 0.0 x G= 0. 1 x G= /4 1/2 3/ /4 1/2 3/ /4 1/2 3/4 1
32 a G b G = c G a G A, b G B c G C A B C A B A B C a G, b G = A, B = A B C = c G
33 d, d ( ) d = 2 n c A B C ( ) d = 2 n c C A B C d2 -n c A B d2 -n c A B A B, C d, d C A B conditions c G d d d 1, left 1 := P c d := 2d d := 2(d 1) d 1, right 1 := P c d := 2(d 1) d := 2d d 1 / 2 d 1 / 2, center 2 := 1, 0 d := 2(d 1 / 2 ) d := 2(d 1 / 2 ) P c = i b 1 j= c j (i b = 1 ) C
34 ? FPGA
35 : : xy = 1 y = 1/x : x 2 + y 2 2 = 0, xy 1 = 0 x 4 + 2x 2 1 = 0, x 3 2x + y = 0
36 Ax = y x y y x a 11 a 12 a 1n a 21 a 22 a 2n.... a n1 a n2 a nn x 1 x 2. x n = y 1 y 2. y n LU L 1 u 11 u 12 u 1n 0 a 22 u 2n u nn x 1 x 2. x n = l l 21 l l n1 l n2 l nn y 1 y 2. y n x y y x
37 y(t) = t 0 g(t τ)x(τ)dτ x(t) y(t) y(t) x(t) Y(s) = G(s)X(s), G(s) 1 Y(s) = X(s) X(s) Y(s) Y(s) X(s)?
38 F(s) = = 0 0 f (t)e st dt f (t)e at e jωt dt f (t) e at (s = a + jω) :?
39 f (t) = L 1 [F(s)](t) = 1 2πj a+j a j F(s)e st ds s:, f (t):, F(s): = Bromwich ε FFT
40 1/ s f N (t) FFT-Based square wave f N (t) FFT-Based 1/ πt F(s) = t 1 s(1 + e 0.1s ) F(s) = 1 s t
41 F(s) G(s) t F(s) G(s) FFT-Based g N(hn) T T -1 inversion ^ N f (hn) T s T 1 t
42 s f (t) = L 1 [F(s)] = L 1 [s i F(s) s i ] = di dt i L 1 [ F(s) s i ] = s i + t i s domain t domain Conventional method F(s) FFT-Based inversion f (hn) N Proposed method F(s) 1 si i-th integral G(s) FFT-Based inversion g N (hn) i d dt i-th differential i ^ N f (hn)
43 1/ s f N (t) FFT-Based square wave Proposed (i=4) f N (t) FFT-Based 1/ πt Proposed (i=4) F(s) = t 1 s(1 + e 0.1s ) F(s) = 1 s t
44 ? FPGA
45 (SFQ)
46 A A B B A B A B A B
47 : z = f (w 1 x 1 + w 2 x 2 + w n x n θ) x x x 1 2 w w w 3 3 θ x n 2 w n 1 z 1 0 f
48
49 (CML) A OUT OUT B A B CML ExOR
50 (Exp ) O1 O2 X1 X2 Y1 Y2
51 : (TDM, FDM, CDM, SDM,...) : FPGA V(t) A B C D 0 90 V(t) A B C D
52 ? :? A NOT B A B AND C A B OR C NOT A B AND A B C OR A B C
53 ? :? CMOS : : IN OUT IN / OUT OUT / IN CMOS inverter Pass-transistor
54 ? a + b = c. a b, c = a + b b c, a = c b
55 A B A B A B A B C A B C A B C
56 AND A B AND C Z (a) (b) (c) Input Input Output Input Input Output Input Input Output A B C A C B B C A Z Z Z Z Z Z Z Z Z Z 0 0 Z 0 Z Z 0 Z Z 1 Z Z 1 1 Z Z 0 0 Z Z 0 Z Z Z 0 0 Z Z Z 1 Z Z 1 Z Z
57 2 : X=1 X=0 (X,X)=(1,0) (X,X)=(0,1). : (X,X) = (0,0). A B A B : IN / OUT OUT / IN
58 Expression of the unfixed bit Two-way circuit 0, 1, Z OUT OUT open pull down (V) OUT OUT Z 0 0
59 ExOR A =0 B C A=1 B C A, B and C Gate control Signal flow B B B B A A BBCC A A A A C C C C B C C ExOR B (a) (b) Input Input Output A A B B C C
60 AND A = 1 B C A = 0 A C C=1, A, B A A B B C C A A B B C AND C
61 A, B, C, S and C +. A, C, S, B. C+ C+ carry out a n b n FA(n) s n+1 sn c2 A A B B Reversible ExOR C C Reversible ExOR carry in sum S S a 1 b1 a 0 b 0 FA(1) c 1 FA(0) c 0 = 0 s 1 s 0 n-bit
62 2 2bit c 0 = a 0 b 0, c 1 = a 1 b 0 a 0 b 1, c 2 = a 1 b 1 (a 1 b 0 a 0 b 1 ), c 3 = a 1 b 1 a 1 b 0 a 0 b 1. A a 1 a 0 B b 1 b 0 Two-way AND a 1 b 1 a 0 b 1 a 1 b 0 a 0 b 0 Reversible ExOR 2 2 bit Reversible ExOR buffer C c 3 c 2 c 1 c 0 carry out carry out augend FA sum augend HA sum carry in addend addend a 2 b 2 FA a 1 b 2 FA HA a 2 b 1 a 0 b 2 a 0 b 1 a 0 b 0 a 1 b HA 1 FA a 2 b 0 HA a 1 b 0 c 5 c 4 c 3 c 2 c 1 c bit
63
Verilog HDL による回路設計記述
Verilog HDL 3 2019 4 1 / 24 ( ) (RTL) (HDL) RTL HDL アルゴリズム 動作合成 論理合成 論理回路 配置 配線 ハードウェア記述言語 シミュレーション レイアウト 2 / 24 HDL VHDL: IEEE Std 1076-1987 Ada IEEE Std 1164-1991 Verilog HDL: 1984 IEEE Std 1364-1995
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