HN58X2502/HN58X2504I

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1 お客様各位カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NE エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し両社の全ての事業が当社に承継されております従いまして本資料中には旧社名での表記が残っておりますが当社の資料として有効ですのでご理解の程宜しくお願い申し上げますルネサスエレクトロニクスホームページ ( 発行ルネサスエレクトロニクス株式会社 ( 問い合わせ先 Not recommend for new design 2010 年 4 月 1 日ルネサスエレクトロニクス株式会社

2 Not recommend OA AV RoH for new design

3 erial Peripheral Interface 2k EEPROM (256-word 8-bit) 4k EEPROM (512-word 8-bit) Electrically Erasable and Programmable Read Only Memory RJJ Rev HN58X25xxx EEPROM ROM MONO MO V 5.5V PI PI 0 (0, 0) 3 (1, 1) 5MHz 5.5V) 3MHz (2.5V (1.8V 5.5V) 3 µa (max) 2mA (max) 2.5mA (max) 16 5ms ) (2.5V / 8ms (1.8V ) OP8 TOP8 TOP8 3000I/real OP8 2500I/real Type No. Internal organization Operating voltage Frequency Package HN58X2502FPIE 2k bit (256 8-bit ) HN58X2504FPIE HN58X2502TIE HN58X2504TIE 4k bit (512 8-bit ) 2k bit (256 8-bit ) 4k bit (512 8-bit ) 1.8 V to 5.5 V 1.8 V to 5.5 V 5 MHz (2.5 V to 5.5 V) 3 MHz (1.8 V to 5.5 V) 5 MHz (2.5 V to 5.5 V) 3 MHz (1.8 V to 5.5 V) 150mil 8-pin plastic OP PRP0008F-B (FP-8BV) 8-pin plastic TOP PTP0008J-B (TTP-8AV) Rev.2.00, , page 1 of 18

4 8-pin OP/TOP 1 8 V 2 7 HOL W 3 6 V 4 5 (Top view) Pin name W HOL V V Function erial clock erial data input erial data output hip select Write protect Hold upply voltage Ground High voltage generator V V W HOL ontrol logic Address generator X decoder Y decoder Memory array Y-select & ense amp. erial-parallel converter Rev.2.00, , page 2 of 18

5 Parameter ymbol Value Unit upply voltage relative to V V 0.6 to +7.0 V Input voltage relative to V V IN 0.5* 2 to +7.0* 3 V Operating temperature range* 1 Topr 40 to +85 torage temperature range Tstg 65 to ns 3.0V 3. V +1.0 Parameter ymbol Min Typ Max Unit upply voltage V V V V Input voltage V 0.7 V + 0.5* 2 V 0.3* 1 V 0.3 V Operating temperature range Topr ns 1.0V 2. 50ns V + 1.0V Parameter ymbol Min Max Unit Test conditions Input leakage current I LI 2 µa V = 5.5V, V IN = 0 to 5.5V (,,, HOL, W) Output leakage current I LO 2 µa V = 5.5V, V OUT = 0 to 5.5V () V current tandby I B 3 µa V IN = V or V, V = 5.5V Active I 1 2 ma V = 5.5V, Read at 5MHz V IN = V 0.1 /V 0.9 = OPEN I ma V = 5.5V, Write at 5MHz V IN = V 0.1/V 0.9 Output voltage V OL1 0.4 V V = 5.5V, I OL = 2mA V OL2 0.4 V V = 2.5V, I OL = 1.5mA V OH1 V 0.8 V V = 5.5V, I OL = 2mA V OH2 V 0.8 V V = 2.5V, I OL = 0.4mA Rev.2.00, , page 3 of 18

6 A V IL = V 0.2 = V 0.8 / 10ns 100pF V 0.3, V 0.7 V Ta= V =2.5V 5.5V Parameter ymbol Alt Min Max Unit Notes lock frequency f f K 5 MHz active setup time t LH t 1 90 ns not active setup time t HH t 2 90 ns deselect time t HL t 90 ns active hold time t HH t H 90 ns not active hold time t HL 90 ns lock high time t H t LH 90 ns 1 lock low time t L t LL 90 ns 1 lock rise time t LH t R 1 µs 2 lock fall time t HL t F 1 µs 2 ata in setup time t VH t U 20 ns ata in hold time t HX t H 30 ns lock low hold time after HOL not active t HHH 70 ns lock low hold time after HOL active t HLH 40 ns lock high setup time before HOL active t HHL 60 ns lock high setup time before HOL not active t HHH 60 ns Output disable time t HZ t I 100 ns 2 lock low to output valid t LV t V 70 ns Output hold time t LX t HO 0 ns Output rise time t LH t RO 50 ns 2 Output fall time t HL t FO 50 ns 2 HOL high to output low-z t HHX t LZ 50 ns 2 HOL low to output high-z t HLZ t HZ 100 ns 2 Write time t W t W 5 ms Erase / Write Endurance 10 6 cycles 3 H 1. + t L t 1/f 3. Ta=25 Rev.2.00, , page 4 of 18

7 Ta= V =1.8V 5.5V Parameter ymbol Alt Min Max Unit Notes lock frequency f f K 3 MHz active setup time t LH t ns not active setup time t HH t ns deselect time t HL t 150 ns active hold time t HH t H 100 ns not active hold time t HL 100 ns lock high time t H t LH 150 ns 1 lock low time t L t LL 150 ns 1 lock rise time t LH t R 1 µs 2 lock fall time t HL t F 1 µs 2 ata in setup time t VH t U 30 ns ata in hold time t HX t H 50 ns lock low hold time after HOL not active t HHH 140 ns lock low hold time after HOL active t HLH 90 ns lock high setup time before HOL active t HHL 120 ns lock high setup time before HOL not active t HHH 120 ns Output disable time t HZ t I 200 ns 2 lock low to output valid t LV t V 120 ns Output hold time t LX t HO 0 ns Output rise time t LH t RO 100 ns 2 Output fall time t HL t FO 100 ns 2 HOL high to output low-z t HHX t LZ 100 ns 2 HOL low to output high-z t HLZ t HZ 100 ns 2 Write time t W t W 8 ms 2. Erase / Write Endurance 10 6 cycles 3 H 1. + t L t 1/f 3. Ta=25 Rev.2.00, , page 5 of 18

8 erial Input Timing t HL t HL t LH t HH t HH t VH t HX t LH t HL MB IN LB IN High Impedance Hold Timing t HLH t HHH t HHL t HHH t HLZ t HHX HOL Output Timing th t HZ t L AR LB IN t LV t LX t LX t LV LB OUT t LH t HL Rev.2.00, , page 6 of 18

9 High-Z L HOL High-Z on t are ) L W ( W) L WRITE Rev.2.00, , page 7 of 18

10 b7 b BP1 BP0 WEL WIP Block Protect Bits Write Enable Latch Bits Write In Progress Bits WIP Bit WEL Bit Write Enable Latch BP0, BP1 Bit Block Protect BP0, BP1 Block Protect OFF 1 Instruction et Instruction escription Instruction format WREN Write Enable 0000 X110 WRI Write isable 0000 X100 RR Read tatus Register 0000 X101 WRR Write tatus Register 0000 X001 REA Read from Memory Array 0000 A011 WRITE Write to Memory Array 0000 A X 2. A HN58X2504I A 8 Rev.2.00, , page 8 of 18

11 Write Enable (WREN) WRR) Write (WRITE Enable Latch (WEL) WEL ) ( () WEL WREN W Instruction 7 High-Z Rev.2.00, , page 9 of 18

12 Write isable (WRI) WRI WEL ) () WEL WEL WRI WRR WRITE ( W)L WRI W Instruction High-Z Rev.2.00, , page 10 of 18

13 REA tatus Register (RR) RR WIP RR W High-Z tatus Register Out WIP bit WIP Write Write tatus Register 1 0 WEL bit WEL Write Enable Latch 1 Write Enable Latch 0 Write Enable Latch Write Write tatus Register BP1, BP0 bit Block Protect Write to Memory Array (WRITE) Write tatus Register (WRR) Block Protect Write to Memory Array (WRITE) Rev.2.00, , page 11 of 18

14 WRITE tatus Register (WRR) WRR (BP1, BP0) WRR WREN WEL WRR WRR b7, b6, b5, b4, b1 b0 b7, b6, b5, b4 1 ( ) L ) H ( WRR W) WRR (t WIP WIP 1 WRR 0 WEL WRR BP0, BP1 BP0, BP1 WRR WRR WRR WEL 1 WRITE ( W)L WRR W tatus Register In 7 MB High-Z Rev.2.00, , page 12 of 18

15 Read from Memory Array (REA) REA ) L ( () ()(A8) 5 bit L 8 0 H REA REA W Instruction Bit Address A8 A7 A6 A5 A3 A2 A1 A0 High-Z ata Out 1 ata Out on t care evice HN58X2504I HN58X2502I Address bits A8 to A0 A7 to A0 1. The most significant address bit are on t are on the HN58X2502 Rev.2.00, , page 13 of 18

16 Write to Memory Array (WRITE) WRITE ) L ( () H WRITE W) (t 8 WIP 0 WRITE (Page) L WEL 1 WRITE BP0, BP1 ( W)L WRITE (1Byte) W Instruction Bit Address ata Byte 1 A8 A7 A6 A5 A3 A2 A1 A High-Z 1. on t care Rev.2.00, , page 14 of 18

17 WRITE (Page) W Instruction Bit Address ata Byte 1 A8 A7 A6 A5 A3 A2 A1 A High-Z W ata Byte ata Byte 3 ata Byte N High-Z 1. on t care Rev.2.00, , page 15 of 18

18 bit (BP1, BP0) 1/2 1/4 ( W)L WRITE, WRR WELbit tatus register bits Array addresses protected BP1 BP0 Protected blocks HN58X2504I HN58X2502I 0 0 None None None 0 1 Upper quarter 180h 1FFh 0h FFh 1 0 Upper half 100h 1FFh 80h FFh 1 1 Whole memory 000h 1FFh 00h FFh High-Z ) L ( L HOL) () HOL) ( H HOL) ( H () HOL) L ( L ( HOL) L HOL status HOL status HOL On/Off Power On Reset On/Off ) V ( On/Off On On 0V On 10µs/V WRR WRITE W) Rev.2.00, , page 16 of 18

19 E HN58X2502FPIE/HN58X2504FPIE (PRP0008F-B / Previous ode: FP-8BV) JEITA Package ode P-OP8-3.9x RENEA ode PRP0008F-B Previous ode FP-8BV MA[Typ.] 0.08g *1 8 5 F bp *2 c E H 1 NOTE) 1. IMENION"*1 (Nom)"AN"*2" O NOT INLUE MOL FLAH. 2. IMENION"*3"OE NOT INLUE TRIM OFFET. Index mark Z 1 e 4 *3 b p x M Terminal cross section ( Ni/Pd/Au plating ) L1 Reference ymbol E A 2 A 1 A b p b 1 imension in Millimeters Min Nom Max c c 1 A θ 0 8 H E θ e 1.27 A L x 0.25 y etail F y Z L L Rev.2.00, , page 17 of 18

20 E HN58X2502TIE/HN58X2504TIE (PTP0008J-B / Previous ode: TTP-8AV) JEITA Package ode P-TOP8-4.4x RENEA ode PTP0008J-B Previous ode TTP-8AV MA[Typ.] 0.034g *1 F 8 5 Index mark Reference ymbol E A 2 A 1 imension in Millimeters Min Nom Max A b p e *3 b p *2 E H 1 NOTE) 1. IMENION"*1 (Nom)"AN"*2" O NOT INLUE MOL FLAH. 2. IMENION"*3"OE NOT INLUE TRIM OFFET. b p c Terminal cross section ( Ni/Pd/Au plating ) L 1 Z x M b 1 c c 1 θ H E A A L θ e x y etail F y Z L L Rev.2.00, , page 18 of 18

21 Rev I 1 max 3.5mA 2mA I 2 max 3.5mA 2.5mA ON TNP-8A HN58X2502FPI HN58X2504FPI HN58X2502TI HN58X2504TI HN58X2502FPIE HN58X2504FPIE HN58X2502TIE HN58X2504TIE FP-8B FP-8BV TTP-8 TTP-8AV A Erase / Write Endurance 3

100-0004 2-6-2 1. 1. 2. 3. (http://www.renesas.

com 100-0004 212-0058 190-0023 980-0013 970-8026 312-0034 950-0087 390-0815 460-0008 541-0044 920-0031 730-0036 680-0822 812-0011 2-6-2 ( ) 890-12 ( ) 2-2-23 ( 2F) 1-1-20

22 ( ( ) ( ) ( 2F) ( 13F) 4-9 ( ) ( 1F) (3F) ( 7F) ( ) ( ) ( 8F) 5-25 ( 8F) ( ) (5F) (03) (044) (042) (022) (0246) (029) (025) (0263) (052) (06) (076) (082) (0857) (092) csc@renesas.com Renesas Technology orp., All rights reserved. Printed in Japan. olophon 5.5

R1RW0408D シリーズ

R1RW0408D シリーズお客様各位カタログ等資料中の旧社名の扱いについて 2010 年 4 月 1 日を以って NEC エレクトロニクス株式会社及び株式会社ルネサステクノロジが合併し両社の全ての事業が当社に承継されております従いまして本資料中には旧社名での表記が残っておりますが当社の資料として有効ですのでご理解の程宜しくお願い申し上げますルネサスエレクトロニクスホームページ (http://www.renesas.com)