VHDL-AMS Department of Electrical Engineering, Doshisha University, Tatara, Kyotanabe, Kyoto, Japan TOYOTA Motor Corporation, Susono, Shizuok

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1 VHDL-AMS Department of Electrical Engineering, Doshisha University, Tatara, Kyotanabe, Kyoto, Japan TOYOTA Motor Corporation, Susono, Shizuoka, Japan kimitoshi MBD(MBD) (model description language) (multi-domain system)ad (AD mixed system) (international standard) (encryption specification) JL 0004/14/ C 2014 SICE 1. 1), 2) MBD(Model-Based Design or Development) () VHDL-AMS(Very-High Speed IC Hardware Description Language - Analog and Mixed Signal) 3)6) VHDL-AMS ) 3 4 IEEE IEC ), 4) 5 (implicit) VHDL-AMS 2. VHDL-AMS 2.1 VHDL-AMS f(x(t), ẋ(t),t)=0 (1) t x, ẋ () VHDL-AMS 1 1 (through) (across) 1 VHDL-AMS

2 2 VHDL-AMS VHDL-AMS VHDL 1 1 [A] [V] () [N] [m] () [N] [m/sec] () [Nm] [rad] () [Nm] [rad/sec] [W] [K] VHDL-AMS IC 1970 ASTAP SPICE 7), 8) MAST 9) 1990 ASIC VHDL IEEE MAST 1993 IEEE VHDL-AMS 2000 (VDA) (FAT-AK30 10) IEEE P VHDL-AMS VHDL-AMS 2 () (Branch quantity) (Free quantity) 2 (Interface Quantity) (in) (out) 1 VHDL VHDL-AMS (simultaneous statement)

3 1: library IEEE; 2: use IEEE.electrical systems.all; 3: entity resistor is 4: generic (R : real:=1.0); 5: port (terminal p, n : electrical); 6: end entity resistor; 7: artitecture behav of resistor is 8: quantity v across i through p to n; 9: begin 10: v = = R i; 11: end architecture behav; (a) VHDL-AMS 1: entity sum is 2: generic (k1 : real:=1.0); 3: generic (k2 : real:=1.0); 4: port (terminal in1, in2 : in real); 5: port (terminal output : out real); 6: end entity sum; 7: artitecture behav of sum is 8: begin 9: output = = k1*in1+k2*in2; 10: end architecture behav; 2 (b) VHDL-AMS VHDL-AMS == 3.2 VHDL-AMS 2 (a) 2 V A 3 6 entity generic R 1Ω port 2 (terminal) p, n (nature) 7 11 architecture quantity v i p n v==r i; == L[H] dot v==l i dot ; dot integ, above (attribute) VHDL-AMS 6) 2(b) 6 entity 2 in1, in2 output 9 output==k1*in1+k2*in2; VHDL-AMS VHDL 3) 4. EPS 4.1 EPS VHDL-AMS EPS EPS(Electric Power Steering) () () 3 EPS EPS

4 4 5 5 (a) (b) (a) (b) DC-DC 7 12V DC-DC 7 30Ah 12V 8 R 01,R 02 R 1,R 2 C 1,C 2 0V 30Ah R 01 =12.56 mωr mΩC F R 02 =9.3mΩR mΩ 1.0mΩ C FE 0 = V 4.4 ECU

5 6 7 12V (a) (b) 9 8 DLL (Dynamic Link Library) 5. 4 EPS Load 80D26 55Ah 30Ah 2 9 (a)

6 (a) U 11 1 (30Ah) (b) DCDC 12 EPS (c) (d) 10 9(b) (a) U DCDC 10 (b) 10 (c) 10 (d) V EPS VHDL-AMS EPS EPS 100A 50A 12 V V EPS 200 mv 55Ah 60Ah30Ah 2 12 V mv 1 EPS 705J 269J38%

() VHDL-AMS VHDL-AMS VHDL-AMS EPS 2013 12 24 1 T. Kato, K. Tsuji, and S.

Kato: The VHDL-AMS hv full vehicle simulation model for the concept planning of power performance and fuel economy estimation results, 7th IFAC Symposium on Advances in Automotive Control (2013) 3

7 () VHDL-AMS VHDL-AMS VHDL-AMS EPS T. Kato, K. Tsuji, and S. Shimada: Requirements to models of automotive system development for future model-based design, 7th IFAC Symposium on Advances in Automotive Control (2013) 2 K. Tsuji and T. Kato: The VHDL-AMS hv full vehicle simulation model for the concept planning of power performance and fuel economy estimation results, 7th IFAC Symposium on Advances in Automotive Control (2013) 3 VHDL Language Reference Manual, IEEE Standard, 1076/1987 ( ) 4 VHDL Analog and Mixed-Signal Extensions, IEEE Standard , IEC ( 2009) 5 E. Christen and K. Bakalar: VHDL-AMS - A hardware description language for analog and mixed-signal applications, IEEE Trans. Circuit and Systems II: Analog and Digital Signal Processing, 46 10, 1263/1272 (1999) 6 P.J. Ashenden, G.D. Peterson, and D.A. Teegarden: The System Designer s Guide to VHDL-AMS, Morgan Kaufmann Publishers (2003) 7 G.D. Hachtel, R. Brayton, and F.G. Gustavson: The sparse tableau approach to network analysis and design, IEEE Trans. Circuit Theory, CT-18, 101/113 (1971) 8 C. H. Ho, A. E. Ruehli, and P. A. Brennan: The Modified nodal approach to network analysis, IEEE Trans. Circuit and Systems, CAS-22, 504/509 (1975) 9 H.A. Mantooth and M. Fiegenbaum: Modeling with an Analog Hardware Description Language, Kluwer Academic Publishers (1995) 10 FAT-AK30 (Working Group: Simulation of Mixed Systems with VHDL-AMS); /index en.html IREQ MIT LEES

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starc_verilog_hdl pptx !!!!!!! ! 2.10.6.! RTL : 1! 1 2! 3.2.5.! : ! 1.7. FPGA 1 FPGA FPGA 1.5.2! 3.1.2.! 3! 3.3.1. DFT! LSI :! 2 : ! ON FPGA!!! FPGA! FPGA! !!!!! ! Verilog HDL 6 9 4! Xilinx ISE!!! RTL! CPU !! 20!! C! VHDL! Xilinx